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cxl: Configure PSL for kernel contexts and merge code 

This updates AFU directed and dedicated modes for contexts attached to the
kernel.

The SR (similar to the MSR in the core) calculation is getting
quite complex and is duplicated in AFU directed and dedicated
modes.  This patch also merges this SR calculation for these modes.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Acked-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Michael Neuling 2015-05-27 16:07:13 +10:00 committed by Michael Ellerman
parent c358d84b4e
commit 2f663527bd
1 changed files with 35 additions and 28 deletions
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63
drivers/misc/cxl/native.c
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@ -430,9 +430,30 @@ err:
#define set_endian(sr) ((sr) &= ~(CXL_PSL_SR_An_LE))
#endif
static u64 calculate_sr(struct cxl_context *ctx)
{
u64 sr = 0;
if (ctx->master)
sr |= CXL_PSL_SR_An_MP;
if (mfspr(SPRN_LPCR) & LPCR_TC)
sr |= CXL_PSL_SR_An_TC;
if (ctx->kernel) {
sr |= CXL_PSL_SR_An_R | (mfmsr() & MSR_SF);
sr |= CXL_PSL_SR_An_HV;
} else {
sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
set_endian(sr);
sr &= ~(CXL_PSL_SR_An_HV);
if (!test_tsk_thread_flag(current, TIF_32BIT))
sr |= CXL_PSL_SR_An_SF;
}
return sr;
}
static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr)
{
u64 sr;
u32 pid;
int r, result;
cxl_assign_psn_space(ctx);
@ -442,22 +463,13 @@ static int attach_afu_directed(struct cxl_context *ctx, u64 wed, u64 amr)
ctx->elem->haurp = 0; /* disable */
ctx->elem->sdr = cpu_to_be64(mfspr(SPRN_SDR1));
sr = 0;
if (ctx->master)
sr |= CXL_PSL_SR_An_MP;
if (mfspr(SPRN_LPCR) & LPCR_TC)
sr |= CXL_PSL_SR_An_TC;
/* HV=0, PR=1, R=1 for userspace
* For kernel contexts: this would need to change
*/
sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
set_endian(sr);
sr &= ~(CXL_PSL_SR_An_HV);
if (!test_tsk_thread_flag(current, TIF_32BIT))
sr |= CXL_PSL_SR_An_SF;
ctx->elem->common.pid = cpu_to_be32(current->pid);
pid = current->pid;
if (ctx->kernel)
pid = 0;
ctx->elem->common.tid = 0;
ctx->elem->sr = cpu_to_be64(sr);
ctx->elem->common.pid = cpu_to_be32(pid);
ctx->elem->sr = cpu_to_be64(calculate_sr(ctx));
ctx->elem->common.csrp = 0; /* disable */
ctx->elem->common.aurp0 = 0; /* disable */
@ -530,20 +542,15 @@ static int activate_dedicated_process(struct cxl_afu *afu)
static int attach_dedicated(struct cxl_context *ctx, u64 wed, u64 amr)
{
struct cxl_afu *afu = ctx->afu;
u64 sr;
u64 pid;
int rc;
sr = 0;
set_endian(sr);
if (ctx->master)
sr |= CXL_PSL_SR_An_MP;
if (mfspr(SPRN_LPCR) & LPCR_TC)
sr |= CXL_PSL_SR_An_TC;
sr |= CXL_PSL_SR_An_PR | CXL_PSL_SR_An_R;
if (!test_tsk_thread_flag(current, TIF_32BIT))
sr |= CXL_PSL_SR_An_SF;
cxl_p2n_write(afu, CXL_PSL_PID_TID_An, (u64)current->pid << 32);
cxl_p1n_write(afu, CXL_PSL_SR_An, sr);
pid = (u64)current->pid << 32;
if (ctx->kernel)
pid = 0;
cxl_p2n_write(afu, CXL_PSL_PID_TID_An, pid);
cxl_p1n_write(afu, CXL_PSL_SR_An, calculate_sr(ctx));
if ((rc = cxl_write_sstp(afu, ctx->sstp0, ctx->sstp1)))
return rc;