[ARM] iop13xx: msi support
Enable devices to signal interrupts via PCI memory cycles. rev6: * fix enable/disable typo, Michael Ellerman rev5: * fix up ack, enable, and disable for iop13xx_msi_chip rev4: * move smp compile fix to separate patch * use dynamic_irq_init in create_irq() * hookup mask/unmask routines in iop13xx_msi_chip rev3: * change msi.c to use linux/smp.h instead of asm/smp.h * call dynamic_irq_cleanup at destroy_irq time rev2: * destroy_irq did not take the full 128 bits of msi_irq_in_use into account * added missing '&' for calls to test_and_set_bit and clear_bit [ebiederm@xmission.com: review comments/suggestions] [dan.j.williams@intel.com: cleanups/forward port to 2.6-git] Signed-off-by: Daniel Wolstenholme <daniel.e.wolstenholme@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Acked-by: Eric W. Biederman <ebiederm@xmission.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Daniel Wolstenholme
Russell King
parent
87b247c416
commit
2fd0237538
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@ -10,3 +10,4 @@ obj-$(CONFIG_ARCH_IOP13XX) += io.o
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obj-$(CONFIG_ARCH_IOP13XX) += tpmi.o
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obj-$(CONFIG_MACH_IQ81340SC) += iq81340sc.o
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obj-$(CONFIG_MACH_IQ81340MC) += iq81340mc.o
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obj-$(CONFIG_PCI_MSI) += msi.o
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@ -26,6 +26,7 @@
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#include <asm/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/arch/irqs.h>
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#include <asm/arch/msi.h>
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/* INTCTL0 CP6 R0 Page 4
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*/
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@ -258,7 +259,7 @@ void __init iop13xx_init_irq(void)
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write_intbase(INTBASE);
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write_intsize(INTSIZE_4);
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for(i = 0; i < NR_IOP13XX_IRQS; i++) {
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for(i = 0; i <= IRQ_IOP13XX_HPI; i++) {
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if (i < 32)
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set_irq_chip(i, &iop13xx_irqchip1);
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else if (i < 64)
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@ -271,4 +272,6 @@ void __init iop13xx_init_irq(void)
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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iop13xx_msi_init();
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}
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@ -0,0 +1,194 @@
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/*
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* arch/arm/mach-iop13xx/msi.c
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*
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* PCI MSI support for the iop13xx processor
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*
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* Copyright (c) 2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#include <linux/pci.h>
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#include <linux/msi.h>
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#include <asm/mach/irq.h>
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#include <asm/irq.h>
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#define IOP13XX_NUM_MSI_IRQS 128
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static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS);
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/* IMIPR0 CP6 R8 Page 1
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*/
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static inline u32 read_imipr_0(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
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return val;
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}
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static inline void write_imipr_0(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
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}
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/* IMIPR1 CP6 R9 Page 1
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*/
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static inline u32 read_imipr_1(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
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return val;
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}
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static inline void write_imipr_1(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
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}
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/* IMIPR2 CP6 R10 Page 1
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*/
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static inline u32 read_imipr_2(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
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return val;
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}
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static inline void write_imipr_2(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
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}
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/* IMIPR3 CP6 R11 Page 1
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*/
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static inline u32 read_imipr_3(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
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return val;
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}
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static inline void write_imipr_3(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
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}
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static u32 (*read_imipr[])(void) = {
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read_imipr_0,
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read_imipr_1,
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read_imipr_2,
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read_imipr_3,
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};
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static void (*write_imipr[])(u32) = {
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write_imipr_0,
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write_imipr_1,
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write_imipr_2,
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write_imipr_3,
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};
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static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc)
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{
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int i, j;
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unsigned long status;
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/* read IMIPR registers and find any active interrupts,
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* then call ISR for each active interrupt
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*/
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for (i = 0; i < ARRAY_SIZE(read_imipr); i++) {
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status = (read_imipr[i])();
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if (!status)
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continue;
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do {
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j = find_first_bit(&status, 32);
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(write_imipr[i])(1 << j); /* write back to clear bit */
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desc = irq_desc + IRQ_IOP13XX_MSI_0 + j + (32*i);
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desc_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i), desc);
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status = (read_imipr[i])();
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} while (status);
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}
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}
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void __init iop13xx_msi_init(void)
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{
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set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
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}
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/*
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* Dynamic irq allocate and deallocation
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*/
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int create_irq(void)
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{
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int irq, pos;
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again:
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pos = find_first_zero_bit(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS);
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irq = IRQ_IOP13XX_MSI_0 + pos;
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if (irq > NR_IRQS)
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return -ENOSPC;
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/* test_and_set_bit operates on 32-bits at a time */
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if (test_and_set_bit(pos, msi_irq_in_use))
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goto again;
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dynamic_irq_init(irq);
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return irq;
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}
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void destroy_irq(unsigned int irq)
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{
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int pos = irq - IRQ_IOP13XX_MSI_0;
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dynamic_irq_cleanup(irq);
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clear_bit(pos, msi_irq_in_use);
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}
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void arch_teardown_msi_irq(unsigned int irq)
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{
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destroy_irq(irq);
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}
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static void iop13xx_msi_nop(unsigned int irq)
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{
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return;
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}
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static struct irq_chip iop13xx_msi_chip = {
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.name = "PCI-MSI",
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.ack = iop13xx_msi_nop,
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.enable = unmask_msi_irq,
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.disable = mask_msi_irq,
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.mask = mask_msi_irq,
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.unmask = unmask_msi_irq,
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};
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int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
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{
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int id, irq = create_irq();
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struct msi_msg msg;
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if (irq < 0)
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return irq;
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set_irq_msi(irq, desc);
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msg.address_hi = 0x0;
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msg.address_lo = IOP13XX_MU_MIMR_PCI;
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id = iop13xx_cpu_id();
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msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f);
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write_msi_msg(irq, &msg);
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set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
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return irq;
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}
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@ -559,6 +559,14 @@ void __init iop13xx_atue_setup(void)
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int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE);
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u32 reg_val;
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#ifdef CONFIG_PCI_MSI
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/* BAR 0 (inbound msi window) */
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__raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
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__raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0);
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__raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0);
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__raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0);
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#endif
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/* BAR 1 (1:1 mapping with Physical RAM) */
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/* Set limit and enable */
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__raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
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@ -720,6 +728,14 @@ void __init iop13xx_atux_setup(void)
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else
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atux_trhfa_timeout = jiffies;
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#ifdef CONFIG_PCI_MSI
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/* BAR 0 (inbound msi window) */
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__raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
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__raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0);
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__raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0);
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__raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0);
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#endif
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/* BAR 1 (1:1 mapping with Physical RAM) */
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/* Set limit and enable */
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__raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
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@ -181,6 +181,7 @@ static inline int iop13xx_cpu_id(void)
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#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
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#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
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#define IOP13XX_PBI_PMMR_OFFSET 0x00001580
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#define IOP13XX_MU_PMMR_OFFSET 0x00004000
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#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
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#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
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@ -412,6 +413,34 @@ static inline int iop13xx_cpu_id(void)
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#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
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/*=======================================================================*/
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/*============================MESSAGING UNIT=============================*/
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#define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\
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(ofs))
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#define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10)
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#define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14)
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#define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18)
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#define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C)
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#define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20)
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#define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24)
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#define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28)
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#define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C)
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#define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30)
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#define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34)
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#define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38)
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#define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C)
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#define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48)
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#define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50)
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#define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54)
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#define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84)
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#define IOP13XX_MU_WINDOW_SIZE (8 * 1024)
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#define IOP13XX_MU_BASE_PHYS (0xff000000)
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#define IOP13XX_MU_BASE_PCI (0xff000000)
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#define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48)
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#define IOP13XX_MU_MIMR_CORE_SELECT (15)
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/*=======================================================================*/
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/*==============================ADMA UNITS===============================*/
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#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
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#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
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@ -168,7 +168,7 @@ static inline u32 read_intpnd_3(void)
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#define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */
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#define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */
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#define IRQ_IOP13XX_RSVD_112 (112) /* 16 */
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#define IRQ_IOP13XX_RSVD_113 (113) /* 17 */
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#define IRQ_IOP13XX_INBD_MSI (113) /* 17 */
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#define IRQ_IOP13XX_RSVD_114 (114) /* 18 */
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#define IRQ_IOP13XX_RSVD_115 (115) /* 19 */
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#define IRQ_IOP13XX_RSVD_116 (116) /* 20 */
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@ -184,7 +184,13 @@ static inline u32 read_intpnd_3(void)
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#define IRQ_IOP13XX_RSVD_126 (126) /* 30 */
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#define IRQ_IOP13XX_HPI (127) /* 31 */
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#ifdef CONFIG_PCI_MSI
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#define IRQ_IOP13XX_MSI_0 (IRQ_IOP13XX_HPI + 1)
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#define NR_IOP13XX_IRQS (IRQ_IOP13XX_MSI_0 + 128)
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#else
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#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
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#endif
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#define NR_IRQS NR_IOP13XX_IRQS
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#endif /* _IOP13XX_IRQ_H_ */
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@ -0,0 +1,11 @@
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#ifndef _IOP13XX_MSI_H_
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#define _IOP13XX_MSI_H_
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#ifdef CONFIG_PCI_MSI
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void iop13xx_msi_init(void);
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#else
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static inline void iop13xx_msi_init(void)
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{
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return;
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}
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#endif
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#endif
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