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ARC: cache detection code bitrot 

* Number of (i|d)cache ways can be retrieved from BCRs and hence no need
  to cross check with with built-in constants
* Use of IS_ENABLED() to check for a Kconfig option
* is_not_cache_aligned() not used anymore

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Vineet Gupta 2013-06-15 10:21:51 +05:30
parent 6546415226
commit 3049918660
4 changed files with 13 additions and 37 deletions
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2
arch/arc/include/asm/arcregs.h
View File

@ -287,7 +287,7 @@ struct cpuinfo_arc_mmu {
};
struct cpuinfo_arc_cache {
unsigned int has_aliasing, sz, line_len, assoc, ver;
unsigned int sz, line_len, assoc, ver;
};
struct cpuinfo_arc_ccm {

11
arch/arc/include/asm/cache.h
View File

@ -18,22 +18,13 @@
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define ARC_ICACHE_WAYS 2
#define ARC_DCACHE_WAYS 4
/* Helpers */
/* For a rare case where customers have differently config I/D */
#define ARC_ICACHE_LINE_LEN L1_CACHE_BYTES
#define ARC_DCACHE_LINE_LEN L1_CACHE_BYTES
#define ICACHE_LINE_MASK (~(ARC_ICACHE_LINE_LEN - 1))
#define DCACHE_LINE_MASK (~(ARC_DCACHE_LINE_LEN - 1))
#if ARC_ICACHE_LINE_LEN != ARC_DCACHE_LINE_LEN
#error "Need to fix some code as I/D cache lines not same"
#else
#define is_not_cache_aligned(p) ((unsigned long)p & (~DCACHE_LINE_MASK))
#endif
/*
* ARC700 doesn't cache any access in top 256M.
* Ideal for wiring memory mapped peripherals as we don't need to do

6
arch/arc/include/asm/cacheflush.h
View File

@ -86,11 +86,7 @@ void flush_anon_page(struct vm_area_struct *vma,
*/
static inline int cache_is_vipt_aliasing(void)
{
#ifdef CONFIG_ARC_CACHE_VIPT_ALIASING
return 1;
#else
return 0;
#endif
return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
}
#define CACHE_COLOR(addr) (((unsigned long)(addr) >> (PAGE_SHIFT)) & 1)

31
arch/arc/mm/cache_arc700.c
View File

@ -144,8 +144,8 @@ void __cpuinit read_decode_cache_bcr(void)
p_ic = &cpuinfo_arc700[cpu].icache;
READ_BCR(ARC_REG_IC_BCR, ibcr);
if (ibcr.config == 0x3)
p_ic->assoc = 2;
BUG_ON(ibcr.config != 3);
p_ic->assoc = 2; /* Fixed to 2w set assoc */
p_ic->line_len = 8 << ibcr.line_len;
p_ic->sz = 0x200 << ibcr.sz;
p_ic->ver = ibcr.ver;
@ -153,8 +153,8 @@ void __cpuinit read_decode_cache_bcr(void)
p_dc = &cpuinfo_arc700[cpu].dcache;
READ_BCR(ARC_REG_DC_BCR, dbcr);
if (dbcr.config == 0x2)
p_dc->assoc = 4;
BUG_ON(dbcr.config != 2);
p_dc->assoc = 4; /* Fixed to 4w set assoc */
p_dc->line_len = 16 << dbcr.line_len;
p_dc->sz = 0x200 << dbcr.sz;
p_dc->ver = dbcr.ver;
@ -182,20 +182,11 @@ void __cpuinit arc_cache_init(void)
#ifdef CONFIG_ARC_HAS_ICACHE
/* 1. Confirm some of I-cache params which Linux assumes */
if ((ic->assoc != ARC_ICACHE_WAYS) ||
(ic->line_len != ARC_ICACHE_LINE_LEN)) {
if (ic->line_len != ARC_ICACHE_LINE_LEN)
panic("Cache H/W doesn't match kernel Config");
}
#if (CONFIG_ARC_MMU_VER > 2)
if (ic->ver != 3) {
if (running_on_hw)
panic("Cache ver doesn't match MMU ver\n");
/* For ISS - suggest the toggles to use */
pr_err("Use -prop=icache_version=3,-prop=dcache_version=3\n");
}
#endif
if (ic->ver != CONFIG_ARC_MMU_VER)
panic("Cache ver doesn't match MMU ver\n");
#endif
/* Enable/disable I-Cache */
@ -214,14 +205,12 @@ chk_dc:
return;
#ifdef CONFIG_ARC_HAS_DCACHE
if ((dc->assoc != ARC_DCACHE_WAYS) ||
(dc->line_len != ARC_DCACHE_LINE_LEN)) {
if (dc->line_len != ARC_DCACHE_LINE_LEN)
panic("Cache H/W doesn't match kernel Config");
}
dcache_does_alias = (dc->sz / ARC_DCACHE_WAYS) > PAGE_SIZE;
/* check for D-Cache aliasing */
dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE;
if (dcache_does_alias && !cache_is_vipt_aliasing())
panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
else if (!dcache_does_alias && cache_is_vipt_aliasing())