From 6691565fb8b7c426adf369b7130944a179af9e69 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Mon, 19 Jun 2017 09:37:29 +0200 Subject: [PATCH 1/7] arm64: dts: marvell: mcbin: enable the mdio node Since the mdio nodes are disabled by default now, we should explicitly enable these nodes at the board level when they are used. Enable the cpm_mdio node for the 8040-mcbin. Signed-off-by: Antoine Tenart Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts index fe56efcfcefe..4968e731de61 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts @@ -116,6 +116,8 @@ }; &cpm_mdio { + status = "okay"; + ge_phy: ethernet-phy@0 { reg = <0>; }; From a6d8bd919a1245ca759e8abc25a78811dec1d03f Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Tue, 20 Jun 2017 08:38:38 +0200 Subject: [PATCH 2/7] arm64: dts: marvell: use new bindings for xor clocks on ap806 New bindings are used for the system controller on the ap806, which means all clock properties must be converted. Use the new bindings in the xor nodes. Signed-off-by: Antoine Tenart Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index ff1964d314de..02e5aff48c81 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -159,7 +159,7 @@ reg = <0x400000 0x1000>, <0x410000 0x1000>; msi-parent = <&gic_v2m0>; - clocks = <&ap_syscon 3>; + clocks = <&ap_clk 3>; dma-coherent; }; @@ -168,7 +168,7 @@ reg = <0x420000 0x1000>, <0x430000 0x1000>; msi-parent = <&gic_v2m0>; - clocks = <&ap_syscon 3>; + clocks = <&ap_clk 3>; dma-coherent; }; @@ -177,7 +177,7 @@ reg = <0x440000 0x1000>, <0x450000 0x1000>; msi-parent = <&gic_v2m0>; - clocks = <&ap_syscon 3>; + clocks = <&ap_clk 3>; dma-coherent; }; @@ -186,7 +186,7 @@ reg = <0x460000 0x1000>, <0x470000 0x1000>; msi-parent = <&gic_v2m0>; - clocks = <&ap_syscon 3>; + clocks = <&ap_clk 3>; dma-coherent; }; From 8dcd4ab00424da31c47ca788b0ddf1b6d7b1d7ff Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 1 Jun 2017 16:55:41 +0200 Subject: [PATCH 3/7] arm64: dts: marvell: remove *-clock-output-names on cp110 The *-clock-output-names of the cp110-system-controller0 node are not used anymore, so remove them. Reviewed-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- .../arm64/boot/dts/marvell/armada-cp110-master.dtsi | 13 ------------- arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 13 ------------- 2 files changed, 26 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index d490a377d0c1..6724078b401f 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -111,19 +111,6 @@ "syscon"; reg = <0x440000 0x1000>; #clock-cells = <2>; - core-clock-output-names = - "cpm-apll", "cpm-ppv2-core", "cpm-eip", - "cpm-core", "cpm-nand-core"; - gate-clock-output-names = - "cpm-audio", "cpm-communit", "cpm-nand", - "cpm-ppv2", "cpm-sdio", "cpm-mg-domain", - "cpm-mg-core", "cpm-xor1", "cpm-xor0", - "cpm-gop-dp", "none", "cpm-pcie_x10", - "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", - "cpm-sata", "cpm-sata-usb", "cpm-main", - "cpm-sd-mmc-gop", "none", "none", - "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1", - "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; }; cpm_rtc: rtc@284000 { diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index dc4673dcf81b..47b20f465ea1 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -118,19 +118,6 @@ "syscon"; reg = <0x440000 0x1000>; #clock-cells = <2>; - core-clock-output-names = - "cps-apll", "cps-ppv2-core", "cps-eip", - "cps-core", "cps-nand-core"; - gate-clock-output-names = - "cps-audio", "cps-communit", "cps-nand", - "cps-ppv2", "cps-sdio", "cps-mg-domain", - "cps-mg-core", "cps-xor1", "cps-xor0", - "cps-gop-dp", "none", "cps-pcie_x10", - "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor", - "cps-sata", "cps-sata-usb", "cps-main", - "cps-sd-mmc-gop", "none", "none", - "cps-slow-io", "cps-usb3h0", "cps-usb3h1", - "cps-usb3dev", "cps-eip150", "cps-eip197"; }; cps_sata0: sata@540000 { From db7bc1ba9100c54236958ab60e1feecd7b203f12 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 1 Jun 2017 16:55:42 +0200 Subject: [PATCH 4/7] arm64: dts: marvell: use new binding for the system controller on cp110 The new binding for the system controller on cp110 moved the clock controller into a subnode. This preliminary step will allow to add gpio and pinctrl subnodes. Reviewed-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- .../boot/dts/marvell/armada-cp110-master.dtsi | 43 ++++++++++--------- .../boot/dts/marvell/armada-cp110-slave.dtsi | 41 ++++++++++-------- 2 files changed, 45 insertions(+), 39 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index 6724078b401f..8076681683fb 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -62,7 +62,7 @@ cpm_ethernet: ethernet@0 { compatible = "marvell,armada-7k-pp22"; reg = <0x0 0x100000>, <0x129000 0xb000>; - clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>; + clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>; clock-names = "pp_clk", "gop_clk", "mg_clk"; status = "disabled"; dma-coherent; @@ -94,7 +94,7 @@ #size-cells = <0>; compatible = "marvell,orion-mdio"; reg = <0x12a200 0x10>; - clocks = <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>; + clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>; status = "disabled"; }; @@ -107,10 +107,13 @@ }; cpm_syscon0: system-controller@440000 { - compatible = "marvell,cp110-system-controller0", - "syscon"; + compatible = "syscon", "simple-mfd"; reg = <0x440000 0x1000>; - #clock-cells = <2>; + + cpm_clk: clock { + compatible = "marvell,cp110-clock"; + #clock-cells = <2>; + }; }; cpm_rtc: rtc@284000 { @@ -125,7 +128,7 @@ "generic-ahci"; reg = <0x540000 0x30000>; interrupts = ; - clocks = <&cpm_syscon0 1 15>; + clocks = <&cpm_clk 1 15>; status = "disabled"; }; @@ -135,7 +138,7 @@ reg = <0x500000 0x4000>; dma-coherent; interrupts = ; - clocks = <&cpm_syscon0 1 22>; + clocks = <&cpm_clk 1 22>; status = "disabled"; }; @@ -145,7 +148,7 @@ reg = <0x510000 0x4000>; dma-coherent; interrupts = ; - clocks = <&cpm_syscon0 1 23>; + clocks = <&cpm_clk 1 23>; status = "disabled"; }; @@ -155,7 +158,7 @@ <0x6b0000 0x1000>; dma-coherent; msi-parent = <&gic_v2m0>; - clocks = <&cpm_syscon0 1 8>; + clocks = <&cpm_clk 1 8>; }; cpm_xor1: xor@6c0000 { @@ -164,7 +167,7 @@ <0x6d0000 0x1000>; dma-coherent; msi-parent = <&gic_v2m0>; - clocks = <&cpm_syscon0 1 7>; + clocks = <&cpm_clk 1 7>; }; cpm_spi0: spi@700600 { @@ -173,7 +176,7 @@ #address-cells = <0x1>; #size-cells = <0x0>; cell-index = <1>; - clocks = <&cpm_syscon0 1 21>; + clocks = <&cpm_clk 1 21>; status = "disabled"; }; @@ -183,7 +186,7 @@ #address-cells = <1>; #size-cells = <0>; cell-index = <2>; - clocks = <&cpm_syscon0 1 21>; + clocks = <&cpm_clk 1 21>; status = "disabled"; }; @@ -193,7 +196,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - clocks = <&cpm_syscon0 1 21>; + clocks = <&cpm_clk 1 21>; status = "disabled"; }; @@ -203,7 +206,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - clocks = <&cpm_syscon0 1 21>; + clocks = <&cpm_clk 1 21>; status = "disabled"; }; @@ -211,7 +214,7 @@ compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; reg = <0x760000 0x7d>; interrupts = ; - clocks = <&cpm_syscon0 1 25>; + clocks = <&cpm_clk 1 25>; status = "okay"; }; @@ -220,7 +223,7 @@ reg = <0x780000 0x300>; interrupts = ; clock-names = "core"; - clocks = <&cpm_syscon0 1 4>; + clocks = <&cpm_clk 1 4>; dma-coherent; status = "disabled"; }; @@ -237,7 +240,7 @@ ; interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; - clocks = <&cpm_syscon0 1 26>; + clocks = <&cpm_clk 1 26>; dma-mask = <0xff 0xffffffff>; }; }; @@ -264,7 +267,7 @@ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; interrupts = ; num-lanes = <1>; - clocks = <&cpm_syscon0 1 13>; + clocks = <&cpm_clk 1 13>; status = "disabled"; }; @@ -291,7 +294,7 @@ interrupts = ; num-lanes = <1>; - clocks = <&cpm_syscon0 1 11>; + clocks = <&cpm_clk 1 11>; status = "disabled"; }; @@ -318,7 +321,7 @@ interrupts = ; num-lanes = <1>; - clocks = <&cpm_syscon0 1 12>; + clocks = <&cpm_clk 1 12>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index 47b20f465ea1..a88300ae20fa 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -69,7 +69,7 @@ cps_ethernet: ethernet@0 { compatible = "marvell,armada-7k-pp22"; reg = <0x0 0x100000>, <0x129000 0xb000>; - clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>; + clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>; clock-names = "pp_clk", "gop_clk", "mg_clk"; status = "disabled"; dma-coherent; @@ -101,7 +101,7 @@ #size-cells = <0>; compatible = "marvell,orion-mdio"; reg = <0x12a200 0x10>; - clocks = <&cps_syscon0 1 9>, <&cps_syscon0 1 5>; + clocks = <&cps_clk 1 9>, <&cps_clk 1 5>; status = "disabled"; }; @@ -114,10 +114,13 @@ }; cps_syscon0: system-controller@440000 { - compatible = "marvell,cp110-system-controller0", - "syscon"; + compatible = "syscon", "simple-mfd"; reg = <0x440000 0x1000>; - #clock-cells = <2>; + + cps_clk: clock { + compatible = "marvell,cp110-clock"; + #clock-cells = <2>; + }; }; cps_sata0: sata@540000 { @@ -125,7 +128,7 @@ "generic-ahci"; reg = <0x540000 0x30000>; interrupts = ; - clocks = <&cps_syscon0 1 15>; + clocks = <&cps_clk 1 15>; status = "disabled"; }; @@ -135,7 +138,7 @@ reg = <0x500000 0x4000>; dma-coherent; interrupts = ; - clocks = <&cps_syscon0 1 22>; + clocks = <&cps_clk 1 22>; status = "disabled"; }; @@ -145,7 +148,7 @@ reg = <0x510000 0x4000>; dma-coherent; interrupts = ; - clocks = <&cps_syscon0 1 23>; + clocks = <&cps_clk 1 23>; status = "disabled"; }; @@ -155,7 +158,7 @@ <0x6b0000 0x1000>; dma-coherent; msi-parent = <&gic_v2m0>; - clocks = <&cps_syscon0 1 8>; + clocks = <&cps_clk 1 8>; }; cps_xor1: xor@6c0000 { @@ -164,7 +167,7 @@ <0x6d0000 0x1000>; dma-coherent; msi-parent = <&gic_v2m0>; - clocks = <&cps_syscon0 1 7>; + clocks = <&cps_clk 1 7>; }; cps_spi0: spi@700600 { @@ -173,7 +176,7 @@ #address-cells = <0x1>; #size-cells = <0x0>; cell-index = <3>; - clocks = <&cps_syscon0 1 21>; + clocks = <&cps_clk 1 21>; status = "disabled"; }; @@ -183,7 +186,7 @@ #address-cells = <1>; #size-cells = <0>; cell-index = <4>; - clocks = <&cps_syscon0 1 21>; + clocks = <&cps_clk 1 21>; status = "disabled"; }; @@ -193,7 +196,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - clocks = <&cps_syscon0 1 21>; + clocks = <&cps_clk 1 21>; status = "disabled"; }; @@ -203,7 +206,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = ; - clocks = <&cps_syscon0 1 21>; + clocks = <&cps_clk 1 21>; status = "disabled"; }; @@ -211,7 +214,7 @@ compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; reg = <0x760000 0x7d>; interrupts = ; - clocks = <&cps_syscon0 1 25>; + clocks = <&cps_clk 1 25>; status = "okay"; }; @@ -227,7 +230,7 @@ ; interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; - clocks = <&cps_syscon0 1 26>; + clocks = <&cps_clk 1 26>; dma-mask = <0xff 0xffffffff>; /* * The cryptographic engine found on the cp110 @@ -262,7 +265,7 @@ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; interrupts = ; num-lanes = <1>; - clocks = <&cps_syscon0 1 13>; + clocks = <&cps_clk 1 13>; status = "disabled"; }; @@ -289,7 +292,7 @@ interrupts = ; num-lanes = <1>; - clocks = <&cps_syscon0 1 11>; + clocks = <&cps_clk 1 11>; status = "disabled"; }; @@ -316,7 +319,7 @@ interrupts = ; num-lanes = <1>; - clocks = <&cps_syscon0 1 12>; + clocks = <&cps_clk 1 12>; status = "disabled"; }; }; From ae701b60028f4e0f6714276fd6790b5126975021 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 12 Jun 2017 17:34:58 +0200 Subject: [PATCH 5/7] arm64: dts: marvell: add pinctrl support for Armada 7K/8K Enable pinctrl support for CP and AP on the Armada 7K/8K SoCs. The CP master being different between Armada 7k and Armada 8k. This commit introduces the intermediates files armada-70x0.dtsi and armada-80x0.dtsi. These new files will provide different compatible strings depending of the SoC family. They will also be the location for the pinmux configuration at the SoC level. Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-7020.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-7040.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 53 ++++++++++++++++ arch/arm64/boot/dts/marvell/armada-8020.dtsi | 3 +- arch/arm64/boot/dts/marvell/armada-8040.dtsi | 3 +- arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 60 +++++++++++++++++++ arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 4 ++ 7 files changed, 121 insertions(+), 6 deletions(-) create mode 100644 arch/arm64/boot/dts/marvell/armada-70x0.dtsi create mode 100644 arch/arm64/boot/dts/marvell/armada-80x0.dtsi diff --git a/arch/arm64/boot/dts/marvell/armada-7020.dtsi b/arch/arm64/boot/dts/marvell/armada-7020.dtsi index 975e73302753..4ab012991d9d 100644 --- a/arch/arm64/boot/dts/marvell/armada-7020.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-7020.dtsi @@ -46,7 +46,7 @@ */ #include "armada-ap806-dual.dtsi" -#include "armada-cp110-master.dtsi" +#include "armada-70x0.dtsi" / { model = "Marvell Armada 7020"; diff --git a/arch/arm64/boot/dts/marvell/armada-7040.dtsi b/arch/arm64/boot/dts/marvell/armada-7040.dtsi index 78d995d62707..cbe460b8fc00 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-7040.dtsi @@ -46,7 +46,7 @@ */ #include "armada-ap806-quad.dtsi" -#include "armada-cp110-master.dtsi" +#include "armada-70x0.dtsi" / { model = "Marvell Armada 7040"; diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi new file mode 100644 index 000000000000..f6c22665d091 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2017 Marvell Technology Group Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Device Tree file for the Armada 70x0 SoC + */ + +#include "armada-cp110-master.dtsi" + +&cpm_syscon0 { + cpm_pinctrl: pinctrl { + compatible = "marvell,armada-7k-pinctrl"; + }; +}; diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi index 7c08f1f28d9e..0ba0bc942598 100644 --- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8020.dtsi @@ -46,8 +46,7 @@ */ #include "armada-ap806-dual.dtsi" -#include "armada-cp110-master.dtsi" -#include "armada-cp110-slave.dtsi" +#include "armada-80x0.dtsi" / { model = "Marvell Armada 8020"; diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi index 33813a75bc30..60fe84f5cbcc 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi @@ -46,8 +46,7 @@ */ #include "armada-ap806-quad.dtsi" -#include "armada-cp110-master.dtsi" -#include "armada-cp110-slave.dtsi" +#include "armada-80x0.dtsi" / { model = "Marvell Armada 8040"; diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi new file mode 100644 index 000000000000..93d1de03b39a --- /dev/null +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2017 Marvell Technology Group Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * Device Tree file for the Armada 80x0 SoC family + */ + +#include "armada-cp110-master.dtsi" +#include "armada-cp110-slave.dtsi" + +&cpm_syscon0 { + cpm_pinctrl: pinctrl { + compatible = "marvell,armada-8k-cpm-pinctrl"; + }; +}; + +&cps_syscon0 { + cps_pinctrl: pinctrl { + compatible = "marvell,armada-8k-cps-pinctrl"; + }; +}; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index 02e5aff48c81..b9b984e3fd55 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -252,6 +252,10 @@ compatible = "marvell,ap806-clock"; #clock-cells = <1>; }; + + ap_pinctrl: pinctrl { + compatible = "marvell,ap806-pinctrl"; + }; }; }; }; From 63dac0f4924b97a6b91b86259cdc4520b4d6254e Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 12 Jun 2017 17:35:00 +0200 Subject: [PATCH 6/7] arm64: dts: marvell: add gpio support for Armada 7K/8K Enable gpio support for CP and AP on the Marvell Armada 7K/8K SoCs. The Armada 8K has two CP110 blocks, each having two GPIO controllers. However, in each CP110 block, one of the GPIO controller cannot be used: in the master CP110, only the second GPIO controller can be used, while on the slave CP110, only the first GPIO controller can be used. On the other side, the Armada 7K has only one CP110, but both its GPIO controllers can be used. For this reason, the GPIO controllers are marked as "disabled" in the armada-cp110-master.dtsi and armada-cp110-slave.dtsi files, and only enabled in the per-SoC dtsi files. Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 15 +++++++++++++ arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 16 ++++++++++++++ arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 10 +++++++++ .../boot/dts/marvell/armada-cp110-master.dtsi | 21 ++++++++++++++++++ .../boot/dts/marvell/armada-cp110-slave.dtsi | 22 +++++++++++++++++++ 5 files changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi index f6c22665d091..860b6ae9dcc5 100644 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi @@ -46,6 +46,21 @@ #include "armada-cp110-master.dtsi" +/ { + aliases { + gpio1 = &cpm_gpio1; + gpio2 = &cpm_gpio2; + }; +}; + +&cpm_gpio1 { + status = "okay"; +}; + +&cpm_gpio2 { + status = "okay"; +}; + &cpm_syscon0 { cpm_pinctrl: pinctrl { compatible = "marvell,armada-7k-pinctrl"; diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi index 93d1de03b39a..666ebe96ba0d 100644 --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi @@ -47,6 +47,22 @@ #include "armada-cp110-master.dtsi" #include "armada-cp110-slave.dtsi" +/ { + aliases { + gpio1 = &cps_gpio1; + gpio2 = &cpm_gpio2; + }; +}; + +/* The 80x0 has two CP blocks, but uses only one block from each. */ +&cps_gpio1 { + status = "okay"; +}; + +&cpm_gpio2 { + status = "okay"; +}; + &cpm_syscon0 { cpm_pinctrl: pinctrl { compatible = "marvell,armada-8k-cpm-pinctrl"; diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index b9b984e3fd55..2557d69fefc8 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -57,6 +57,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; + gpio0 = &ap_gpio; }; psci { @@ -256,6 +257,15 @@ ap_pinctrl: pinctrl { compatible = "marvell,ap806-pinctrl"; }; + + ap_gpio: gpio { + compatible = "marvell,armada-8k-gpio"; + offset = <0x1040>; + ngpios = <19>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&ap_pinctrl 0 0 19>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index 8076681683fb..7835d4f517dc 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -114,6 +114,27 @@ compatible = "marvell,cp110-clock"; #clock-cells = <2>; }; + + cpm_gpio1: gpio@100 { + compatible = "marvell,armada-8k-gpio"; + offset = <0x100>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&cpm_pinctrl 0 0 32>; + status = "disabled"; + + }; + + cpm_gpio2: gpio@140 { + compatible = "marvell,armada-8k-gpio"; + offset = <0x140>; + ngpios = <31>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&cpm_pinctrl 0 32 31>; + status = "disabled"; + }; }; cpm_rtc: rtc@284000 { diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index a88300ae20fa..22e4feb1bace 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -121,6 +121,28 @@ compatible = "marvell,cp110-clock"; #clock-cells = <2>; }; + + cps_gpio1: gpio@100 { + compatible = "marvell,armada-8k-gpio"; + offset = <0x100>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&cps_pinctrl 0 0 32>; + status = "disabled"; + + }; + + cps_gpio2: gpio@140 { + compatible = "marvell,armada-8k-gpio"; + offset = <0x140>; + ngpios = <31>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&cps_pinctrl 0 32 31>; + status = "disabled"; + }; + }; cps_sata0: sata@540000 { From 6ef84a827c37547504514a80bdb35f74a67df5a3 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 21 Jun 2017 15:29:17 +0200 Subject: [PATCH 7/7] arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K This commit modifies the Marvell EBU Armada 7K and 8K Device Tree files to describe the ICU and GICP units, and use ICU interrupts for all devices in the CP110 blocks. Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 7 +++ .../boot/dts/marvell/armada-cp110-master.dtsi | 59 +++++++++++-------- .../boot/dts/marvell/armada-cp110-slave.dtsi | 55 +++++++++-------- 3 files changed, 73 insertions(+), 48 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi index 2557d69fefc8..1eb1f1e9aac4 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi @@ -147,6 +147,13 @@ marvell,spi-base = <128>, <136>, <144>, <152>; }; + gicp: gicp@3f0040 { + compatible = "marvell,ap806-gicp"; + reg = <0x3f0040 0x10>; + marvell,spi-ranges = <64 64>, <288 64>; + msi-controller; + }; + pic: interrupt-controller@3f0100 { compatible = "marvell,armada-8k-pic"; reg = <0x3f0100 0x10>; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi index 7835d4f517dc..aec5f94423dd 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi @@ -44,19 +44,20 @@ * Device Tree file for Marvell Armada CP110 Master. */ +#define ICU_GRP_NSR 0x0 + / { cp110-master { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; - interrupt-parent = <&gic>; + interrupt-parent = <&cpm_icu>; ranges; config-space@f2000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; - interrupt-parent = <&gic>; ranges = <0x0 0x0 0xf2000000 0x2000000>; cpm_ethernet: ethernet@0 { @@ -68,21 +69,21 @@ dma-coherent; cpm_eth0: eth0 { - interrupts = ; + interrupts = ; port-id = <0>; gop-port-id = <0>; status = "disabled"; }; cpm_eth1: eth1 { - interrupts = ; + interrupts = ; port-id = <1>; gop-port-id = <2>; status = "disabled"; }; cpm_eth2: eth2 { - interrupts = ; + interrupts = ; port-id = <2>; gop-port-id = <3>; status = "disabled"; @@ -106,6 +107,14 @@ status = "disabled"; }; + cpm_icu: interrupt-controller@1e0000 { + compatible = "marvell,cp110-icu"; + reg = <0x1e0000 0x10>; + #interrupt-cells = <3>; + interrupt-controller; + msi-parent = <&gicp>; + }; + cpm_syscon0: system-controller@440000 { compatible = "syscon", "simple-mfd"; reg = <0x440000 0x1000>; @@ -141,14 +150,14 @@ compatible = "marvell,armada-8k-rtc"; reg = <0x284000 0x20>, <0x284080 0x24>; reg-names = "rtc", "rtc-soc"; - interrupts = ; + interrupts = ; }; cpm_sata0: sata@540000 { compatible = "marvell,armada-8k-ahci", "generic-ahci"; reg = <0x540000 0x30000>; - interrupts = ; + interrupts = ; clocks = <&cpm_clk 1 15>; status = "disabled"; }; @@ -158,7 +167,7 @@ "generic-xhci"; reg = <0x500000 0x4000>; dma-coherent; - interrupts = ; + interrupts = ; clocks = <&cpm_clk 1 22>; status = "disabled"; }; @@ -168,7 +177,7 @@ "generic-xhci"; reg = <0x510000 0x4000>; dma-coherent; - interrupts = ; + interrupts = ; clocks = <&cpm_clk 1 23>; status = "disabled"; }; @@ -216,7 +225,7 @@ reg = <0x701000 0x20>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clocks = <&cpm_clk 1 21>; status = "disabled"; }; @@ -226,7 +235,7 @@ reg = <0x701100 0x20>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clocks = <&cpm_clk 1 21>; status = "disabled"; }; @@ -234,7 +243,7 @@ cpm_trng: trng@760000 { compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; reg = <0x760000 0x7d>; - interrupts = ; + interrupts = ; clocks = <&cpm_clk 1 25>; status = "okay"; }; @@ -242,7 +251,7 @@ cpm_sdhci0: sdhci@780000 { compatible = "marvell,armada-cp110-sdhci"; reg = <0x780000 0x300>; - interrupts = ; + interrupts = ; clock-names = "core"; clocks = <&cpm_clk 1 4>; dma-coherent; @@ -252,13 +261,13 @@ cpm_crypto: crypto@800000 { compatible = "inside-secure,safexcel-eip197"; reg = <0x800000 0x200000>; - interrupts = , - , - , - , - , - ; + , + , + , + , + ; interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; clocks = <&cpm_clk 1 26>; @@ -285,8 +294,8 @@ /* non-prefetchable memory */ 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - interrupts = ; + interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; num-lanes = <1>; clocks = <&cpm_clk 1 13>; status = "disabled"; @@ -311,8 +320,8 @@ /* non-prefetchable memory */ 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - interrupts = ; + interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; num-lanes = <1>; clocks = <&cpm_clk 1 11>; @@ -338,8 +347,8 @@ /* non-prefetchable memory */ 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - interrupts = ; + interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; num-lanes = <1>; clocks = <&cpm_clk 1 12>; diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi index 22e4feb1bace..9daf1e17bdfe 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi @@ -44,19 +44,20 @@ * Device Tree file for Marvell Armada CP110 Slave. */ +#define ICU_GRP_NSR 0x0 + / { cp110-slave { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; - interrupt-parent = <&gic>; + interrupt-parent = <&cps_icu>; ranges; config-space@f4000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; - interrupt-parent = <&gic>; ranges = <0x0 0x0 0xf4000000 0x2000000>; cps_rtc: rtc@284000 { @@ -75,21 +76,21 @@ dma-coherent; cps_eth0: eth0 { - interrupts = ; + interrupts = ; port-id = <0>; gop-port-id = <0>; status = "disabled"; }; cps_eth1: eth1 { - interrupts = ; + interrupts = ; port-id = <1>; gop-port-id = <2>; status = "disabled"; }; cps_eth2: eth2 { - interrupts = ; + interrupts = ; port-id = <2>; gop-port-id = <3>; status = "disabled"; @@ -113,6 +114,14 @@ status = "disabled"; }; + cps_icu: interrupt-controller@1e0000 { + compatible = "marvell,cp110-icu"; + reg = <0x1e0000 0x10>; + #interrupt-cells = <3>; + interrupt-controller; + msi-parent = <&gicp>; + }; + cps_syscon0: system-controller@440000 { compatible = "syscon", "simple-mfd"; reg = <0x440000 0x1000>; @@ -149,7 +158,7 @@ compatible = "marvell,armada-8k-ahci", "generic-ahci"; reg = <0x540000 0x30000>; - interrupts = ; + interrupts = ; clocks = <&cps_clk 1 15>; status = "disabled"; }; @@ -159,7 +168,7 @@ "generic-xhci"; reg = <0x500000 0x4000>; dma-coherent; - interrupts = ; + interrupts = ; clocks = <&cps_clk 1 22>; status = "disabled"; }; @@ -169,7 +178,7 @@ "generic-xhci"; reg = <0x510000 0x4000>; dma-coherent; - interrupts = ; + interrupts = ; clocks = <&cps_clk 1 23>; status = "disabled"; }; @@ -217,7 +226,7 @@ reg = <0x701000 0x20>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clocks = <&cps_clk 1 21>; status = "disabled"; }; @@ -227,7 +236,7 @@ reg = <0x701100 0x20>; #address-cells = <1>; #size-cells = <0>; - interrupts = ; + interrupts = ; clocks = <&cps_clk 1 21>; status = "disabled"; }; @@ -235,7 +244,7 @@ cps_trng: trng@760000 { compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76"; reg = <0x760000 0x7d>; - interrupts = ; + interrupts = ; clocks = <&cps_clk 1 25>; status = "okay"; }; @@ -243,13 +252,13 @@ cps_crypto: crypto@800000 { compatible = "inside-secure,safexcel-eip197"; reg = <0x800000 0x200000>; - interrupts = , - , - , - , - , - ; + , + , + , + , + ; interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3", "eip"; clocks = <&cps_clk 1 26>; @@ -284,8 +293,8 @@ /* non-prefetchable memory */ 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; - interrupts = ; + interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; num-lanes = <1>; clocks = <&cps_clk 1 13>; status = "disabled"; @@ -310,8 +319,8 @@ /* non-prefetchable memory */ 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; - interrupts = ; + interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; num-lanes = <1>; clocks = <&cps_clk 1 11>; @@ -337,8 +346,8 @@ /* non-prefetchable memory */ 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>; interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; - interrupts = ; + interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>; + interrupts = ; num-lanes = <1>; clocks = <&cps_clk 1 12>;