sm501: add support for the SM502 programmable PLL
SM502 has a programmable PLL which can provide the panel pixel clock instead of the 288MHz and 336MHz PLLs. [akpm@linux-foundation.org: coding-style fixes] Signed-off-by: Ville Syrjala <syrjala@sci.fi> Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -48,6 +48,7 @@ struct sm501_devdata {
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unsigned int pdev_id;
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unsigned int pdev_id;
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unsigned int irq;
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unsigned int irq;
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void __iomem *regs;
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void __iomem *regs;
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unsigned int rev;
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};
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};
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#define MHZ (1000 * 1000)
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#define MHZ (1000 * 1000)
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@ -417,46 +418,108 @@ struct sm501_clock {
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unsigned long mclk;
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unsigned long mclk;
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int divider;
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int divider;
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int shift;
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int shift;
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unsigned int m, n, k;
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};
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};
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/* sm501_calc_clock
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*
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* Calculates the nearest discrete clock frequency that
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* can be achieved with the specified input clock.
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* the maximum divisor is 3 or 5
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*/
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static int sm501_calc_clock(unsigned long freq,
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struct sm501_clock *clock,
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int max_div,
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unsigned long mclk,
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long *best_diff)
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{
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int ret = 0;
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int divider;
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int shift;
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long diff;
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/* try dividers 1 and 3 for CRT and for panel,
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try divider 5 for panel only.*/
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for (divider = 1; divider <= max_div; divider += 2) {
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/* try all 8 shift values.*/
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for (shift = 0; shift < 8; shift++) {
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/* Calculate difference to requested clock */
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diff = sm501fb_round_div(mclk, divider << shift) - freq;
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if (diff < 0)
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diff = -diff;
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/* If it is less than the current, use it */
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if (diff < *best_diff) {
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*best_diff = diff;
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clock->mclk = mclk;
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clock->divider = divider;
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clock->shift = shift;
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ret = 1;
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}
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}
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}
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return ret;
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}
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/* sm501_calc_pll
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*
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* Calculates the nearest discrete clock frequency that can be
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* achieved using the programmable PLL.
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* the maximum divisor is 3 or 5
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*/
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static unsigned long sm501_calc_pll(unsigned long freq,
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struct sm501_clock *clock,
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int max_div)
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{
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unsigned long mclk;
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unsigned int m, n, k;
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long best_diff = 999999999;
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/*
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* The SM502 datasheet doesn't specify the min/max values for M and N.
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* N = 1 at least doesn't work in practice.
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*/
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for (m = 2; m <= 255; m++) {
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for (n = 2; n <= 127; n++) {
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for (k = 0; k <= 1; k++) {
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mclk = (24000000UL * m / n) >> k;
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if (sm501_calc_clock(freq, clock, max_div,
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mclk, &best_diff)) {
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clock->m = m;
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clock->n = n;
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clock->k = k;
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}
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}
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}
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}
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/* Return best clock. */
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return clock->mclk / (clock->divider << clock->shift);
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}
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/* sm501_select_clock
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/* sm501_select_clock
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*
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*
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* selects nearest discrete clock frequency the SM501 can achive
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* Calculates the nearest discrete clock frequency that can be
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* achieved using the 288MHz and 336MHz PLLs.
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* the maximum divisor is 3 or 5
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* the maximum divisor is 3 or 5
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*/
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*/
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static unsigned long sm501_select_clock(unsigned long freq,
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static unsigned long sm501_select_clock(unsigned long freq,
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struct sm501_clock *clock,
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struct sm501_clock *clock,
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int max_div)
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int max_div)
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{
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{
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unsigned long mclk;
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unsigned long mclk;
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int divider;
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int shift;
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long diff;
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long best_diff = 999999999;
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long best_diff = 999999999;
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/* Try 288MHz and 336MHz clocks. */
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/* Try 288MHz and 336MHz clocks. */
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for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
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for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
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/* try dividers 1 and 3 for CRT and for panel,
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sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
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try divider 5 for panel only.*/
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for (divider = 1; divider <= max_div; divider += 2) {
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/* try all 8 shift values.*/
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for (shift = 0; shift < 8; shift++) {
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/* Calculate difference to requested clock */
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diff = sm501fb_round_div(mclk, divider << shift) - freq;
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if (diff < 0)
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diff = -diff;
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/* If it is less than the current, use it */
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if (diff < best_diff) {
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best_diff = diff;
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clock->mclk = mclk;
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clock->divider = divider;
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clock->shift = shift;
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}
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}
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}
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}
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}
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/* Return best clock. */
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/* Return best clock. */
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@ -478,6 +541,7 @@ unsigned long sm501_set_clock(struct device *dev,
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unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE);
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unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE);
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unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK);
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unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK);
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unsigned char reg;
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unsigned char reg;
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unsigned int pll_reg = 0;
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unsigned long sm501_freq; /* the actual frequency acheived */
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unsigned long sm501_freq; /* the actual frequency acheived */
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struct sm501_clock to;
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struct sm501_clock to;
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@ -492,14 +556,28 @@ unsigned long sm501_set_clock(struct device *dev,
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* requested frequency the value must be multiplied by
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* requested frequency the value must be multiplied by
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* 2. This clock also has an additional pre divisor */
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* 2. This clock also has an additional pre divisor */
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sm501_freq = (sm501_select_clock(2 * req_freq, &to, 5) / 2);
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if (sm->rev >= 0xC0) {
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reg=to.shift & 0x07;/* bottom 3 bits are shift */
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/* SM502 -> use the programmable PLL */
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if (to.divider == 3)
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sm501_freq = (sm501_calc_pll(2 * req_freq,
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reg |= 0x08; /* /3 divider required */
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&to, 5) / 2);
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else if (to.divider == 5)
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reg = to.shift & 0x07;/* bottom 3 bits are shift */
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reg |= 0x10; /* /5 divider required */
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if (to.divider == 3)
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if (to.mclk != 288000000)
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reg |= 0x08; /* /3 divider required */
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reg |= 0x20; /* which mclk pll is source */
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else if (to.divider == 5)
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reg |= 0x10; /* /5 divider required */
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reg |= 0x40; /* select the programmable PLL */
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pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
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} else {
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sm501_freq = (sm501_select_clock(2 * req_freq,
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&to, 5) / 2);
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reg = to.shift & 0x07;/* bottom 3 bits are shift */
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if (to.divider == 3)
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reg |= 0x08; /* /3 divider required */
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else if (to.divider == 5)
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reg |= 0x10; /* /5 divider required */
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if (to.mclk != 288000000)
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reg |= 0x20; /* which mclk pll is source */
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}
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break;
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break;
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case SM501_CLOCK_V2XCLK:
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case SM501_CLOCK_V2XCLK:
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@ -560,6 +638,10 @@ unsigned long sm501_set_clock(struct device *dev,
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}
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}
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writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
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writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
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if (pll_reg)
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writel(pll_reg, sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
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sm501_sync_regs(sm);
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sm501_sync_regs(sm);
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dev_info(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
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dev_info(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
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@ -580,15 +662,24 @@ EXPORT_SYMBOL_GPL(sm501_set_clock);
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* finds the closest available frequency for a given clock
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* finds the closest available frequency for a given clock
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*/
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*/
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unsigned long sm501_find_clock(int clksrc,
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unsigned long sm501_find_clock(struct device *dev,
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int clksrc,
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unsigned long req_freq)
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unsigned long req_freq)
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{
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{
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struct sm501_devdata *sm = dev_get_drvdata(dev);
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unsigned long sm501_freq; /* the frequency achiveable by the 501 */
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unsigned long sm501_freq; /* the frequency achiveable by the 501 */
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struct sm501_clock to;
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struct sm501_clock to;
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switch (clksrc) {
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switch (clksrc) {
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case SM501_CLOCK_P2XCLK:
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case SM501_CLOCK_P2XCLK:
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sm501_freq = (sm501_select_clock(2 * req_freq, &to, 5) / 2);
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if (sm->rev >= 0xC0) {
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/* SM502 -> use the programmable PLL */
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sm501_freq = (sm501_calc_pll(2 * req_freq,
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&to, 5) / 2);
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} else {
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sm501_freq = (sm501_select_clock(2 * req_freq,
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&to, 5) / 2);
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}
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break;
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break;
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case SM501_CLOCK_V2XCLK:
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case SM501_CLOCK_V2XCLK:
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@ -895,6 +986,8 @@ static int sm501_init_dev(struct sm501_devdata *sm)
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dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
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dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
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sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
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sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
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sm->rev = devid & SM501_DEVICEID_REVMASK;
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sm501_dump_gate(sm);
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sm501_dump_gate(sm);
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ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
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ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
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@ -129,11 +129,14 @@
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#define SM501_DEVICEID_SM501 (0x05010000)
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#define SM501_DEVICEID_SM501 (0x05010000)
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#define SM501_DEVICEID_IDMASK (0xffff0000)
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#define SM501_DEVICEID_IDMASK (0xffff0000)
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#define SM501_DEVICEID_REVMASK (0x000000ff)
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#define SM501_PLLCLOCK_COUNT (0x000064)
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#define SM501_PLLCLOCK_COUNT (0x000064)
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#define SM501_MISC_TIMING (0x000068)
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#define SM501_MISC_TIMING (0x000068)
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#define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
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#define SM501_CURRENT_SDRAM_CLOCK (0x00006C)
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#define SM501_PROGRAMMABLE_PLL_CONTROL (0x000074)
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/* GPIO base */
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/* GPIO base */
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#define SM501_GPIO (0x010000)
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#define SM501_GPIO (0x010000)
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#define SM501_GPIO_DATA_LOW (0x00)
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#define SM501_GPIO_DATA_LOW (0x00)
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@ -24,7 +24,8 @@ extern int sm501_unit_power(struct device *dev,
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extern unsigned long sm501_set_clock(struct device *dev,
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extern unsigned long sm501_set_clock(struct device *dev,
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int clksrc, unsigned long freq);
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int clksrc, unsigned long freq);
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extern unsigned long sm501_find_clock(int clksrc, unsigned long req_freq);
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extern unsigned long sm501_find_clock(struct device *dev,
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int clksrc, unsigned long req_freq);
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/* sm501_misc_control
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/* sm501_misc_control
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*
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*
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