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Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

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Pull x86 cpu updates from Ingo Molnar:
 "Two changes: a Hygon CPU fix, and an optimization Centaur CPUs"

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/power: Optimize C3 entry on Centaur CPUs
  x86/CPU/hygon: Fix phys_proc_id calculation logic for multi-die processors
This commit is contained in:
Linus Torvalds 2019-05-06 15:53:51 -07:00
commit 31a4319b68
2 changed files with 17 additions and 0 deletions
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12
arch/x86/kernel/acpi/cstate.c
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@ -51,6 +51,18 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
if (c->x86_vendor == X86_VENDOR_INTEL && if (c->x86_vendor == X86_VENDOR_INTEL &&
(c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f))) (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
flags->bm_control = 0; flags->bm_control = 0;
/*
* For all recent Centaur CPUs, the ucode will make sure that each
* core can keep cache coherence with each other while entering C3
* type state. So, set bm_check to 1 to indicate that the kernel
* doesn't need to execute a cache flush operation (WBINVD) when
* entering C3 type state.
*/
if (c->x86_vendor == X86_VENDOR_CENTAUR) {
if (c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0x0f &&
c->x86_stepping >= 0x0e))
flags->bm_check = 1;
}
} }
EXPORT_SYMBOL(acpi_processor_power_init_bm_check); EXPORT_SYMBOL(acpi_processor_power_init_bm_check);

5
arch/x86/kernel/cpu/hygon.c
View File

@ -19,6 +19,8 @@
#include "cpu.h" #include "cpu.h"
#define APICID_SOCKET_ID_BIT 6
/* /*
* nodes_per_socket: Stores the number of nodes per socket. * nodes_per_socket: Stores the number of nodes per socket.
* Refer to CPUID Fn8000_001E_ECX Node Identifiers[10:8] * Refer to CPUID Fn8000_001E_ECX Node Identifiers[10:8]
@ -87,6 +89,9 @@ static void hygon_get_topology(struct cpuinfo_x86 *c)
if (!err) if (!err)
c->x86_coreid_bits = get_count_order(c->x86_max_cores); c->x86_coreid_bits = get_count_order(c->x86_max_cores);
/* Socket ID is ApicId[6] for these processors. */
c->phys_proc_id = c->apicid >> APICID_SOCKET_ID_BIT;
cacheinfo_hygon_init_llc_id(c, cpu, node_id); cacheinfo_hygon_init_llc_id(c, cpu, node_id);
} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
u64 value; u64 value;