MIPS: dsp: Add assembler support for DSP ASEs.
Newer toolchains support the DSP and DSP Rev2 instructions. This patch performs a check for that support and adds compiler and assembler flags for only the files that need use those instructions. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4752/ Signed-off-by: John Crispin <blogic@openwrt.org>
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@ -1155,6 +1155,48 @@ do { \
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: "=r" (__res)); \
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__res;})
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#ifdef HAVE_AS_DSP
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#define rddsp(mask) \
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({ \
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unsigned int __dspctl; \
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\
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__asm__ __volatile__( \
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" rddsp %0, %x1 \n" \
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: "=r" (__dspctl) \
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: "i" (mask)); \
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__dspctl; \
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})
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#define wrdsp(val, mask) \
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do { \
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__asm__ __volatile__( \
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" wrdsp %0, %x1 \n" \
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: \
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: "r" (val), "i" (mask)); \
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} while (0)
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#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
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#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
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#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
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#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
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#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
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#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
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#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
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#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
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#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
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#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
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#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
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#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
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#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
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#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
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#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
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#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
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#else
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#define rddsp(mask) \
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({ \
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unsigned int __res; \
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@ -1184,29 +1226,6 @@ do { \
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: "r" (val), "i" (mask)); \
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} while (0)
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#if 0 /* Need DSP ASE capable assembler ... */
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#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
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#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
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#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
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#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
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#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
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#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
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#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
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#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
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#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
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#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
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#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
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#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
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#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
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#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
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#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
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#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
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#else
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#define mfhi0() \
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({ \
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unsigned long __treg; \
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@ -98,4 +98,35 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o
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obj-$(CONFIG_JUMP_LABEL) += jump_label.o
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#
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# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is safe
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# to enable DSP assembler support here even if the MIPS Release 2 CPU we
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# are targetting does not support DSP because all code-paths making use of
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# it properly check that the running CPU *actually does* support these
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# instructions.
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#
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ifeq ($(CONFIG_CPU_MIPSR2), y)
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CFLAGS_DSP = -DHAVE_AS_DSP
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#
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# Check if assembler supports DSP ASE
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#
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ifeq ($(call cc-option-yn,-mdsp), y)
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CFLAGS_DSP += -mdsp
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endif
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#
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# Check if assembler supports DSP ASE Rev2
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#
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ifeq ($(call cc-option-yn,-mdspr2), y)
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CFLAGS_DSP += -mdspr2
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endif
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CFLAGS_signal.o = $(CFLAGS_DSP)
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CFLAGS_signal32.o = $(CFLAGS_DSP)
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CFLAGS_process.o = $(CFLAGS_DSP)
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CFLAGS_branch.o = $(CFLAGS_DSP)
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CFLAGS_ptrace.o = $(CFLAGS_DSP)
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endif
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CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)
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