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[ARM] 4913/1: [AT91] PMC_MDIV definitions 

The allowed values for the MDIV field (Master Clock Division) in the
PMC controller differ between the AT91RM9200 and AT91SAM9/CAP9.
To remove possible confusion, change the definitions to be more explicit.

Also define the Processor Clock Division bits.

Signed-off-by: Andrew Victor <linux@maxim.org.za>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Andrew Victor 2008-04-02 22:31:31 +01:00 committed by Russell King
parent c21098ea56
commit 32b1216d1e
1 changed files with 11 additions and 4 deletions
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15
include/asm-arm/arch-at91/at91_pmc.h
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@ -76,10 +76,17 @@
#define AT91_PMC_PRES_32 (5 << 2)
#define AT91_PMC_PRES_64 (6 << 2)
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
#define AT91_PMC_MDIV_1 (0 << 8)
#define AT91_PMC_MDIV_2 (1 << 8)
#define AT91_PMC_MDIV_3 (2 << 8)
#define AT91_PMC_MDIV_4 (3 << 8)
#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
#define AT91RM9200_PMC_MDIV_3 (2 << 8)
#define AT91RM9200_PMC_MDIV_4 (3 << 8)
#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
#define AT91SAM9_PMC_MDIV_6 (3 << 8)
#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
#define AT91_PMC_PDIV_1 (0 << 12)
#define AT91_PMC_PDIV_2 (1 << 12)
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */