ARM: dts: ipq8074: Add pcie nodes
The driver/phy support for ipq8074 is available now. So enabling the nodes in DT. Reviewed-by: Abhishek Sahu <absahu@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sricharan R <sricharan@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Sricharan R
Andy Gross
parent
22592a2277
commit
33057e1672
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@ -24,7 +24,7 @@
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ranges = <0 0 0 0xffffffff>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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compatible = "simple-bus";
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pinctrl@1000000 {
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq8074-pinctrl";
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compatible = "qcom,ipq8074-pinctrl";
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reg = <0x1000000 0x300000>;
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reg = <0x1000000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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@ -278,6 +278,161 @@
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pinctrl-names = "default";
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pinctrl-names = "default";
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status = "disabled";
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status = "disabled";
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};
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};
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pcie_phy0: phy@86000 {
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compatible = "qcom,ipq8074-qmp-pcie-phy";
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reg = <0x86000 0x1000>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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clock-names = "pipe_clk";
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clock-output-names = "pcie20_phy0_pipe_clk";
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resets = <&gcc GCC_PCIE0_PHY_BCR>,
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<&gcc GCC_PCIE0PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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status = "disabled";
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};
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pcie0: pci@20000000 {
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compatible = "qcom,pcie-ipq8074";
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reg = <0x20000000 0xf1d
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0x20000f20 0xa8
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0x80000 0x2000
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0x20100000 0x1000>;
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reg-names = "dbi", "elbi", "parf", "config";
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device_type = "pci";
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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phys = <&pcie_phy0>;
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phy-names = "pciephy";
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ranges = <0x81000000 0 0x20200000 0x20200000
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0 0x100000 /* downstream I/O */
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0x82000000 0 0x20300000 0x20300000
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0 0xd00000>; /* non-prefetchable memory */
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 75
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IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc 0 78
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IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc 0 79
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IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc 0 83
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IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
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<&gcc GCC_PCIE0_AXI_M_CLK>,
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<&gcc GCC_PCIE0_AXI_S_CLK>,
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<&gcc GCC_PCIE0_AHB_CLK>,
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<&gcc GCC_PCIE0_AUX_CLK>;
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clock-names = "iface",
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"axi_m",
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"axi_s",
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"ahb",
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"aux";
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resets = <&gcc GCC_PCIE0_PIPE_ARES>,
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<&gcc GCC_PCIE0_SLEEP_ARES>,
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<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
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<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
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<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
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<&gcc GCC_PCIE0_AHB_ARES>,
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<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
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reset-names = "pipe",
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"sleep",
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"sticky",
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"axi_m",
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"axi_s",
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"ahb",
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"axi_m_sticky";
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status = "disabled";
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};
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pcie_phy1: phy@8e000 {
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compatible = "qcom,ipq8074-qmp-pcie-phy";
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reg = <0x8e000 0x1000>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
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clock-names = "pipe_clk";
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clock-output-names = "pcie20_phy1_pipe_clk";
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resets = <&gcc GCC_PCIE1_PHY_BCR>,
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<&gcc GCC_PCIE1PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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status = "disabled";
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};
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pcie1: pci@10000000 {
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compatible = "qcom,pcie-ipq8074";
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reg = <0x10000000 0xf1d
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0x10000f20 0xa8
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0x88000 0x2000
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0x10100000 0x1000>;
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reg-names = "dbi", "elbi", "parf", "config";
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device_type = "pci";
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linux,pci-domain = <1>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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phys = <&pcie_phy1>;
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phy-names = "pciephy";
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ranges = <0x81000000 0 0x10200000 0x10200000
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0 0x100000 /* downstream I/O */
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0x82000000 0 0x10300000 0x10300000
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0 0xd00000>; /* non-prefetchable memory */
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 142
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IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc 0 143
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IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc 0 144
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IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc 0 145
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IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
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<&gcc GCC_PCIE1_AXI_M_CLK>,
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<&gcc GCC_PCIE1_AXI_S_CLK>,
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<&gcc GCC_PCIE1_AHB_CLK>,
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<&gcc GCC_PCIE1_AUX_CLK>;
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clock-names = "iface",
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"axi_m",
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"axi_s",
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"ahb",
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"aux";
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resets = <&gcc GCC_PCIE1_PIPE_ARES>,
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<&gcc GCC_PCIE1_SLEEP_ARES>,
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<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
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<&gcc GCC_PCIE1_AXI_MASTER_ARES>,
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<&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
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<&gcc GCC_PCIE1_AHB_ARES>,
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<&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
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reset-names = "pipe",
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"sleep",
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"sticky",
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"axi_m",
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"axi_s",
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"ahb",
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"axi_m_sticky";
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status = "disabled";
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};
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};
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};
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cpus {
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cpus {
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