e1000e: only perform ESB2 MDIC workaround on certain configurations
A workaround added for all ESB2 devices (adds a delay for all MDIC accesses which resolves an issue with the MDIC ready bit being set prematurely) is applicable only to devices in which the MAC-PHY interconnect is not operating in a certain mode with in-band MDIO. Check the control register for the operating mode and enable the workaround accordingly. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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0781895067
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@ -46,6 +46,9 @@
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#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
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#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
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#define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
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#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
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#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
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#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
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@ -462,28 +465,36 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
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return ret_val;
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}
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/*
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* The "ready" bit in the MDIC register may be incorrectly set
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* before the device has completed the "Page Select" MDI
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* transaction. So we wait 200us after each MDI command...
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*/
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udelay(200);
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if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
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/*
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* The "ready" bit in the MDIC register may be incorrectly set
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* before the device has completed the "Page Select" MDI
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* transaction. So we wait 200us after each MDI command...
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*/
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udelay(200);
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/* ...and verify the command was successful. */
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ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
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/* ...and verify the command was successful. */
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ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
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if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
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ret_val = -E1000_ERR_PHY;
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e1000_release_phy_80003es2lan(hw);
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return ret_val;
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if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
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ret_val = -E1000_ERR_PHY;
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e1000_release_phy_80003es2lan(hw);
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return ret_val;
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}
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udelay(200);
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ret_val = e1000e_read_phy_reg_mdic(hw,
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MAX_PHY_REG_ADDRESS & offset,
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data);
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udelay(200);
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} else {
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ret_val = e1000e_read_phy_reg_mdic(hw,
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MAX_PHY_REG_ADDRESS & offset,
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data);
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}
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udelay(200);
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ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
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data);
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udelay(200);
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e1000_release_phy_80003es2lan(hw);
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return ret_val;
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@ -526,28 +537,35 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
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return ret_val;
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}
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if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
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/*
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* The "ready" bit in the MDIC register may be incorrectly set
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* before the device has completed the "Page Select" MDI
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* transaction. So we wait 200us after each MDI command...
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*/
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udelay(200);
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/*
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* The "ready" bit in the MDIC register may be incorrectly set
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* before the device has completed the "Page Select" MDI
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* transaction. So we wait 200us after each MDI command...
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*/
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udelay(200);
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/* ...and verify the command was successful. */
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ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
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/* ...and verify the command was successful. */
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ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
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if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
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e1000_release_phy_80003es2lan(hw);
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return -E1000_ERR_PHY;
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}
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if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
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e1000_release_phy_80003es2lan(hw);
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return -E1000_ERR_PHY;
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udelay(200);
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ret_val = e1000e_write_phy_reg_mdic(hw,
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MAX_PHY_REG_ADDRESS & offset,
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data);
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udelay(200);
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} else {
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ret_val = e1000e_write_phy_reg_mdic(hw,
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MAX_PHY_REG_ADDRESS & offset,
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data);
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}
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udelay(200);
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ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
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data);
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udelay(200);
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e1000_release_phy_80003es2lan(hw);
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return ret_val;
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@ -866,6 +884,19 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
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reg_data &= ~0x00100000;
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E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
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/* default to true to enable the MDIC W/A */
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hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
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ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_OFFSET >>
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E1000_KMRNCTRLSTA_OFFSET_SHIFT,
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&i);
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if (!ret_val) {
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if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
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E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
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hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
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}
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/*
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* Clear all of the statistics registers (clear on read). It is
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* important that we do this after we have tried to establish link
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@ -900,6 +900,10 @@ struct e1000_dev_spec_82571 {
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u32 smb_counter;
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};
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struct e1000_dev_spec_80003es2lan {
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bool mdic_wa_enable;
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};
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struct e1000_shadow_ram {
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u16 value;
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bool modified;
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@ -928,6 +932,7 @@ struct e1000_hw {
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union {
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struct e1000_dev_spec_82571 e82571;
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struct e1000_dev_spec_80003es2lan e80003es2lan;
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struct e1000_dev_spec_ich8lan ich8lan;
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} dev_spec;
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};
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