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m68knommu: make ColdFire Park and Assignment register definitions absolute addresses 

Make all definitions of the ColdFire MPARK and IRQ Assignment registers
absolute addresses. Currently some are relative to the MBAR peripheral
region.

The various ColdFire parts use different methods to address the internal
registers, some are absolute, some are relative to peripheral regions
which can be mapped at different address ranges (such as the MBAR and IPSBAR
registers). We don't want to deal with this in the code when we are
accessing these registers, so make all register definitions the absolute
address - factoring out whether it is an offset into a peripheral region.

This makes them all consistently defined, and reduces the occasional bugs
caused by inconsistent definition of the register addresses.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer 2012-09-14 16:09:59 +10:00
parent 1419ea3b34
commit 35142b915b
4 changed files with 9 additions and 9 deletions
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4
arch/m68k/include/asm/m5249sim.h
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@ -30,8 +30,8 @@
#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */

2
arch/m68k/include/asm/m525xsim.h
View File

@ -30,7 +30,7 @@
#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog srv */
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */

6
arch/m68k/include/asm/m5307sim.h
View File

@ -28,9 +28,9 @@
#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */
#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */
#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */

6
arch/m68k/include/asm/m5407sim.h
View File

@ -28,9 +28,9 @@
#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */
#define MCFSIM_PLLCR 0x08 /* PLL Control Reg*/
#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/
#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Intr Assignment */
#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl */
#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pending */
#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */