drm/radeon: check if pcie gen 2 is already enabled (v2)
If so, skip enabling it to save time. v2: coding style fixes Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3431,9 +3431,14 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
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if (!(mask & DRM_PCIE_SPEED_50))
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if (!(mask & DRM_PCIE_SPEED_50))
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return;
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return;
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speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
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if (speed_cntl & LC_CURRENT_DATA_RATE) {
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DRM_INFO("PCIE gen 2 link speeds already enabled\n");
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return;
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}
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DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
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DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
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speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
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if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
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if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
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(speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
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(speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
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@ -3703,6 +3703,12 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
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if (!(mask & DRM_PCIE_SPEED_50))
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if (!(mask & DRM_PCIE_SPEED_50))
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return;
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return;
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speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
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if (speed_cntl & LC_CURRENT_DATA_RATE) {
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DRM_INFO("PCIE gen 2 link speeds already enabled\n");
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return;
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}
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DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
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DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
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/* 55 nm r6xx asics */
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/* 55 nm r6xx asics */
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