[PATCH] sata_sil24: implement loss of completion interrupt on PCI-X errta fix
SiI3124 might lose completion interrupt if completion interrupt occurs shortly after SLOT_STAT register is read for the previous completion interrupt if it is operating in PCI-X mode. This currently doesn't trigger as libata never queues more than one command, but it will with NCQ changes. This patch implements the workaround - turning on WoC and explicitly clearing interrupt. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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@ -221,6 +221,7 @@ enum {
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/* host flags */
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/* host flags */
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SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
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ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
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SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
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IRQ_STAT_4PORTS = 0xf,
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IRQ_STAT_4PORTS = 0xf,
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};
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};
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@ -348,7 +349,8 @@ static struct ata_port_info sil24_port_info[] = {
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/* sil_3124 */
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/* sil_3124 */
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{
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{
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.sht = &sil24_sht,
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.sht = &sil24_sht,
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.host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4),
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.host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
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SIL24_FLAG_PCIX_IRQ_WOC,
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.pio_mask = 0x1f, /* pio0-4 */
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x3f, /* udma0-5 */
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.udma_mask = 0x3f, /* udma0-5 */
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@ -737,6 +739,10 @@ static inline void sil24_host_intr(struct ata_port *ap)
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slot_stat = readl(port + PORT_SLOT_STAT);
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slot_stat = readl(port + PORT_SLOT_STAT);
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if (!(slot_stat & HOST_SSTAT_ATTN)) {
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if (!(slot_stat & HOST_SSTAT_ATTN)) {
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struct sil24_port_priv *pp = ap->private_data;
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struct sil24_port_priv *pp = ap->private_data;
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if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
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writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
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/*
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/*
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* !HOST_SSAT_ATTN guarantees successful completion,
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* !HOST_SSAT_ATTN guarantees successful completion,
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* so reading back tf registers is unnecessary for
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* so reading back tf registers is unnecessary for
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@ -868,6 +874,7 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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void __iomem *host_base = NULL;
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void __iomem *host_base = NULL;
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void __iomem *port_base = NULL;
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void __iomem *port_base = NULL;
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int i, rc;
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int i, rc;
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u32 tmp;
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if (!printed_version++)
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
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dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
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@ -941,13 +948,23 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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/* GPIO off */
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/* GPIO off */
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writel(0, host_base + HOST_FLASH_CMD);
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writel(0, host_base + HOST_FLASH_CMD);
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/* Apply workaround for completion IRQ loss on PCI-X errata */
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if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
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tmp = readl(host_base + HOST_CTRL);
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if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
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dev_printk(KERN_INFO, &pdev->dev,
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"Applying completion IRQ loss on PCI-X "
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"errata fix\n");
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else
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probe_ent->host_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
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}
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/* clear global reset & mask interrupts during initialization */
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/* clear global reset & mask interrupts during initialization */
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writel(0, host_base + HOST_CTRL);
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writel(0, host_base + HOST_CTRL);
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for (i = 0; i < probe_ent->n_ports; i++) {
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for (i = 0; i < probe_ent->n_ports; i++) {
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void __iomem *port = port_base + i * PORT_REGS_SIZE;
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void __iomem *port = port_base + i * PORT_REGS_SIZE;
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unsigned long portu = (unsigned long)port;
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unsigned long portu = (unsigned long)port;
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u32 tmp;
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probe_ent->port[i].cmd_addr = portu + PORT_PRB;
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probe_ent->port[i].cmd_addr = portu + PORT_PRB;
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probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
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probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
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@ -969,6 +986,12 @@ static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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"failed to clear port RST\n");
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"failed to clear port RST\n");
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}
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}
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/* Configure IRQ WoC */
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if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC)
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writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
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else
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writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
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/* Zero error counters. */
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/* Zero error counters. */
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writel(0x8000, port + PORT_DECODE_ERR_THRESH);
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writel(0x8000, port + PORT_DECODE_ERR_THRESH);
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writel(0x8000, port + PORT_CRC_ERR_THRESH);
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writel(0x8000, port + PORT_CRC_ERR_THRESH);
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