mvebu fixes for 4.2 (part 0)
Fix legacy dove IRQ numbers -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlWSPfkACgkQCwYYjhRyO9VKKgCgmYkea99EaF8JyQnYxr5pAxGp c1cAn39dJD1oblKHzFl7BiUjNaigbXIp =kPSW -----END PGP SIGNATURE----- Merge tag 'mvebu-fixes-4.2-0' of git://git.infradead.org/linux-mvebu into next/late Merge "ARM: mvebu: fixes for v4.2" from Gregory Clement: mvebu fixes for 4.2 (part 0) Fix legacy dove IRQ numbers * tag 'mvebu-fixes-4.2-0' of git://git.infradead.org/linux-mvebu: ARM: dove: fix legacy dove IRQ numbers ARM: mvebu: fix suspend to RAM on big-endian configurations
This commit is contained in:
Kevin Hilman
commit
375d610ff5
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@ -14,73 +14,73 @@
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/*
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* Dove Low Interrupt Controller
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*/
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#define IRQ_DOVE_BRIDGE 0
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#define IRQ_DOVE_H2C 1
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#define IRQ_DOVE_C2H 2
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#define IRQ_DOVE_NAND 3
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#define IRQ_DOVE_PDMA 4
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#define IRQ_DOVE_SPI1 5
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#define IRQ_DOVE_SPI0 6
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#define IRQ_DOVE_UART_0 7
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#define IRQ_DOVE_UART_1 8
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#define IRQ_DOVE_UART_2 9
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#define IRQ_DOVE_UART_3 10
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#define IRQ_DOVE_I2C 11
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#define IRQ_DOVE_GPIO_0_7 12
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#define IRQ_DOVE_GPIO_8_15 13
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#define IRQ_DOVE_GPIO_16_23 14
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#define IRQ_DOVE_PCIE0_ERR 15
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#define IRQ_DOVE_PCIE0 16
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#define IRQ_DOVE_PCIE1_ERR 17
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#define IRQ_DOVE_PCIE1 18
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#define IRQ_DOVE_I2S0 19
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#define IRQ_DOVE_I2S0_ERR 20
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#define IRQ_DOVE_I2S1 21
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#define IRQ_DOVE_I2S1_ERR 22
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#define IRQ_DOVE_USB_ERR 23
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#define IRQ_DOVE_USB0 24
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#define IRQ_DOVE_USB1 25
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#define IRQ_DOVE_GE00_RX 26
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#define IRQ_DOVE_GE00_TX 27
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#define IRQ_DOVE_GE00_MISC 28
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#define IRQ_DOVE_GE00_SUM 29
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#define IRQ_DOVE_GE00_ERR 30
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#define IRQ_DOVE_CRYPTO 31
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#define IRQ_DOVE_BRIDGE (1 + 0)
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#define IRQ_DOVE_H2C (1 + 1)
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#define IRQ_DOVE_C2H (1 + 2)
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#define IRQ_DOVE_NAND (1 + 3)
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#define IRQ_DOVE_PDMA (1 + 4)
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#define IRQ_DOVE_SPI1 (1 + 5)
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#define IRQ_DOVE_SPI0 (1 + 6)
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#define IRQ_DOVE_UART_0 (1 + 7)
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#define IRQ_DOVE_UART_1 (1 + 8)
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#define IRQ_DOVE_UART_2 (1 + 9)
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#define IRQ_DOVE_UART_3 (1 + 10)
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#define IRQ_DOVE_I2C (1 + 11)
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#define IRQ_DOVE_GPIO_0_7 (1 + 12)
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#define IRQ_DOVE_GPIO_8_15 (1 + 13)
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#define IRQ_DOVE_GPIO_16_23 (1 + 14)
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#define IRQ_DOVE_PCIE0_ERR (1 + 15)
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#define IRQ_DOVE_PCIE0 (1 + 16)
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#define IRQ_DOVE_PCIE1_ERR (1 + 17)
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#define IRQ_DOVE_PCIE1 (1 + 18)
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#define IRQ_DOVE_I2S0 (1 + 19)
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#define IRQ_DOVE_I2S0_ERR (1 + 20)
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#define IRQ_DOVE_I2S1 (1 + 21)
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#define IRQ_DOVE_I2S1_ERR (1 + 22)
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#define IRQ_DOVE_USB_ERR (1 + 23)
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#define IRQ_DOVE_USB0 (1 + 24)
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#define IRQ_DOVE_USB1 (1 + 25)
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#define IRQ_DOVE_GE00_RX (1 + 26)
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#define IRQ_DOVE_GE00_TX (1 + 27)
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#define IRQ_DOVE_GE00_MISC (1 + 28)
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#define IRQ_DOVE_GE00_SUM (1 + 29)
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#define IRQ_DOVE_GE00_ERR (1 + 30)
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#define IRQ_DOVE_CRYPTO (1 + 31)
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/*
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* Dove High Interrupt Controller
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*/
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#define IRQ_DOVE_AC97 32
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#define IRQ_DOVE_PMU 33
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#define IRQ_DOVE_CAM 34
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#define IRQ_DOVE_SDIO0 35
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#define IRQ_DOVE_SDIO1 36
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#define IRQ_DOVE_SDIO0_WAKEUP 37
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#define IRQ_DOVE_SDIO1_WAKEUP 38
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#define IRQ_DOVE_XOR_00 39
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#define IRQ_DOVE_XOR_01 40
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#define IRQ_DOVE_XOR0_ERR 41
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#define IRQ_DOVE_XOR_10 42
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#define IRQ_DOVE_XOR_11 43
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#define IRQ_DOVE_XOR1_ERR 44
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#define IRQ_DOVE_LCD_DCON 45
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#define IRQ_DOVE_LCD1 46
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#define IRQ_DOVE_LCD0 47
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#define IRQ_DOVE_GPU 48
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#define IRQ_DOVE_PERFORM_MNTR 49
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#define IRQ_DOVE_VPRO_DMA1 51
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#define IRQ_DOVE_SSP_TIMER 54
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#define IRQ_DOVE_SSP 55
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#define IRQ_DOVE_MC_L2_ERR 56
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#define IRQ_DOVE_CRYPTO_ERR 59
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#define IRQ_DOVE_GPIO_24_31 60
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#define IRQ_DOVE_HIGH_GPIO 61
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#define IRQ_DOVE_SATA 62
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#define IRQ_DOVE_AC97 (1 + 32)
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#define IRQ_DOVE_PMU (1 + 33)
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#define IRQ_DOVE_CAM (1 + 34)
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#define IRQ_DOVE_SDIO0 (1 + 35)
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#define IRQ_DOVE_SDIO1 (1 + 36)
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#define IRQ_DOVE_SDIO0_WAKEUP (1 + 37)
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#define IRQ_DOVE_SDIO1_WAKEUP (1 + 38)
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#define IRQ_DOVE_XOR_00 (1 + 39)
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#define IRQ_DOVE_XOR_01 (1 + 40)
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#define IRQ_DOVE_XOR0_ERR (1 + 41)
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#define IRQ_DOVE_XOR_10 (1 + 42)
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#define IRQ_DOVE_XOR_11 (1 + 43)
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#define IRQ_DOVE_XOR1_ERR (1 + 44)
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#define IRQ_DOVE_LCD_DCON (1 + 45)
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#define IRQ_DOVE_LCD1 (1 + 46)
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#define IRQ_DOVE_LCD0 (1 + 47)
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#define IRQ_DOVE_GPU (1 + 48)
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#define IRQ_DOVE_PERFORM_MNTR (1 + 49)
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#define IRQ_DOVE_VPRO_DMA1 (1 + 51)
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#define IRQ_DOVE_SSP_TIMER (1 + 54)
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#define IRQ_DOVE_SSP (1 + 55)
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#define IRQ_DOVE_MC_L2_ERR (1 + 56)
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#define IRQ_DOVE_CRYPTO_ERR (1 + 59)
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#define IRQ_DOVE_GPIO_24_31 (1 + 60)
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#define IRQ_DOVE_HIGH_GPIO (1 + 61)
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#define IRQ_DOVE_SATA (1 + 62)
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/*
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* DOVE General Purpose Pins
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*/
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#define IRQ_DOVE_GPIO_START 64
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#define IRQ_DOVE_GPIO_START 65
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#define NR_GPIO_IRQS 64
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/*
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@ -126,14 +126,14 @@ __exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
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stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
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stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
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if (stat) {
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unsigned int hwirq = __fls(stat);
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unsigned int hwirq = 1 + __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
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stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
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if (stat) {
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unsigned int hwirq = 32 + __fls(stat);
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unsigned int hwirq = 33 + __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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@ -144,8 +144,8 @@ void __init dove_init_irq(void)
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{
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int i;
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orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
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orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
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orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
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orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
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#ifdef CONFIG_MULTI_IRQ_HANDLER
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set_handle_irq(dove_legacy_handle_irq);
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@ -43,6 +43,9 @@ static void mvebu_armada_xp_gp_pm_enter(void __iomem *sdram_reg, u32 srcmd)
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for (i = 0; i < ARMADA_XP_GP_PIC_NR_GPIOS; i++)
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ackcmd |= BIT(pic_raw_gpios[i]);
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srcmd = cpu_to_le32(srcmd);
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ackcmd = cpu_to_le32(ackcmd);
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/*
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* Wait a while, the PIC needs quite a bit of time between the
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* two GPIO commands.
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