Merge 3.15-rc3 into staging-next
This commit is contained in:
commit
37aa48368f
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 15
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc2
|
||||
EXTRAVERSION = -rc3
|
||||
NAME = Shuffling Zombie Juror
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -30,9 +30,9 @@ config ARM
|
|||
select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
|
||||
select HAVE_ARCH_TRACEHOOK
|
||||
select HAVE_BPF_JIT
|
||||
select HAVE_CC_STACKPROTECTOR
|
||||
select HAVE_CONTEXT_TRACKING
|
||||
select HAVE_C_RECORDMCOUNT
|
||||
select HAVE_CC_STACKPROTECTOR
|
||||
select HAVE_DEBUG_KMEMLEAK
|
||||
select HAVE_DMA_API_DEBUG
|
||||
select HAVE_DMA_ATTRS
|
||||
|
@ -311,6 +311,7 @@ config ARCH_MULTIPLATFORM
|
|||
select ARM_HAS_SG_CHAIN
|
||||
select ARM_PATCH_PHYS_VIRT
|
||||
select AUTO_ZRELADDR
|
||||
select CLKSRC_OF
|
||||
select COMMON_CLK
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select MULTI_IRQ_HANDLER
|
||||
|
@ -422,8 +423,8 @@ config ARCH_EFM32
|
|||
bool "Energy Micro efm32"
|
||||
depends on !MMU
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select AUTO_ZRELADDR
|
||||
select ARM_NVIC
|
||||
select AUTO_ZRELADDR
|
||||
select CLKSRC_OF
|
||||
select COMMON_CLK
|
||||
select CPU_V7M
|
||||
|
@ -511,8 +512,8 @@ config ARCH_IXP4XX
|
|||
bool "IXP4xx-based"
|
||||
depends on MMU
|
||||
select ARCH_HAS_DMA_SET_COHERENT_MASK
|
||||
select ARCH_SUPPORTS_BIG_ENDIAN
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select ARCH_SUPPORTS_BIG_ENDIAN
|
||||
select CLKSRC_MMIO
|
||||
select CPU_XSCALE
|
||||
select DMABOUNCE if PCI
|
||||
|
@ -1110,9 +1111,9 @@ config ARM_NR_BANKS
|
|||
default 8
|
||||
|
||||
config IWMMXT
|
||||
bool "Enable iWMMXt support" if !CPU_PJ4
|
||||
depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
|
||||
default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
|
||||
bool "Enable iWMMXt support"
|
||||
depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
|
||||
default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
|
||||
help
|
||||
Enable support for iWMMXt context switching at run time if
|
||||
running on a CPU that supports it.
|
||||
|
@ -1575,8 +1576,8 @@ config BIG_LITTLE
|
|||
config BL_SWITCHER
|
||||
bool "big.LITTLE switcher support"
|
||||
depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
|
||||
select CPU_PM
|
||||
select ARM_CPU_SUSPEND
|
||||
select CPU_PM
|
||||
help
|
||||
The big.LITTLE "switcher" provides the core functionality to
|
||||
transparently handle transition between a cluster of A15's
|
||||
|
@ -1920,9 +1921,9 @@ config XEN
|
|||
depends on CPU_V7 && !CPU_V6
|
||||
depends on !GENERIC_ATOMIC64
|
||||
depends on MMU
|
||||
select ARCH_DMA_ADDR_T_64BIT
|
||||
select ARM_PSCI
|
||||
select SWIOTLB_XEN
|
||||
select ARCH_DMA_ADDR_T_64BIT
|
||||
help
|
||||
Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
|
||||
|
||||
|
|
|
@ -1030,9 +1030,9 @@ config DEBUG_UART_PHYS
|
|||
default 0x40100000 if DEBUG_PXA_UART1
|
||||
default 0x42000000 if ARCH_GEMINI
|
||||
default 0x7c0003f8 if FOOTBRIDGE
|
||||
default 0x80230000 if DEBUG_PICOXCELL_UART
|
||||
default 0x80070000 if DEBUG_IMX23_UART
|
||||
default 0x80074000 if DEBUG_IMX28_UART
|
||||
default 0x80230000 if DEBUG_PICOXCELL_UART
|
||||
default 0x808c0000 if ARCH_EP93XX
|
||||
default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
|
||||
default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX
|
||||
|
@ -1096,22 +1096,22 @@ config DEBUG_UART_VIRT
|
|||
default 0xfeb26000 if DEBUG_RK3X_UART1
|
||||
default 0xfeb30c00 if DEBUG_KEYSTONE_UART0
|
||||
default 0xfeb31000 if DEBUG_KEYSTONE_UART1
|
||||
default 0xfec12000 if DEBUG_MVEBU_UART || DEBUG_MVEBU_UART_ALTERNATE
|
||||
default 0xfed60000 if DEBUG_RK29_UART0
|
||||
default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
|
||||
default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
|
||||
default 0xfec02000 if DEBUG_SOCFPGA_UART
|
||||
default 0xfec12000 if DEBUG_MVEBU_UART || DEBUG_MVEBU_UART_ALTERNATE
|
||||
default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
|
||||
default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
|
||||
default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2
|
||||
default 0xfed12000 if ARCH_KIRKWOOD
|
||||
default 0xfed60000 if DEBUG_RK29_UART0
|
||||
default 0xfed64000 if DEBUG_RK29_UART1 || DEBUG_RK3X_UART2
|
||||
default 0xfed68000 if DEBUG_RK29_UART2 || DEBUG_RK3X_UART3
|
||||
default 0xfedc0000 if ARCH_EP93XX
|
||||
default 0xfee003f8 if FOOTBRIDGE
|
||||
default 0xfee20000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
|
||||
default 0xfef36000 if DEBUG_HIGHBANK_UART
|
||||
default 0xfee82340 if ARCH_IOP13XX
|
||||
default 0xfef00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
|
||||
default 0xfef00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN
|
||||
default 0xfef36000 if DEBUG_HIGHBANK_UART
|
||||
default 0xfefff700 if ARCH_IOP33X
|
||||
default 0xff003000 if DEBUG_U300_UART
|
||||
default DEBUG_UART_PHYS if !MMU
|
||||
|
|
|
@ -51,10 +51,9 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
|
|||
|
||||
dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
|
||||
dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
|
||||
dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
|
||||
bcm21664-garnet.dtb
|
||||
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
|
||||
dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
|
||||
dtb-$(CONFIG_ARCH_BERLIN) += \
|
||||
berlin2-sony-nsz-gs7.dtb \
|
||||
berlin2cd-google-chromecast.dtb
|
||||
|
@ -246,6 +245,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
|
|||
omap3-sbc-t3730.dtb \
|
||||
omap3-devkit8000.dtb \
|
||||
omap3-beagle-xm.dtb \
|
||||
omap3-beagle-xm-ab.dtb \
|
||||
omap3-evm.dtb \
|
||||
omap3-evm-37xx.dtb \
|
||||
omap3-ldp.dtb \
|
||||
|
@ -294,13 +294,6 @@ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
|
|||
dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
|
||||
qcom-msm8960-cdp.dtb \
|
||||
qcom-apq8074-dragonboard.dtb
|
||||
dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
|
||||
ste-hrefprev60-stuib.dtb \
|
||||
ste-hrefprev60-tvk.dtb \
|
||||
ste-hrefv60plus-stuib.dtb \
|
||||
ste-hrefv60plus-tvk.dtb \
|
||||
ste-ccu8540.dtb \
|
||||
ste-ccu9540.dtb
|
||||
dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
|
||||
dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
|
||||
s3c6410-smdk6410.dtb
|
||||
|
@ -369,9 +362,16 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
|
|||
tegra30-cardhu-a04.dtb \
|
||||
tegra114-dalmore.dtb \
|
||||
tegra124-venice2.dtb
|
||||
dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
|
||||
dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
|
||||
ste-hrefprev60-stuib.dtb \
|
||||
ste-hrefprev60-tvk.dtb \
|
||||
ste-hrefv60plus-stuib.dtb \
|
||||
ste-hrefv60plus-tvk.dtb \
|
||||
ste-ccu8540.dtb \
|
||||
ste-ccu9540.dtb
|
||||
dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
|
||||
versatile-pb.dtb
|
||||
dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
|
||||
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
|
||||
vexpress-v2p-ca9.dtb \
|
||||
vexpress-v2p-ca15-tc1.dtb \
|
||||
|
|
|
@ -183,7 +183,7 @@
|
|||
&usb {
|
||||
status = "okay";
|
||||
|
||||
control@44e10000 {
|
||||
control@44e10620 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -204,7 +204,7 @@
|
|||
dr_mode = "host";
|
||||
};
|
||||
|
||||
dma-controller@07402000 {
|
||||
dma-controller@47402000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
|
@ -301,8 +301,8 @@
|
|||
|
||||
am335x_evm_audio_pins: am335x_evm_audio_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */
|
||||
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */
|
||||
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
|
||||
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
|
||||
0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
|
||||
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
|
||||
>;
|
||||
|
@ -331,7 +331,7 @@
|
|||
&usb {
|
||||
status = "okay";
|
||||
|
||||
control@44e10000 {
|
||||
control@44e10620 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -352,7 +352,7 @@
|
|||
dr_mode = "host";
|
||||
};
|
||||
|
||||
dma-controller@07402000 {
|
||||
dma-controller@47402000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
|
@ -364,7 +364,7 @@
|
|||
&usb {
|
||||
status = "okay";
|
||||
|
||||
control@44e10000 {
|
||||
control@44e10620 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -385,7 +385,7 @@
|
|||
dr_mode = "host";
|
||||
};
|
||||
|
||||
dma-controller@07402000 {
|
||||
dma-controller@47402000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
|
@ -118,7 +118,6 @@
|
|||
reg = <0 0 0>; /* CS0, offset 0 */
|
||||
nand-bus-width = <8>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
gpmc,device-nand = "true";
|
||||
gpmc,device-width = <1>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
|
@ -202,7 +201,7 @@
|
|||
&usb {
|
||||
status = "okay";
|
||||
|
||||
control@44e10000 {
|
||||
control@44e10620 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -223,7 +222,7 @@
|
|||
dr_mode = "host";
|
||||
};
|
||||
|
||||
dma-controller@07402000 {
|
||||
dma-controller@47402000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
|
@ -72,7 +72,7 @@
|
|||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is uses for IPs
|
||||
* The soc node represents the soc top level view. It is used for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
|
@ -94,8 +94,8 @@
|
|||
|
||||
/*
|
||||
* XXX: Use a flat representation of the AM33XX interconnect.
|
||||
* The real AM33XX interconnect network is quite complex.Since
|
||||
* that will not bring real advantage to represent that in DT
|
||||
* The real AM33XX interconnect network is quite complex. Since
|
||||
* it will not bring real advantage to represent that in DT
|
||||
* for the moment, just use a fake OCP bus entry to represent
|
||||
* the whole bus hierarchy.
|
||||
*/
|
||||
|
|
|
@ -230,6 +230,7 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
reg = <0x72004 0x4>;
|
||||
clocks = <&gateclk 4>;
|
||||
};
|
||||
|
||||
eth1: ethernet@74000 {
|
||||
|
|
|
@ -336,6 +336,7 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
reg = <0x72004 0x4>;
|
||||
clocks = <&gateclk 4>;
|
||||
};
|
||||
|
||||
coredivclk: clock@e4250 {
|
||||
|
|
|
@ -80,7 +80,7 @@
|
|||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is uses for IPs
|
||||
* The soc node represents the soc top level view. It is used for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
|
@ -94,7 +94,7 @@
|
|||
/*
|
||||
* XXX: Use a flat representation of the SOC interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
* Since that will not bring real advantage to represent that in DT for
|
||||
* Since it will not bring real advantage to represent that in DT for
|
||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
*/
|
||||
|
|
|
@ -1640,7 +1640,7 @@
|
|||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
|
||||
ti,bit-shift = <28>;
|
||||
ti,bit-shift = <24>;
|
||||
reg = <0x1860>;
|
||||
};
|
||||
|
||||
|
|
|
@ -56,6 +56,7 @@
|
|||
|
||||
osc {
|
||||
compatible = "fsl,imx-osc", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -29,6 +29,7 @@
|
|||
|
||||
osc26m {
|
||||
compatible = "fsl,imx-osc26m", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -48,6 +48,7 @@
|
|||
|
||||
osc26m {
|
||||
compatible = "fsl,imx-osc26m", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -53,21 +53,25 @@
|
|||
|
||||
ckil {
|
||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ckih1 {
|
||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
ckih2 {
|
||||
compatible = "fsl,imx-ckih2", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc {
|
||||
compatible = "fsl,imx-osc", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -50,21 +50,25 @@
|
|||
|
||||
ckil {
|
||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ckih1 {
|
||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
ckih2 {
|
||||
compatible = "fsl,imx-ckih2", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc {
|
||||
compatible = "fsl,imx-osc", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -17,7 +17,8 @@
|
|||
compatible = "denx,imx53-m53evk", "fsl,imx53";
|
||||
|
||||
memory {
|
||||
reg = <0x70000000 0x20000000>;
|
||||
reg = <0x70000000 0x20000000>,
|
||||
<0xb0000000 0x20000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
|
@ -193,17 +194,17 @@
|
|||
irq-trigger = <0x1>;
|
||||
|
||||
stmpe_touchscreen {
|
||||
compatible = "stmpe,ts";
|
||||
compatible = "st,stmpe-ts";
|
||||
reg = <0>;
|
||||
ts,sample-time = <4>;
|
||||
ts,mod-12b = <1>;
|
||||
ts,ref-sel = <0>;
|
||||
ts,adc-freq = <1>;
|
||||
ts,ave-ctrl = <3>;
|
||||
ts,touch-det-delay = <3>;
|
||||
ts,settling = <4>;
|
||||
ts,fraction-z = <7>;
|
||||
ts,i-drive = <1>;
|
||||
st,sample-time = <4>;
|
||||
st,mod-12b = <1>;
|
||||
st,ref-sel = <0>;
|
||||
st,adc-freq = <1>;
|
||||
st,ave-ctrl = <3>;
|
||||
st,touch-det-delay = <3>;
|
||||
st,settling = <4>;
|
||||
st,fraction-z = <7>;
|
||||
st,i-drive = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
@ -14,7 +14,8 @@
|
|||
|
||||
/ {
|
||||
memory {
|
||||
reg = <0x70000000 0x40000000>;
|
||||
reg = <0x70000000 0x20000000>,
|
||||
<0xb0000000 0x20000000>;
|
||||
};
|
||||
|
||||
display0: display@di0 {
|
||||
|
|
|
@ -25,12 +25,17 @@
|
|||
soc {
|
||||
display: display@di0 {
|
||||
compatible = "fsl,imx-parallel-display";
|
||||
crtcs = <&ipu 0>;
|
||||
interface-pix-fmt = "rgb24";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_rgb24_vga1>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
display0_in: endpoint {
|
||||
remote-endpoint = <&ipu_di0_disp0>;
|
||||
};
|
||||
};
|
||||
|
||||
display-timings {
|
||||
VGA {
|
||||
clock-frequency = <25200000>;
|
||||
|
@ -293,6 +298,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&ipu_di0_disp0 {
|
||||
remote-endpoint = <&display0_in>;
|
||||
};
|
||||
|
||||
&kpp {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_kpp>;
|
||||
|
|
|
@ -70,21 +70,25 @@
|
|||
|
||||
ckil {
|
||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ckih1 {
|
||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <22579200>;
|
||||
};
|
||||
|
||||
ckih2 {
|
||||
compatible = "fsl,imx-ckih2", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc {
|
||||
compatible = "fsl,imx-osc", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
@ -430,7 +434,7 @@
|
|||
|
||||
port {
|
||||
lvds1_in: endpoint {
|
||||
remote-endpoint = <&ipu_di0_lvds0>;
|
||||
remote-endpoint = <&ipu_di1_lvds1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
@ -19,7 +19,10 @@
|
|||
compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
|
||||
|
||||
aliases {
|
||||
gpio7 = &stmpe_gpio;
|
||||
gpio7 = &stmpe_gpio1;
|
||||
gpio8 = &stmpe_gpio2;
|
||||
stmpe-i2c0 = &stmpe1;
|
||||
stmpe-i2c1 = &stmpe2;
|
||||
};
|
||||
|
||||
memory {
|
||||
|
@ -40,13 +43,15 @@
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_otg_vbus: regulator@1 {
|
||||
reg_usb_otg_switch: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "usb_otg_vbus";
|
||||
regulator-name = "usb_otg_switch";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio7 12 0>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_host1: regulator@2 {
|
||||
|
@ -65,23 +70,23 @@
|
|||
|
||||
led-blue {
|
||||
label = "blue";
|
||||
gpios = <&stmpe_gpio 8 GPIO_ACTIVE_HIGH>;
|
||||
gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led-green {
|
||||
label = "green";
|
||||
gpios = <&stmpe_gpio 9 GPIO_ACTIVE_HIGH>;
|
||||
gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-pink {
|
||||
label = "pink";
|
||||
gpios = <&stmpe_gpio 10 GPIO_ACTIVE_HIGH>;
|
||||
gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-red {
|
||||
label = "red";
|
||||
gpios = <&stmpe_gpio 11 GPIO_ACTIVE_HIGH>;
|
||||
gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -99,7 +104,8 @@
|
|||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2
|
||||
&pinctrl_stmpe>;
|
||||
&pinctrl_stmpe1
|
||||
&pinctrl_stmpe2>;
|
||||
status = "okay";
|
||||
|
||||
pmic: pfuze100@08 {
|
||||
|
@ -205,13 +211,25 @@
|
|||
};
|
||||
};
|
||||
|
||||
stmpe: stmpe1601@40 {
|
||||
stmpe1: stmpe1601@40 {
|
||||
compatible = "st,stmpe1601";
|
||||
reg = <0x40>;
|
||||
interrupts = <30 0>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
|
||||
stmpe_gpio: stmpe_gpio {
|
||||
stmpe_gpio1: stmpe_gpio {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "st,stmpe-gpio";
|
||||
};
|
||||
};
|
||||
|
||||
stmpe2: stmpe1601@44 {
|
||||
compatible = "st,stmpe1601";
|
||||
reg = <0x44>;
|
||||
interrupts = <2 0>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
|
||||
stmpe_gpio2: stmpe_gpio {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "st,stmpe-gpio";
|
||||
};
|
||||
|
@ -273,10 +291,14 @@
|
|||
>;
|
||||
};
|
||||
|
||||
pinctrl_stmpe: stmpegrp {
|
||||
pinctrl_stmpe1: stmpe1grp {
|
||||
fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
|
||||
};
|
||||
|
||||
pinctrl_stmpe2: stmpe2grp {
|
||||
fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
||||
|
@ -293,7 +315,7 @@
|
|||
|
||||
pinctrl_usbotg: usbotggrp {
|
||||
fsl,pins = <
|
||||
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
||||
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
|
@ -344,11 +366,11 @@
|
|||
&usbh1 {
|
||||
vbus-supply = <®_usb_host1>;
|
||||
disable-over-current;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg {
|
||||
vbus-supply = <®_usb_otg_vbus>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg>;
|
||||
disable-over-current;
|
||||
|
|
|
@ -487,9 +487,6 @@
|
|||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
lvds-channel@0 {
|
||||
crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
|
|
|
@ -436,9 +436,6 @@
|
|||
|
||||
&ldb {
|
||||
status = "okay";
|
||||
lvds-channel@0 {
|
||||
crtcs = <&ipu1 0>, <&ipu1 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
|
|
|
@ -26,25 +26,25 @@
|
|||
/* GPIO16 -> AR8035 25MHz */
|
||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
|
||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
|
||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
|
||||
/* AR8035 pin strapping: IO voltage: pull up */
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||
/* AR8035 pin strapping: PHYADDR#0: pull down */
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
|
||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
|
||||
/* AR8035 pin strapping: PHYADDR#1: pull down */
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0
|
||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
|
||||
/* AR8035 pin strapping: MODE#1: pull up */
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||
/* AR8035 pin strapping: MODE#3: pull up */
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||
/* AR8035 pin strapping: MODE#0: pull down */
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
|
||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
|
||||
|
||||
/*
|
||||
* As the RMII pins are also connected to RGMII
|
||||
|
|
|
@ -10,6 +10,8 @@
|
|||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
|
@ -46,8 +48,6 @@
|
|||
intc: interrupt-controller@00a01000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x00a01000 0x1000>,
|
||||
<0x00a00100 0x100>;
|
||||
|
@ -59,16 +59,19 @@
|
|||
|
||||
ckil {
|
||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ckih1 {
|
||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc {
|
||||
compatible = "fsl,imx-osc", "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
@ -138,6 +141,12 @@
|
|||
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
|
||||
num-lanes = <1>;
|
||||
interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
|
||||
clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
|
||||
status = "disabled";
|
||||
|
|
|
@ -282,6 +282,7 @@
|
|||
MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
|
||||
MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
|
||||
MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
|
||||
MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
|
@ -68,8 +68,6 @@
|
|||
intc: interrupt-controller@00a01000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x00a01000 0x1000>,
|
||||
<0x00a00100 0x100>;
|
||||
|
@ -81,11 +79,13 @@
|
|||
|
||||
ckil {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
osc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -75,7 +75,7 @@
|
|||
m25p16@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "m25p16";
|
||||
compatible = "st,m25p16";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
mode = <0>;
|
||||
|
|
|
@ -46,7 +46,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mx25l4005a";
|
||||
compatible = "mxicy,mx25l4005a";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
mode = <0>;
|
||||
|
|
|
@ -43,7 +43,7 @@
|
|||
m25p40@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mx25l1606e";
|
||||
compatible = "mxicy,mx25l1606e";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
mode = <0>;
|
||||
|
|
|
@ -48,7 +48,7 @@
|
|||
status = "okay";
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "at,24c04";
|
||||
compatible = "atmel,24c04";
|
||||
pagesize = <16>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
|
|
@ -56,7 +56,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mx25l12805d";
|
||||
compatible = "mxicy,mx25l12805d";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <50000000>;
|
||||
mode = <0>;
|
||||
|
|
|
@ -32,7 +32,7 @@
|
|||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mx25l4005a";
|
||||
compatible = "mxicy,mx25l4005a";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <20000000>;
|
||||
mode = <0>;
|
||||
|
@ -50,7 +50,7 @@
|
|||
status = "okay";
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "at,24c04";
|
||||
compatible = "atmel,24c04";
|
||||
pagesize = <16>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
|
|
@ -104,7 +104,7 @@
|
|||
status = "okay";
|
||||
|
||||
adt7476: adt7476a@2e {
|
||||
compatible = "adt7476";
|
||||
compatible = "adi,adt7476";
|
||||
reg = <0x2e>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -94,7 +94,7 @@
|
|||
status = "okay";
|
||||
|
||||
lm85: lm85@2e {
|
||||
compatible = "lm85";
|
||||
compatible = "national,lm85";
|
||||
reg = <0x2e>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -40,7 +40,7 @@
|
|||
pinctrl-names = "default";
|
||||
|
||||
s35390a: s35390a@30 {
|
||||
compatible = "s35390a";
|
||||
compatible = "sii,s35390a";
|
||||
reg = <0x30>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -52,7 +52,7 @@
|
|||
pinctrl-names = "default";
|
||||
|
||||
s24c02: s24c02@50 {
|
||||
compatible = "24c02";
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -0,0 +1,16 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "omap3-beagle-xm.dts"
|
||||
|
||||
/ {
|
||||
/* HS USB Port 2 Power enable was inverted with the xM C */
|
||||
hsusb2_power: hsusb2_power_reg {
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
|
@ -112,7 +112,6 @@
|
|||
reg = <0 0 0>; /* CS0, offset 0 */
|
||||
nand-bus-width = <16>;
|
||||
|
||||
gpmc,device-nand;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
|
|
|
@ -368,7 +368,6 @@
|
|||
/* no elm on omap3 */
|
||||
|
||||
gpmc,mux-add-data = <0>;
|
||||
gpmc,device-nand;
|
||||
gpmc,device-width = <2>;
|
||||
gpmc,wait-pin = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
|
|
|
@ -74,7 +74,7 @@
|
|||
/*
|
||||
* XXX: Use a flat representation of the OMAP3 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
* Since that will not bring real advantage to represent that in DT for
|
||||
* Since it will not bring real advantage to represent that in DT for
|
||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
*/
|
||||
|
|
|
@ -72,7 +72,7 @@
|
|||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is uses for IPs
|
||||
* The soc node represents the soc top level view. It is used for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
|
@ -96,7 +96,7 @@
|
|||
/*
|
||||
* XXX: Use a flat representation of the OMAP4 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
* Since that will not bring real advantage to represent that in DT for
|
||||
* Since it will not bring real advantage to represent that in DT for
|
||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
*/
|
||||
|
|
|
@ -93,7 +93,7 @@
|
|||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is uses for IPs
|
||||
* The soc node represents the soc top level view. It is used for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
|
@ -107,7 +107,7 @@
|
|||
/*
|
||||
* XXX: Use a flat representation of the OMAP3 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
* Since that will not bring real advantage to represent that in DT for
|
||||
* Since it will not bring real advantage to represent that in DT for
|
||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
*/
|
||||
|
@ -813,6 +813,12 @@
|
|||
<0x4a084c00 0x40>;
|
||||
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
||||
ctrl-module = <&omap_control_usb3phy>;
|
||||
clocks = <&usb_phy_cm_clk32k>,
|
||||
<&sys_clkin>,
|
||||
<&usb_otg_ss_refclk960m>;
|
||||
clock-names = "wkupclk",
|
||||
"sysclk",
|
||||
"refclk";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -28,7 +28,6 @@
|
|||
gic: interrupt-controller@c2800000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0xc2800000 0x1000>,
|
||||
<0xc2000000 0x1000>;
|
||||
|
|
|
@ -141,12 +141,12 @@
|
|||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
renesas,gpios = "sdhi0_data4", "sdhi0_ctrl";
|
||||
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
renesas,function = "sdhi0";
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
renesas,gpios = "sdhi2_data4", "sdhi2_ctrl";
|
||||
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
renesas,function = "sdhi2";
|
||||
};
|
||||
|
||||
|
|
|
@ -230,17 +230,17 @@
|
|||
};
|
||||
|
||||
sdhi0_pins: sd0 {
|
||||
renesas,gpios = "sdhi0_data4", "sdhi0_ctrl";
|
||||
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||
renesas,function = "sdhi0";
|
||||
};
|
||||
|
||||
sdhi1_pins: sd1 {
|
||||
renesas,gpios = "sdhi1_data4", "sdhi1_ctrl";
|
||||
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||
renesas,function = "sdhi1";
|
||||
};
|
||||
|
||||
sdhi2_pins: sd2 {
|
||||
renesas,gpios = "sdhi2_data4", "sdhi2_ctrl";
|
||||
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
renesas,function = "sdhi2";
|
||||
};
|
||||
|
||||
|
|
|
@ -149,7 +149,7 @@
|
|||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>,
|
||||
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
|
@ -164,7 +164,7 @@
|
|||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_none>,
|
||||
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
|
@ -179,7 +179,7 @@
|
|||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_none>,
|
||||
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart2 */
|
||||
|
@ -187,7 +187,7 @@
|
|||
|
||||
uart3 {
|
||||
uart3_xfer: uart3-xfer {
|
||||
rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_none>,
|
||||
rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
|
||||
<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
|
|
|
@ -34,7 +34,6 @@
|
|||
gic: interrupt-controller@f0001000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0xf0001000 0x1000>,
|
||||
<0xf0000100 0x100>;
|
||||
|
|
|
@ -233,19 +233,6 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@0,70006400 {
|
||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
||||
reg = <0x0 0x70006400 0x0 0x40>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&tegra_car TEGRA124_CLK_UARTE>;
|
||||
resets = <&tegra_car 66>;
|
||||
reset-names = "serial";
|
||||
dmas = <&apbdma 20>, <&apbdma 20>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm@0,7000a000 {
|
||||
compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
|
||||
reg = <0x0 0x7000a000 0x0 0x100>;
|
||||
|
|
|
@ -25,11 +25,13 @@
|
|||
clocks {
|
||||
audio_ext {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24576000>;
|
||||
};
|
||||
|
||||
enet_ext {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -45,11 +45,13 @@
|
|||
|
||||
sxosc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
fxosc {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
};
|
||||
|
@ -72,8 +74,6 @@
|
|||
intc: interrupt-controller@40002000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x40003000 0x1000>,
|
||||
<0x40002100 0x100>;
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
clocks = <&clkc 3>;
|
||||
clock-latency = <1000>;
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
666667 1000000
|
||||
|
@ -54,6 +55,28 @@
|
|||
interrupt-parent = <&intc>;
|
||||
ranges;
|
||||
|
||||
i2c0: zynq-i2c@e0004000 {
|
||||
compatible = "cdns,i2c-r1p10";
|
||||
status = "disabled";
|
||||
clocks = <&clkc 38>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 25 4>;
|
||||
reg = <0xe0004000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
i2c1: zynq-i2c@e0005000 {
|
||||
compatible = "cdns,i2c-r1p10";
|
||||
status = "disabled";
|
||||
clocks = <&clkc 39>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <0 48 4>;
|
||||
reg = <0xe0005000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@f8f01000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
|
@ -34,6 +34,82 @@
|
|||
phy-mode = "rgmii";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
i2cswitch@74 {
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
si570: clock-generator@5d {
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
temperature-stability = <50>;
|
||||
reg = <0x5d>;
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
eeprom@54 {
|
||||
compatible = "at,24c08";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
gpio@21 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
hwmon@52 {
|
||||
compatible = "ti,ucd9248";
|
||||
reg = <52>;
|
||||
};
|
||||
hwmon@53 {
|
||||
compatible = "ti,ucd9248";
|
||||
reg = <53>;
|
||||
};
|
||||
hwmon@54 {
|
||||
compatible = "ti,ucd9248";
|
||||
reg = <54>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -35,6 +35,74 @@
|
|||
phy-mode = "rgmii";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
i2cswitch@74 {
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x74>;
|
||||
|
||||
i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
si570: clock-generator@5d {
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
temperature-stability = <50>;
|
||||
reg = <0x5d>;
|
||||
factory-fout = <156250000>;
|
||||
clock-frequency = <148500000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
eeprom@54 {
|
||||
compatible = "at,24c08";
|
||||
reg = <0x54>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
gpio@21 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
ucd90120@65 {
|
||||
compatible = "ti,ucd90120";
|
||||
reg = <0x65>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -797,10 +797,8 @@ static int __init bL_switcher_init(void)
|
|||
{
|
||||
int ret;
|
||||
|
||||
if (MAX_NR_CLUSTERS != 2) {
|
||||
pr_err("%s: only dual cluster systems are supported\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
if (!mcpm_is_available())
|
||||
return -ENODEV;
|
||||
|
||||
cpu_notifier(bL_switcher_hotplug_callback, 0);
|
||||
|
||||
|
|
|
@ -48,6 +48,11 @@ int __init mcpm_platform_register(const struct mcpm_platform_ops *ops)
|
|||
return 0;
|
||||
}
|
||||
|
||||
bool mcpm_is_available(void)
|
||||
{
|
||||
return (platform_ops) ? true : false;
|
||||
}
|
||||
|
||||
int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster)
|
||||
{
|
||||
if (!platform_ops)
|
||||
|
|
|
@ -226,7 +226,7 @@ CONFIG_USB_DWC3=m
|
|||
CONFIG_USB_TEST=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_OMAP_USB2=y
|
||||
CONFIG_OMAP_USB3=y
|
||||
CONFIG_TI_PIPE3=y
|
||||
CONFIG_AM335X_PHY_USB=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DEBUG=y
|
||||
|
|
|
@ -11,6 +11,7 @@ CONFIG_MODULES=y
|
|||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_LBDAF is not set
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
# CONFIG_ARCH_MULTI_V7 is not set
|
||||
CONFIG_ARCH_U300=y
|
||||
|
@ -21,7 +22,6 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
|
|||
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||
CONFIG_CMDLINE="root=/dev/ram0 rw rootfstype=rootfs console=ttyAMA0,115200n8 lpj=515072"
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_FPE_NWFPE=y
|
||||
# CONFIG_SUSPEND is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
|
@ -64,8 +64,8 @@ CONFIG_TMPFS=y
|
|||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
CONFIG_TIMER_STATS=y
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
|
|
|
@ -1,16 +1,16 @@
|
|||
# CONFIG_SWAP is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_ARCH_U8500=y
|
||||
CONFIG_MACH_HREFV60=y
|
||||
CONFIG_MACH_SNOWBALL=y
|
||||
CONFIG_MACH_UX500_DT=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_PREEMPT=y
|
||||
|
@ -34,16 +34,22 @@ CONFIG_IP_PNP=y
|
|||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_PHONET=y
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_CFG80211=y
|
||||
CONFIG_CFG80211_DEBUGFS=y
|
||||
CONFIG_MAC80211=y
|
||||
CONFIG_MAC80211_LEDS=y
|
||||
CONFIG_CAIF=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=65536
|
||||
CONFIG_SENSORS_BH1780=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_SMSC_PHY=y
|
||||
# CONFIG_WLAN is not set
|
||||
CONFIG_CW1200=y
|
||||
CONFIG_CW1200_WLAN_SDIO=y
|
||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
|
@ -85,15 +91,12 @@ CONFIG_AB8500_USB=y
|
|||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_ETH=m
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_UNSAFE_RESUME=y
|
||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
||||
CONFIG_MMC_ARMMMCI=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_LM3530=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_LP5521=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_AB8500=y
|
||||
|
@ -103,6 +106,11 @@ CONFIG_STE_DMA40=y
|
|||
CONFIG_STAGING=y
|
||||
CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y
|
||||
CONFIG_HSEM_U8500=y
|
||||
CONFIG_IIO=y
|
||||
CONFIG_IIO_ST_ACCEL_3AXIS=y
|
||||
CONFIG_IIO_ST_GYRO_3AXIS=y
|
||||
CONFIG_IIO_ST_MAGN_3AXIS=y
|
||||
CONFIG_IIO_ST_PRESS=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
|
@ -110,8 +118,6 @@ CONFIG_EXT2_FS_SECURITY=y
|
|||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
|
|
|
@ -222,22 +222,22 @@ static inline int cpu_is_xsc3(void)
|
|||
#endif
|
||||
|
||||
/*
|
||||
* Marvell's PJ4 core is based on V7 version. It has some modification
|
||||
* for coprocessor setting. For this reason, we need a way to distinguish
|
||||
* it.
|
||||
* Marvell's PJ4 and PJ4B cores are based on V7 version,
|
||||
* but require a specical sequence for enabling coprocessors.
|
||||
* For this reason, we need a way to distinguish them.
|
||||
*/
|
||||
#ifndef CONFIG_CPU_PJ4
|
||||
#define cpu_is_pj4() 0
|
||||
#else
|
||||
#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
|
||||
static inline int cpu_is_pj4(void)
|
||||
{
|
||||
unsigned int id;
|
||||
|
||||
id = read_cpuid_id();
|
||||
if ((id & 0xfffffff0) == 0x562f5840)
|
||||
if ((id & 0xff0fff00) == 0x560f5800)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define cpu_is_pj4() 0
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
@ -156,7 +156,7 @@
|
|||
/* Select the best insn combination to perform the */ \
|
||||
/* actual __m * __n / (__p << 64) operation. */ \
|
||||
if (!__c) { \
|
||||
asm ( "umull %Q0, %R0, %1, %Q2\n\t" \
|
||||
asm ( "umull %Q0, %R0, %Q1, %Q2\n\t" \
|
||||
"mov %Q0, #0" \
|
||||
: "=&r" (__res) \
|
||||
: "r" (__m), "r" (__n) \
|
||||
|
|
|
@ -53,6 +53,13 @@ void mcpm_set_early_poke(unsigned cpu, unsigned cluster,
|
|||
* CPU/cluster power operations API for higher subsystems to use.
|
||||
*/
|
||||
|
||||
/**
|
||||
* mcpm_is_available - returns whether MCPM is initialized and available
|
||||
*
|
||||
* This returns true or false accordingly.
|
||||
*/
|
||||
bool mcpm_is_available(void);
|
||||
|
||||
/**
|
||||
* mcpm_cpu_power_up - make given CPU in given cluster runable
|
||||
*
|
||||
|
|
|
@ -98,15 +98,25 @@ static inline void __tlb_alloc_page(struct mmu_gather *tlb)
|
|||
}
|
||||
}
|
||||
|
||||
static inline void tlb_flush_mmu(struct mmu_gather *tlb)
|
||||
static inline void tlb_flush_mmu_tlbonly(struct mmu_gather *tlb)
|
||||
{
|
||||
tlb_flush(tlb);
|
||||
}
|
||||
|
||||
static inline void tlb_flush_mmu_free(struct mmu_gather *tlb)
|
||||
{
|
||||
free_pages_and_swap_cache(tlb->pages, tlb->nr);
|
||||
tlb->nr = 0;
|
||||
if (tlb->pages == tlb->local)
|
||||
__tlb_alloc_page(tlb);
|
||||
}
|
||||
|
||||
static inline void tlb_flush_mmu(struct mmu_gather *tlb)
|
||||
{
|
||||
tlb_flush_mmu_tlbonly(tlb);
|
||||
tlb_flush_mmu_free(tlb);
|
||||
}
|
||||
|
||||
static inline void
|
||||
tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned long start, unsigned long end)
|
||||
{
|
||||
|
|
|
@ -408,6 +408,7 @@
|
|||
#define __NR_finit_module (__NR_SYSCALL_BASE+379)
|
||||
#define __NR_sched_setattr (__NR_SYSCALL_BASE+380)
|
||||
#define __NR_sched_getattr (__NR_SYSCALL_BASE+381)
|
||||
#define __NR_renameat2 (__NR_SYSCALL_BASE+382)
|
||||
|
||||
/*
|
||||
* This may need to be greater than __NR_last_syscall+1 in order to
|
||||
|
|
|
@ -79,6 +79,7 @@ obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o
|
|||
obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o
|
||||
obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o
|
||||
obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o
|
||||
obj-$(CONFIG_CPU_PJ4B) += pj4-cp0.o
|
||||
obj-$(CONFIG_IWMMXT) += iwmmxt.o
|
||||
obj-$(CONFIG_PERF_EVENTS) += perf_regs.o
|
||||
obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o
|
||||
|
|
|
@ -391,6 +391,7 @@
|
|||
CALL(sys_finit_module)
|
||||
/* 380 */ CALL(sys_sched_setattr)
|
||||
CALL(sys_sched_getattr)
|
||||
CALL(sys_renameat2)
|
||||
#ifndef syscalls_counted
|
||||
.equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
|
||||
#define syscalls_counted
|
||||
|
|
|
@ -587,7 +587,7 @@ __fixup_pv_table:
|
|||
add r6, r6, r3 @ adjust __pv_phys_pfn_offset address
|
||||
add r7, r7, r3 @ adjust __pv_offset address
|
||||
mov r0, r8, lsr #12 @ convert to PFN
|
||||
str r0, [r6, #LOW_OFFSET] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset
|
||||
str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset
|
||||
strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits
|
||||
mov r6, r3, lsr #24 @ constant for add/sub instructions
|
||||
teq r3, r6, lsl #24 @ must be 16MiB aligned
|
||||
|
|
|
@ -19,12 +19,16 @@
|
|||
#include <asm/thread_info.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
|
||||
#if defined(CONFIG_CPU_PJ4)
|
||||
#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
|
||||
#define PJ4(code...) code
|
||||
#define XSC(code...)
|
||||
#else
|
||||
#elif defined(CONFIG_CPU_MOHAWK) || \
|
||||
defined(CONFIG_CPU_XSC3) || \
|
||||
defined(CONFIG_CPU_XSCALE)
|
||||
#define PJ4(code...)
|
||||
#define XSC(code...) code
|
||||
#else
|
||||
#error "Unsupported iWMMXt architecture"
|
||||
#endif
|
||||
|
||||
#define MMX_WR0 (0x00)
|
||||
|
|
|
@ -184,3 +184,10 @@ void machine_kexec(struct kimage *image)
|
|||
|
||||
soft_restart(reboot_entry_phys);
|
||||
}
|
||||
|
||||
void arch_crash_save_vmcoreinfo(void)
|
||||
{
|
||||
#ifdef CONFIG_ARM_LPAE
|
||||
VMCOREINFO_CONFIG(ARM_LPAE);
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -45,7 +45,7 @@ static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
|
|||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static struct notifier_block iwmmxt_notifier_block = {
|
||||
static struct notifier_block __maybe_unused iwmmxt_notifier_block = {
|
||||
.notifier_call = iwmmxt_do,
|
||||
};
|
||||
|
||||
|
@ -72,6 +72,33 @@ static void __init pj4_cp_access_write(u32 value)
|
|||
: "=r" (temp) : "r" (value));
|
||||
}
|
||||
|
||||
static int __init pj4_get_iwmmxt_version(void)
|
||||
{
|
||||
u32 cp_access, wcid;
|
||||
|
||||
cp_access = pj4_cp_access_read();
|
||||
pj4_cp_access_write(cp_access | 0xf);
|
||||
|
||||
/* check if coprocessor 0 and 1 are available */
|
||||
if ((pj4_cp_access_read() & 0xf) != 0xf) {
|
||||
pj4_cp_access_write(cp_access);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* read iWMMXt coprocessor id register p1, c0 */
|
||||
__asm__ __volatile__ ("mrc p1, 0, %0, c0, c0, 0\n" : "=r" (wcid));
|
||||
|
||||
pj4_cp_access_write(cp_access);
|
||||
|
||||
/* iWMMXt v1 */
|
||||
if ((wcid & 0xffffff00) == 0x56051000)
|
||||
return 1;
|
||||
/* iWMMXt v2 */
|
||||
if ((wcid & 0xffffff00) == 0x56052000)
|
||||
return 2;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
|
||||
|
@ -79,17 +106,26 @@ static void __init pj4_cp_access_write(u32 value)
|
|||
*/
|
||||
static int __init pj4_cp0_init(void)
|
||||
{
|
||||
u32 cp_access;
|
||||
u32 __maybe_unused cp_access;
|
||||
int vers;
|
||||
|
||||
if (!cpu_is_pj4())
|
||||
return 0;
|
||||
|
||||
vers = pj4_get_iwmmxt_version();
|
||||
if (vers < 0)
|
||||
return 0;
|
||||
|
||||
#ifndef CONFIG_IWMMXT
|
||||
pr_info("PJ4 iWMMXt coprocessor detected, but kernel support is missing.\n");
|
||||
#else
|
||||
cp_access = pj4_cp_access_read() & ~0xf;
|
||||
pj4_cp_access_write(cp_access);
|
||||
|
||||
printk(KERN_INFO "PJ4 iWMMXt coprocessor enabled.\n");
|
||||
pr_info("PJ4 iWMMXt v%d coprocessor enabled.\n", vers);
|
||||
elf_hwcap |= HWCAP_IWMMXT;
|
||||
thread_register_notifier(&iwmmxt_notifier_block);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -203,9 +203,9 @@ asmlinkage long sys_oabi_fcntl64(unsigned int fd, unsigned int cmd,
|
|||
int ret;
|
||||
|
||||
switch (cmd) {
|
||||
case F_GETLKP:
|
||||
case F_SETLKP:
|
||||
case F_SETLKPW:
|
||||
case F_OFD_GETLK:
|
||||
case F_OFD_SETLK:
|
||||
case F_OFD_SETLKW:
|
||||
case F_GETLK64:
|
||||
case F_SETLK64:
|
||||
case F_SETLKW64:
|
||||
|
|
|
@ -1296,7 +1296,7 @@ static struct resource adc_resources[] = {
|
|||
};
|
||||
|
||||
static struct platform_device at91_adc_device = {
|
||||
.name = "at91_adc",
|
||||
.name = "at91sam9260-adc",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &adc_data,
|
||||
|
|
|
@ -1204,7 +1204,7 @@ static struct resource adc_resources[] = {
|
|||
};
|
||||
|
||||
static struct platform_device at91_adc_device = {
|
||||
.name = "at91_adc",
|
||||
.name = "at91sam9g45-adc",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &adc_data,
|
||||
|
|
|
@ -208,8 +208,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
* the "output_enable" bit as a gate, even though it's really just
|
||||
* enabling clock output.
|
||||
*/
|
||||
clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10);
|
||||
clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11);
|
||||
clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
|
||||
clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
|
||||
|
||||
/* name parent_name reg idx */
|
||||
clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
|
||||
|
@ -258,14 +258,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
|
||||
clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
|
||||
clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
|
||||
clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
|
||||
clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
|
||||
clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels));
|
||||
clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels));
|
||||
clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels));
|
||||
clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
|
||||
clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
|
||||
clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
|
||||
clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
|
||||
clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
|
||||
clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||
|
@ -445,6 +445,15 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
|||
clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
|
||||
}
|
||||
|
||||
clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
|
||||
clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
|
||||
clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
|
||||
clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
|
||||
clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
|
||||
|
||||
/*
|
||||
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
|
||||
* We can not get the 100MHz from the pll2_pfd0_352m.
|
||||
|
|
|
@ -48,7 +48,7 @@ static struct omap_dss_board_info rx51_dss_board_info = {
|
|||
|
||||
static int __init rx51_video_init(void)
|
||||
{
|
||||
if (!machine_is_nokia_rx51() && !of_machine_is_compatible("nokia,omap3-n900"))
|
||||
if (!machine_is_nokia_rx51())
|
||||
return 0;
|
||||
|
||||
if (omap_mux_init_gpio(RX51_LCD_RESET_GPIO, OMAP_PIN_OUTPUT)) {
|
||||
|
|
|
@ -209,7 +209,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
|
|||
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
|
||||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
|
||||
return 1;
|
||||
} else if (soc_is_am33xx() || cpu_is_omap44xx()) {
|
||||
} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
|
||||
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
|
||||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
|
||||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
|
||||
|
@ -255,7 +255,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
|
|||
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
|
||||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
|
||||
return __clk_get_rate(dd->clk_bypass);
|
||||
} else if (soc_is_am33xx() || cpu_is_omap44xx()) {
|
||||
} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
|
||||
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
|
||||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
|
||||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
|
||||
|
|
|
@ -501,7 +501,7 @@ static int gpmc_cs_delete_mem(int cs)
|
|||
int r;
|
||||
|
||||
spin_lock(&gpmc_mem_lock);
|
||||
r = release_resource(&gpmc_cs_mem[cs]);
|
||||
r = release_resource(res);
|
||||
res->start = 0;
|
||||
res->end = 0;
|
||||
spin_unlock(&gpmc_mem_lock);
|
||||
|
@ -527,6 +527,14 @@ static int gpmc_cs_remap(int cs, u32 base)
|
|||
pr_err("%s: requested chip-select is disabled\n", __func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/*
|
||||
* Make sure we ignore any device offsets from the GPMC partition
|
||||
* allocated for the chip select and that the new base confirms
|
||||
* to the GPMC 16MB minimum granularity.
|
||||
*/
|
||||
base &= ~(SZ_16M - 1);
|
||||
|
||||
gpmc_cs_get_memconf(cs, &old_base, &size);
|
||||
if (base == old_base)
|
||||
return 0;
|
||||
|
@ -586,6 +594,8 @@ EXPORT_SYMBOL(gpmc_cs_request);
|
|||
|
||||
void gpmc_cs_free(int cs)
|
||||
{
|
||||
struct resource *res = &gpmc_cs_mem[cs];
|
||||
|
||||
spin_lock(&gpmc_mem_lock);
|
||||
if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
|
||||
printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
|
||||
|
@ -594,7 +604,8 @@ void gpmc_cs_free(int cs)
|
|||
return;
|
||||
}
|
||||
gpmc_cs_disable_mem(cs);
|
||||
release_resource(&gpmc_cs_mem[cs]);
|
||||
if (res->flags)
|
||||
release_resource(res);
|
||||
gpmc_cs_set_reserved(cs, 0);
|
||||
spin_unlock(&gpmc_mem_lock);
|
||||
}
|
||||
|
|
|
@ -2546,11 +2546,12 @@ static int __init _init(struct omap_hwmod *oh, void *data)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (np)
|
||||
if (np) {
|
||||
if (of_find_property(np, "ti,no-reset-on-init", NULL))
|
||||
oh->flags |= HWMOD_INIT_NO_RESET;
|
||||
if (of_find_property(np, "ti,no-idle-on-init", NULL))
|
||||
oh->flags |= HWMOD_INIT_NO_IDLE;
|
||||
}
|
||||
|
||||
oh->_state = _HWMOD_STATE_INITIALIZED;
|
||||
|
||||
|
|
|
@ -1964,7 +1964,7 @@ static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
|
|||
static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
|
||||
.name = "usb_host_hs",
|
||||
.class = &omap3xxx_usb_host_hs_hwmod_class,
|
||||
.clkdm_name = "l3_init_clkdm",
|
||||
.clkdm_name = "usbhost_clkdm",
|
||||
.mpu_irqs = omap3xxx_usb_host_hs_irqs,
|
||||
.main_clk = "usbhost_48m_fck",
|
||||
.prcm = {
|
||||
|
@ -2047,7 +2047,7 @@ static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
|
|||
static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
|
||||
.name = "usb_tll_hs",
|
||||
.class = &omap3xxx_usb_tll_hs_hwmod_class,
|
||||
.clkdm_name = "l3_init_clkdm",
|
||||
.clkdm_name = "core_l4_clkdm",
|
||||
.mpu_irqs = omap3xxx_usb_tll_hs_irqs,
|
||||
.main_clk = "usbtll_fck",
|
||||
.prcm = {
|
||||
|
|
|
@ -330,10 +330,6 @@ void omap_sram_idle(void)
|
|||
omap3_sram_restore_context();
|
||||
omap2_sms_restore_context();
|
||||
}
|
||||
if (core_next_state == PWRDM_POWER_OFF)
|
||||
omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
|
||||
OMAP3430_GR_MOD,
|
||||
OMAP3_PRM_VOLTCTRL_OFFSET);
|
||||
}
|
||||
omap3_intc_resume_idle();
|
||||
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/mfd/asic3.h>
|
||||
#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
|
||||
|
||||
#define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO
|
||||
#define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS)
|
||||
|
|
|
@ -152,7 +152,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
|
|||
|
||||
node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
|
||||
if (!node) {
|
||||
pr_err("%s: could not find sram dt node\n", __func__);
|
||||
pr_err("%s: could not find pmu dt node\n", __func__);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
@ -992,6 +992,7 @@ static struct asoc_simple_card_info fsi_wm8978_info = {
|
|||
.platform = "sh_fsi2",
|
||||
.daifmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
|
||||
.cpu_dai = {
|
||||
.fmt = SND_SOC_DAIFMT_IB_NF,
|
||||
.name = "fsia-dai",
|
||||
},
|
||||
.codec_dai = {
|
||||
|
|
|
@ -588,14 +588,12 @@ static struct asoc_simple_card_info rsnd_card_info = {
|
|||
.card = "SSI01-AK4643",
|
||||
.codec = "ak4642-codec.2-0012",
|
||||
.platform = "rcar_sound",
|
||||
.daifmt = SND_SOC_DAIFMT_LEFT_J,
|
||||
.daifmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM,
|
||||
.cpu_dai = {
|
||||
.name = "rcar_sound",
|
||||
.fmt = SND_SOC_DAIFMT_CBS_CFS,
|
||||
},
|
||||
.codec_dai = {
|
||||
.name = "ak4642-hifi",
|
||||
.fmt = SND_SOC_DAIFMT_CBM_CFM,
|
||||
.sysclk = 11289600,
|
||||
},
|
||||
};
|
||||
|
|
|
@ -170,7 +170,7 @@ static struct clk mstp_clks[MSTP_NR] = {
|
|||
[MSTP010] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 10, 0), /* SSI2 */
|
||||
[MSTP009] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 9, 0), /* SSI3 */
|
||||
[MSTP008] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 8, 0), /* SRU */
|
||||
[MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 7, 0), /* HSPI */
|
||||
[MSTP007] = SH_CLK_MSTP32(&s_clk, MSTPCR0, 7, 0), /* HSPI */
|
||||
};
|
||||
|
||||
static struct clk_lookup lookups[] = {
|
||||
|
|
|
@ -71,7 +71,7 @@ static void clockevent_set_mode(enum clock_event_mode mode,
|
|||
static int clockevent_next_event(unsigned long evt,
|
||||
struct clock_event_device *clk_event_dev);
|
||||
|
||||
static void spear_clocksource_init(void)
|
||||
static void __init spear_clocksource_init(void)
|
||||
{
|
||||
u32 tick_rate;
|
||||
u16 val;
|
||||
|
|
|
@ -70,7 +70,4 @@ config TEGRA_AHB
|
|||
which controls AHB bus master arbitration and some
|
||||
performance parameters(priority, prefech size).
|
||||
|
||||
config TEGRA_EMC_SCALING_ENABLE
|
||||
bool "Enable scaling the memory frequency"
|
||||
|
||||
endmenu
|
||||
|
|
|
@ -51,12 +51,14 @@ static int dcscb_allcpus_mask[2];
|
|||
static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
|
||||
{
|
||||
unsigned int rst_hold, cpumask = (1 << cpu);
|
||||
unsigned int all_mask = dcscb_allcpus_mask[cluster];
|
||||
unsigned int all_mask;
|
||||
|
||||
pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
|
||||
if (cpu >= 4 || cluster >= 2)
|
||||
return -EINVAL;
|
||||
|
||||
all_mask = dcscb_allcpus_mask[cluster];
|
||||
|
||||
/*
|
||||
* Since this is called with IRQs enabled, and no arch_spin_lock_irq
|
||||
* variant exists, we need to disable IRQs manually here.
|
||||
|
@ -101,11 +103,12 @@ static void dcscb_power_down(void)
|
|||
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
||||
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
|
||||
cpumask = (1 << cpu);
|
||||
all_mask = dcscb_allcpus_mask[cluster];
|
||||
|
||||
pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
|
||||
BUG_ON(cpu >= 4 || cluster >= 2);
|
||||
|
||||
all_mask = dcscb_allcpus_mask[cluster];
|
||||
|
||||
__mcpm_cpu_going_down(cpu, cluster);
|
||||
|
||||
arch_spin_lock(&dcscb_lock);
|
||||
|
|
|
@ -392,7 +392,7 @@ static irqreturn_t ve_spc_irq_handler(int irq, void *data)
|
|||
* +--------------------------+
|
||||
* | 31 20 | 19 0 |
|
||||
* +--------------------------+
|
||||
* | u_volt | freq(kHz) |
|
||||
* | m_volt | freq(kHz) |
|
||||
* +--------------------------+
|
||||
*/
|
||||
#define MULT_FACTOR 20
|
||||
|
@ -414,7 +414,7 @@ static int ve_spc_populate_opps(uint32_t cluster)
|
|||
ret = ve_spc_read_sys_cfg(SYSCFG_SCC, off, &data);
|
||||
if (!ret) {
|
||||
opps->freq = (data & FREQ_MASK) * MULT_FACTOR;
|
||||
opps->u_volt = data >> VOLT_SHIFT;
|
||||
opps->u_volt = (data >> VOLT_SHIFT) * 1000;
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
|
|
|
@ -420,29 +420,29 @@ config CPU_32v3
|
|||
bool
|
||||
select CPU_USE_DOMAINS if MMU
|
||||
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
|
||||
select TLS_REG_EMUL if SMP || !MMU
|
||||
select NEED_KUSER_HELPERS
|
||||
select TLS_REG_EMUL if SMP || !MMU
|
||||
|
||||
config CPU_32v4
|
||||
bool
|
||||
select CPU_USE_DOMAINS if MMU
|
||||
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
|
||||
select TLS_REG_EMUL if SMP || !MMU
|
||||
select NEED_KUSER_HELPERS
|
||||
select TLS_REG_EMUL if SMP || !MMU
|
||||
|
||||
config CPU_32v4T
|
||||
bool
|
||||
select CPU_USE_DOMAINS if MMU
|
||||
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
|
||||
select TLS_REG_EMUL if SMP || !MMU
|
||||
select NEED_KUSER_HELPERS
|
||||
select TLS_REG_EMUL if SMP || !MMU
|
||||
|
||||
config CPU_32v5
|
||||
bool
|
||||
select CPU_USE_DOMAINS if MMU
|
||||
select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
|
||||
select TLS_REG_EMUL if SMP || !MMU
|
||||
select NEED_KUSER_HELPERS
|
||||
select TLS_REG_EMUL if SMP || !MMU
|
||||
|
||||
config CPU_32v6
|
||||
bool
|
||||
|
|
|
@ -1963,8 +1963,8 @@ arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size)
|
|||
mapping->nr_bitmaps = 1;
|
||||
mapping->extensions = extensions;
|
||||
mapping->base = base;
|
||||
mapping->size = bitmap_size << PAGE_SHIFT;
|
||||
mapping->bits = BITS_PER_BYTE * bitmap_size;
|
||||
mapping->size = mapping->bits << PAGE_SHIFT;
|
||||
|
||||
spin_lock_init(&mapping->lock);
|
||||
|
||||
|
|
|
@ -866,6 +866,8 @@ vfp_double_multiply_accumulate(int dd, int dn, int dm, u32 fpscr, u32 negate, ch
|
|||
vdp.sign = vfp_sign_negate(vdp.sign);
|
||||
|
||||
vfp_double_unpack(&vdn, vfp_get_double(dd));
|
||||
if (vdn.exponent == 0 && vdn.significand)
|
||||
vfp_double_normalise_denormal(&vdn);
|
||||
if (negate & NEG_SUBTRACT)
|
||||
vdn.sign = vfp_sign_negate(vdn.sign);
|
||||
|
||||
|
|
|
@ -915,6 +915,8 @@ vfp_single_multiply_accumulate(int sd, int sn, s32 m, u32 fpscr, u32 negate, cha
|
|||
v = vfp_get_float(sd);
|
||||
pr_debug("VFP: s%u = %08x\n", sd, v);
|
||||
vfp_single_unpack(&vsn, v);
|
||||
if (vsn.exponent == 0 && vsn.significand)
|
||||
vfp_single_normalise_denormal(&vsn);
|
||||
if (negate & NEG_SUBTRACT)
|
||||
vsn.sign = vfp_sign_negate(vsn.sign);
|
||||
|
||||
|
|
|
@ -323,8 +323,6 @@ menu "CPU Power Management"
|
|||
|
||||
source "drivers/cpuidle/Kconfig"
|
||||
|
||||
source "kernel/power/Kconfig"
|
||||
|
||||
source "drivers/cpufreq/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
|
|
@ -22,6 +22,9 @@ typedef struct {
|
|||
void *vdso;
|
||||
} mm_context_t;
|
||||
|
||||
#define INIT_MM_CONTEXT(name) \
|
||||
.context.id_lock = __RAW_SPIN_LOCK_UNLOCKED(name.context.id_lock),
|
||||
|
||||
#define ASID(mm) ((mm)->context.id & 0xffff)
|
||||
|
||||
extern void paging_init(void);
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
#ifndef __ASM_TLB_H
|
||||
#define __ASM_TLB_H
|
||||
|
||||
#define __tlb_remove_pmd_tlb_entry __tlb_remove_pmd_tlb_entry
|
||||
|
||||
#include <asm-generic/tlb.h>
|
||||
|
||||
|
@ -99,5 +100,10 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
|
|||
}
|
||||
#endif
|
||||
|
||||
static inline void __tlb_remove_pmd_tlb_entry(struct mmu_gather *tlb, pmd_t *pmdp,
|
||||
unsigned long address)
|
||||
{
|
||||
tlb_add_flush(tlb, address);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -403,8 +403,9 @@ __SYSCALL(378, sys_kcmp)
|
|||
__SYSCALL(379, sys_finit_module)
|
||||
__SYSCALL(380, sys_sched_setattr)
|
||||
__SYSCALL(381, sys_sched_getattr)
|
||||
__SYSCALL(382, sys_renameat2)
|
||||
|
||||
#define __NR_compat_syscalls 379
|
||||
#define __NR_compat_syscalls 383
|
||||
|
||||
/*
|
||||
* Compat syscall numbers used by the AArch64 kernel.
|
||||
|
|
|
@ -318,9 +318,6 @@ static int brk_handler(unsigned long addr, unsigned int esr,
|
|||
if (call_break_hook(regs, esr) == DBG_HOOK_HANDLED)
|
||||
return 0;
|
||||
|
||||
pr_warn("unexpected brk exception at %lx, esr=0x%x\n",
|
||||
(long)instruction_pointer(regs), esr);
|
||||
|
||||
if (!user_mode(regs))
|
||||
return -EFAULT;
|
||||
|
||||
|
|
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Reference in New Issue