From bda003036684b9779fca2b3d457621eaff9bcd0a Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Wed, 30 Jul 2014 22:50:59 +0200 Subject: [PATCH 1/6] clk: add pxa clocks infrastructure Add a the common code used by all PXA variants. This is the first step in the transition from architecture defined clocks (in arch/arm/mach-pxa) towards clock framework. The goal is to have the same features (and not all the features) of the existing clocks, and enable the transition of PXA to device-tree. All PXA rely on a "CKEN" type clock, which : - has a gate (bit in CKEN register) - is generated from a PLL, generally divided - has an alternate low power clock Each variant will specialize the CKEN clock : - pxa25x have no low power clock - pxa27x in low power use always the 13 MHz ring oscillator - pxa3xx in low power have specific dividers for each clock The device-tree provides a list of CLK_* (ex: CLK_USB or CLK_I2C) to get a handle on the clock. While pxa-clock.h will describe all the clocks of all the variants, each variant will only use a subset of it. Signed-off-by: Robert Jarzmik Signed-off-by: Mike Turquette --- drivers/clk/Makefile | 1 + drivers/clk/pxa/Makefile | 1 + drivers/clk/pxa/clk-pxa.c | 97 +++++++++++++++++++++++ drivers/clk/pxa/clk-pxa.h | 107 ++++++++++++++++++++++++++ include/dt-bindings/clock/pxa-clock.h | 77 ++++++++++++++++++ 5 files changed, 283 insertions(+) create mode 100644 drivers/clk/pxa/Makefile create mode 100644 drivers/clk/pxa/clk-pxa.c create mode 100644 drivers/clk/pxa/clk-pxa.h create mode 100644 include/dt-bindings/clock/pxa-clock.h diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f537a0b1f798..7891e4edaa07 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_ARCH_MMP) += mmp/ endif obj-$(CONFIG_PLAT_ORION) += mvebu/ obj-$(CONFIG_ARCH_MXS) += mxs/ +obj-$(CONFIG_ARCH_PXA) += pxa/ obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/ diff --git a/drivers/clk/pxa/Makefile b/drivers/clk/pxa/Makefile new file mode 100644 index 000000000000..cb2bd8ff53da --- /dev/null +++ b/drivers/clk/pxa/Makefile @@ -0,0 +1 @@ +obj-y += clk-pxa.o diff --git a/drivers/clk/pxa/clk-pxa.c b/drivers/clk/pxa/clk-pxa.c new file mode 100644 index 000000000000..ef3c05389c0a --- /dev/null +++ b/drivers/clk/pxa/clk-pxa.c @@ -0,0 +1,97 @@ +/* + * Marvell PXA family clocks + * + * Copyright (C) 2014 Robert Jarzmik + * + * Common clock code for PXA clocks ("CKEN" type clocks + DT) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + */ +#include +#include +#include +#include + +#include +#include "clk-pxa.h" + +DEFINE_SPINLOCK(lock); + +static struct clk *pxa_clocks[CLK_MAX]; +static struct clk_onecell_data onecell_data = { + .clks = pxa_clocks, + .clk_num = CLK_MAX, +}; + +#define to_pxa_clk(_hw) container_of(_hw, struct pxa_clk_cken, hw) + +static unsigned long cken_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct pxa_clk_cken *pclk = to_pxa_clk(hw); + struct clk_fixed_factor *fix; + + if (!pclk->is_in_low_power || pclk->is_in_low_power()) + fix = &pclk->lp; + else + fix = &pclk->hp; + fix->hw.clk = hw->clk; + return clk_fixed_factor_ops.recalc_rate(&fix->hw, parent_rate); +} + +static struct clk_ops cken_rate_ops = { + .recalc_rate = cken_recalc_rate, +}; + +static u8 cken_get_parent(struct clk_hw *hw) +{ + struct pxa_clk_cken *pclk = to_pxa_clk(hw); + + if (!pclk->is_in_low_power) + return 0; + return pclk->is_in_low_power() ? 0 : 1; +} + +static struct clk_ops cken_mux_ops = { + .get_parent = cken_get_parent, + .set_parent = dummy_clk_set_parent, +}; + +void __init clkdev_pxa_register(int ckid, const char *con_id, + const char *dev_id, struct clk *clk) +{ + if (!IS_ERR(clk) && (ckid != CLK_NONE)) + pxa_clocks[ckid] = clk; + if (!IS_ERR(clk)) + clk_register_clkdev(clk, con_id, dev_id); +} + +int __init clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks) +{ + int i; + struct pxa_clk_cken *pclk; + struct clk *clk; + + for (i = 0; i < nb_clks; i++) { + pclk = clks + i; + pclk->gate.lock = &lock; + clk = clk_register_composite(NULL, pclk->name, + pclk->parent_names, 2, + &pclk->hw, &cken_mux_ops, + &pclk->hw, &cken_rate_ops, + &pclk->gate.hw, &clk_gate_ops, + pclk->flags); + clkdev_pxa_register(pclk->ckid, pclk->con_id, pclk->dev_id, + clk); + } + return 0; +} + +static void __init pxa_dt_clocks_init(struct device_node *np) +{ + of_clk_add_provider(np, of_clk_src_onecell_get, &onecell_data); +} +CLK_OF_DECLARE(pxa_clks, "marvell,pxa-clocks", pxa_dt_clocks_init); diff --git a/drivers/clk/pxa/clk-pxa.h b/drivers/clk/pxa/clk-pxa.h new file mode 100644 index 000000000000..5fe219d06b49 --- /dev/null +++ b/drivers/clk/pxa/clk-pxa.h @@ -0,0 +1,107 @@ +/* + * Marvell PXA family clocks + * + * Copyright (C) 2014 Robert Jarzmik + * + * Common clock code for PXA clocks ("CKEN" type clocks + DT) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + */ +#ifndef _CLK_PXA_ +#define _CLK_PXA_ + +#define PARENTS(name) \ + static const char *name ## _parents[] __initconst +#define MUX_RO_RATE_RO_OPS(name, clk_name) \ + static struct clk_hw name ## _mux_hw; \ + static struct clk_hw name ## _rate_hw; \ + static struct clk_ops name ## _mux_ops = { \ + .get_parent = name ## _get_parent, \ + .set_parent = dummy_clk_set_parent, \ + }; \ + static struct clk_ops name ## _rate_ops = { \ + .recalc_rate = name ## _get_rate, \ + }; \ + static struct clk *clk_register_ ## name(void) \ + { \ + return clk_register_composite(NULL, clk_name, \ + name ## _parents, \ + ARRAY_SIZE(name ## _parents), \ + &name ## _mux_hw, &name ## _mux_ops, \ + &name ## _rate_hw, &name ## _rate_ops, \ + NULL, NULL, CLK_GET_RATE_NOCACHE); \ + } + +#define RATE_RO_OPS(name, clk_name) \ + static struct clk_hw name ## _rate_hw; \ + static struct clk_ops name ## _rate_ops = { \ + .recalc_rate = name ## _get_rate, \ + }; \ + static struct clk *clk_register_ ## name(void) \ + { \ + return clk_register_composite(NULL, clk_name, \ + name ## _parents, \ + ARRAY_SIZE(name ## _parents), \ + NULL, NULL, \ + &name ## _rate_hw, &name ## _rate_ops, \ + NULL, NULL, CLK_GET_RATE_NOCACHE); \ + } + +/* + * CKEN clock type + * This clock takes it source from 2 possible parents : + * - a low power parent + * - a normal parent + * + * +------------+ +-----------+ + * | Low Power | --- | x mult_lp | + * | Clock | | / div_lp |\ + * +------------+ +-----------+ \+-----+ +-----------+ + * | Mux |---| CKEN gate | + * +------------+ +-----------+ /+-----+ +-----------+ + * | High Power | | x mult_hp |/ + * | Clock | --- | / div_hp | + * +------------+ +-----------+ + */ +struct pxa_clk_cken { + struct clk_hw hw; + int ckid; + const char *name; + const char *dev_id; + const char *con_id; + const char **parent_names; + struct clk_fixed_factor lp; + struct clk_fixed_factor hp; + struct clk_gate gate; + bool (*is_in_low_power)(void); + const unsigned long flags; +}; + +#define PXA_CKEN(_dev_id, _con_id, _name, parents, _mult_lp, _div_lp, \ + _mult_hp, _div_hp, is_lp, _cken_reg, _cken_bit, flag) \ + { .ckid = CLK_ ## _name, .name = #_name, \ + .dev_id = _dev_id, .con_id = _con_id, .parent_names = parents,\ + .lp = { .mult = _mult_lp, .div = _div_lp }, \ + .hp = { .mult = _mult_hp, .div = _div_hp }, \ + .is_in_low_power = is_lp, \ + .gate = { .reg = (void __iomem *)_cken_reg, .bit_idx = _cken_bit }, \ + .flags = flag, \ + } +#define PXA_CKEN_1RATE(dev_id, con_id, name, parents, cken_reg, \ + cken_bit, flag) \ + PXA_CKEN(dev_id, con_id, name, parents, 1, 1, 1, 1, \ + NULL, cken_reg, cken_bit, flag) + +static int dummy_clk_set_parent(struct clk_hw *hw, u8 index) +{ + return 0; +} + +extern void clkdev_pxa_register(int ckid, const char *con_id, + const char *dev_id, struct clk *clk); +extern int clk_pxa_cken_init(struct pxa_clk_cken *clks, int nb_clks); + +#endif diff --git a/include/dt-bindings/clock/pxa-clock.h b/include/dt-bindings/clock/pxa-clock.h new file mode 100644 index 000000000000..e65803b1dc7e --- /dev/null +++ b/include/dt-bindings/clock/pxa-clock.h @@ -0,0 +1,77 @@ +/* + * Inspired by original work from pxa2xx-regs.h by Nicolas Pitre + * Copyright (C) 2014 Robert Jarzmik + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__ +#define __DT_BINDINGS_CLOCK_PXA2XX_H__ + +#define CLK_NONE 0 +#define CLK_1WIRE 1 +#define CLK_AC97 2 +#define CLK_AC97CONF 3 +#define CLK_ASSP 4 +#define CLK_BOOT 5 +#define CLK_BTUART 6 +#define CLK_CAMERA 7 +#define CLK_CIR 8 +#define CLK_CORE 9 +#define CLK_DMC 10 +#define CLK_FFUART 11 +#define CLK_FICP 12 +#define CLK_GPIO 13 +#define CLK_HSIO2 14 +#define CLK_HWUART 15 +#define CLK_I2C 16 +#define CLK_I2S 17 +#define CLK_IM 18 +#define CLK_INC 19 +#define CLK_ISC 20 +#define CLK_KEYPAD 21 +#define CLK_LCD 22 +#define CLK_MEMC 23 +#define CLK_MEMSTK 24 +#define CLK_MINI_IM 25 +#define CLK_MINI_LCD 26 +#define CLK_MMC 27 +#define CLK_MMC1 28 +#define CLK_MMC2 29 +#define CLK_MMC3 30 +#define CLK_MSL 31 +#define CLK_MSL0 32 +#define CLK_MVED 33 +#define CLK_NAND 34 +#define CLK_NSSP 35 +#define CLK_OSTIMER 36 +#define CLK_PWM0 37 +#define CLK_PWM1 38 +#define CLK_PWM2 39 +#define CLK_PWM3 40 +#define CLK_PWRI2C 41 +#define CLK_PXA300_GCU 42 +#define CLK_PXA320_GCU 43 +#define CLK_SMC 44 +#define CLK_SSP 45 +#define CLK_SSP1 46 +#define CLK_SSP2 47 +#define CLK_SSP3 48 +#define CLK_SSP4 49 +#define CLK_STUART 50 +#define CLK_TOUCH 51 +#define CLK_TPM 52 +#define CLK_UDC 53 +#define CLK_USB 54 +#define CLK_USB2 55 +#define CLK_USBH 56 +#define CLK_USBHOST 57 +#define CLK_USIM 58 +#define CLK_USIM1 59 +#define CLK_USMI0 60 +#define CLK_MAX 61 + +#endif From 53f3394a0fe97420ec260e4dad7854add90a66dd Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Wed, 30 Jul 2014 22:51:00 +0200 Subject: [PATCH 2/6] clk: dts: document pxa clock binding Document the device-tree binding of Marvell PXA based SoCs. PXA clocks are mostly fixed rate and fixed ratio clocks derived from an external oscillator, and gated by a register set (CKEN or CKEN*). Signed-off-by: Robert Jarzmik Signed-off-by: Mike Turquette --- .../devicetree/bindings/clock/pxa-clock.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/pxa-clock.txt diff --git a/Documentation/devicetree/bindings/clock/pxa-clock.txt b/Documentation/devicetree/bindings/clock/pxa-clock.txt new file mode 100644 index 000000000000..4b4a9024bd99 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/pxa-clock.txt @@ -0,0 +1,16 @@ +* Clock bindings for Marvell PXA chips + +Required properties: +- compatible: Should be "marvell,pxa-clocks" +- #clock-cells: Should be <1> + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell (see include/.../pxa-clock.h). + +Examples: + +pxa2xx_clks: pxa2xx_clks@41300004 { + compatible = "marvell,pxa-clocks"; + #clock-cells = <1>; + status = "okay"; +}; From 108f303f0ed92549b061e08a18361ad4bd540b27 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Wed, 30 Jul 2014 22:51:01 +0200 Subject: [PATCH 3/6] arm: pxa: add clock pll selection bits Add missing bits for CCCR and CCSR : - CPLL and PPLL selection, either full speed or 13MHz - CPSR masks Signed-off-by: Robert Jarzmik Signed-off-by: Mike Turquette --- arch/arm/mach-pxa/include/mach/pxa2xx-regs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h index ee6ced1cea7f..f1dd62946b36 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h @@ -143,6 +143,16 @@ #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ +#define CCCR_CPDIS_BIT (31) +#define CCCR_PPDIS_BIT (30) +#define CCCR_LCD_26_BIT (27) +#define CCCR_A_BIT (25) + +#define CCSR_N2_MASK CCCR_N_MASK +#define CCSR_M_MASK CCCR_M_MASK +#define CCSR_L_MASK CCCR_L_MASK +#define CCSR_N2_SHIFT 7 + #define CKEN_AC97CONF (31) /* AC97 Controller Configuration */ #define CKEN_CAMERA (24) /* Camera Interface Clock Enable */ #define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */ From d40670dc616936ed12335b9408087c9923939f1f Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Wed, 30 Jul 2014 22:51:02 +0200 Subject: [PATCH 4/6] clk: add pxa27x clock drivers Move pxa27x clock drivers from arch/arm/mach-pxa to driver/clk. In the move : - convert to new clock framework legacy clocks - provide clocks as before for platform data based boards - provide clocks through devicetree Signed-off-by: Robert Jarzmik Signed-off-by: Mike Turquette --- drivers/clk/pxa/Makefile | 1 + drivers/clk/pxa/clk-pxa27x.c | 370 +++++++++++++++++++++++++++++++++++ 2 files changed, 371 insertions(+) create mode 100644 drivers/clk/pxa/clk-pxa27x.c diff --git a/drivers/clk/pxa/Makefile b/drivers/clk/pxa/Makefile index cb2bd8ff53da..4ff2abcd500b 100644 --- a/drivers/clk/pxa/Makefile +++ b/drivers/clk/pxa/Makefile @@ -1 +1,2 @@ obj-y += clk-pxa.o +obj-$(CONFIG_PXA27x) += clk-pxa27x.o diff --git a/drivers/clk/pxa/clk-pxa27x.c b/drivers/clk/pxa/clk-pxa27x.c new file mode 100644 index 000000000000..b345cc791e5d --- /dev/null +++ b/drivers/clk/pxa/clk-pxa27x.c @@ -0,0 +1,370 @@ +/* + * Marvell PXA27x family clocks + * + * Copyright (C) 2014 Robert Jarzmik + * + * Heavily inspired from former arch/arm/mach-pxa/clock.c. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + */ +#include +#include +#include +#include +#include +#include + +#include +#include "clk-pxa.h" + +#define KHz 1000 +#define MHz (1000 * 1000) + +enum { + PXA_CORE_13Mhz = 0, + PXA_CORE_RUN, + PXA_CORE_TURBO, +}; + +enum { + PXA_BUS_13Mhz = 0, + PXA_BUS_RUN, +}; + +enum { + PXA_LCD_13Mhz = 0, + PXA_LCD_RUN, +}; + +enum { + PXA_MEM_13Mhz = 0, + PXA_MEM_SYSTEM_BUS, + PXA_MEM_RUN, +}; + +static const char * const get_freq_khz[] = { + "core", "run", "cpll", "memory", + "system_bus" +}; + +/* + * Get the clock frequency as reflected by CCSR and the turbo flag. + * We assume these values have been applied via a fcs. + * If info is not 0 we also display the current settings. + */ +unsigned int pxa27x_get_clk_frequency_khz(int info) +{ + struct clk *clk; + unsigned long clks[5]; + int i; + + for (i = 0; i < 5; i++) { + clk = clk_get(NULL, get_freq_khz[i]); + if (IS_ERR(clk)) { + clks[i] = 0; + } else { + clks[i] = clk_get_rate(clk); + clk_put(clk); + } + } + if (info) { + pr_info("Run Mode clock: %ld.%02ldMHz\n", + clks[1] / 1000000, (clks[1] % 1000000) / 10000); + pr_info("Turbo Mode clock: %ld.%02ldMHz\n", + clks[2] / 1000000, (clks[2] % 1000000) / 10000); + pr_info("Memory clock: %ld.%02ldMHz\n", + clks[3] / 1000000, (clks[3] % 1000000) / 10000); + pr_info("System bus clock: %ld.%02ldMHz\n", + clks[4] / 1000000, (clks[4] % 1000000) / 10000); + } + return (unsigned int)clks[0]; +} + +bool pxa27x_is_ppll_disabled(void) +{ + unsigned long ccsr = CCSR; + + return ccsr & (1 << CCCR_PPDIS_BIT); +} + +#define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \ + bit, is_lp, flags) \ + PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \ + is_lp, &CKEN, CKEN_ ## bit, flags) +#define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \ + PXA27X_CKEN(dev_id, con_id, pxa27x_pbus_parents, mult_hp, \ + div_hp, bit, pxa27x_is_ppll_disabled, 0) + +PARENTS(pxa27x_pbus) = { "osc_13mhz", "ppll_312mhz" }; +PARENTS(pxa27x_sbus) = { "system_bus", "system_bus" }; +PARENTS(pxa27x_32Mhz_bus) = { "osc_32_768khz", "osc_32_768khz" }; +PARENTS(pxa27x_lcd_bus) = { "lcd_base", "lcd_base" }; +PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" }; + +#define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \ + PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ + &CKEN, CKEN_ ## bit, 0) +#define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \ + PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \ + &CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED) + +static struct pxa_clk_cken pxa27x_clocks[] = { + PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1), + PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1), + PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1), + PXA27X_PBUS_CKEN("pxa2xx-i2s", NULL, I2S, 2, 51, 0), + PXA27X_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 19, 0), + PXA27X_PBUS_CKEN("pxa27x-udc", NULL, USB, 2, 13, 5), + PXA27X_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC, 2, 32, 0), + PXA27X_PBUS_CKEN("pxa2xx-ir", "FICPCLK", FICP, 2, 13, 0), + PXA27X_PBUS_CKEN("pxa27x-ohci", NULL, USBHOST, 2, 13, 0), + PXA27X_PBUS_CKEN("pxa2xx-i2c.1", NULL, PWRI2C, 1, 24, 0), + PXA27X_PBUS_CKEN("pxa27x-ssp.0", NULL, SSP1, 1, 24, 0), + PXA27X_PBUS_CKEN("pxa27x-ssp.1", NULL, SSP2, 1, 24, 0), + PXA27X_PBUS_CKEN("pxa27x-ssp.2", NULL, SSP3, 1, 24, 0), + PXA27X_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 24, 0), + PXA27X_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 24, 0), + PXA27X_PBUS_CKEN(NULL, "MSLCLK", MSL, 2, 13, 0), + PXA27X_PBUS_CKEN(NULL, "USIMCLK", USIM, 2, 13, 0), + PXA27X_PBUS_CKEN(NULL, "MSTKCLK", MEMSTK, 2, 32, 0), + PXA27X_PBUS_CKEN(NULL, "AC97CLK", AC97, 1, 1, 0), + PXA27X_PBUS_CKEN(NULL, "AC97CONFCLK", AC97CONF, 1, 1, 0), + PXA27X_PBUS_CKEN(NULL, "OSTIMER0", OSTIMER, 1, 96, 0), + + PXA27X_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD, + pxa27x_32Mhz_bus_parents, 0), + PXA27X_CKEN_1RATE(NULL, "IMCLK", IM, pxa27x_sbus_parents, 0), + PXA27X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, pxa27x_lcd_bus_parents, 0), + PXA27X_CKEN_1RATE("pxa27x-camera.0", NULL, CAMERA, + pxa27x_lcd_bus_parents, 0), + PXA27X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC, + pxa27x_membus_parents, 0), + +}; + +static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned long clkcfg; + unsigned int t, ht; + unsigned int l, L, n2, N; + unsigned long ccsr = CCSR; + + asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); + t = clkcfg & (1 << 0); + ht = clkcfg & (1 << 2); + + l = ccsr & CCSR_L_MASK; + n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT; + L = l * parent_rate; + N = (L * n2) / 2; + + return t ? N : L; +} +PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" }; +RATE_RO_OPS(clk_pxa27x_cpll, "cpll"); + +static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned int l, osc_forced; + unsigned long ccsr = CCSR; + unsigned long cccr = CCCR; + + l = ccsr & CCSR_L_MASK; + osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); + if (osc_forced) { + if (cccr & (1 << CCCR_LCD_26_BIT)) + return parent_rate * 2; + else + return parent_rate; + } + + if (l <= 7) + return parent_rate; + if (l <= 16) + return parent_rate / 2; + return parent_rate / 4; +} + +static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw) +{ + unsigned int osc_forced; + unsigned long ccsr = CCSR; + + osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); + if (osc_forced) + return PXA_LCD_13Mhz; + else + return PXA_LCD_RUN; +} + +PARENTS(clk_pxa27x_lcd_base) = { "osc_13mhz", "run" }; +MUX_RO_RATE_RO_OPS(clk_pxa27x_lcd_base, "lcd_base"); + +static void __init pxa27x_register_plls(void) +{ + clk_register_fixed_rate(NULL, "osc_13mhz", NULL, + CLK_GET_RATE_NOCACHE | CLK_IS_ROOT, + 13 * MHz); + clk_register_fixed_rate(NULL, "osc_32_768khz", NULL, + CLK_GET_RATE_NOCACHE | CLK_IS_ROOT, + 32768 * KHz); + clk_register_fixed_rate(NULL, "clk_dummy", NULL, CLK_IS_ROOT, 0); + clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1); +} + +static unsigned long clk_pxa27x_core_get_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned long clkcfg; + unsigned int t, ht, b, osc_forced; + unsigned long ccsr = CCSR; + + osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); + asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); + t = clkcfg & (1 << 0); + ht = clkcfg & (1 << 2); + b = clkcfg & (1 << 3); + + if (osc_forced) + return parent_rate; + if (ht) + return parent_rate / 2; + else + return parent_rate; +} + +static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw) +{ + unsigned long clkcfg; + unsigned int t, ht, b, osc_forced; + unsigned long ccsr = CCSR; + + osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); + if (osc_forced) + return PXA_CORE_13Mhz; + + asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); + t = clkcfg & (1 << 0); + ht = clkcfg & (1 << 2); + b = clkcfg & (1 << 3); + + if (ht || t) + return PXA_CORE_TURBO; + return PXA_CORE_RUN; +} +PARENTS(clk_pxa27x_core) = { "osc_13mhz", "run", "cpll" }; +MUX_RO_RATE_RO_OPS(clk_pxa27x_core, "core"); + +static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned long ccsr = CCSR; + unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT; + + return (parent_rate / n2) * 2; +} +PARENTS(clk_pxa27x_run) = { "cpll" }; +RATE_RO_OPS(clk_pxa27x_run, "run"); + +static void __init pxa27x_register_core(void) +{ + clk_register_clk_pxa27x_cpll(); + clk_register_clk_pxa27x_run(); + + clkdev_pxa_register(CLK_CORE, "core", NULL, + clk_register_clk_pxa27x_core()); +} + +static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned long clkcfg; + unsigned int b, osc_forced; + unsigned long ccsr = CCSR; + + osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); + asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg)); + b = clkcfg & (1 << 3); + + if (osc_forced) + return parent_rate; + if (b) + return parent_rate / 2; + else + return parent_rate; +} + +static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw) +{ + unsigned int osc_forced; + unsigned long ccsr = CCSR; + + osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); + if (osc_forced) + return PXA_BUS_13Mhz; + else + return PXA_BUS_RUN; +} + +PARENTS(clk_pxa27x_system_bus) = { "osc_13mhz", "run" }; +MUX_RO_RATE_RO_OPS(clk_pxa27x_system_bus, "system_bus"); + +static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned int a, l, osc_forced; + unsigned long cccr = CCCR; + unsigned long ccsr = CCSR; + + osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); + a = cccr & CCCR_A_BIT; + l = ccsr & CCSR_L_MASK; + + if (osc_forced || a) + return parent_rate; + if (l <= 10) + return parent_rate; + if (l <= 20) + return parent_rate / 2; + return parent_rate / 4; +} + +static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw) +{ + unsigned int osc_forced, a; + unsigned long cccr = CCCR; + unsigned long ccsr = CCSR; + + osc_forced = ccsr & (1 << CCCR_CPDIS_BIT); + a = cccr & CCCR_A_BIT; + if (osc_forced) + return PXA_MEM_13Mhz; + if (a) + return PXA_MEM_SYSTEM_BUS; + else + return PXA_MEM_RUN; +} + +PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" }; +MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory"); + +static void __init pxa27x_base_clocks_init(void) +{ + pxa27x_register_plls(); + pxa27x_register_core(); + clk_register_clk_pxa27x_system_bus(); + clk_register_clk_pxa27x_memory(); + clk_register_clk_pxa27x_lcd_base(); +} + +static int __init pxa27x_clocks_init(void) +{ + pxa27x_base_clocks_init(); + return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks)); +} +postcore_initcall(pxa27x_clocks_init); From 85fe55c11a410a1e26ad3cf2d7a83adf6d019d5d Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Wed, 30 Jul 2014 22:51:03 +0200 Subject: [PATCH 5/6] dts: add devicetree bindings for pxa27x clocks Add the clock tree description for the PXA27x based boards. Signed-off-by: Robert Jarzmik Signed-off-by: Mike Turquette --- arch/arm/boot/dts/pxa27x.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi index a70546945985..80fc5d7e9ef9 100644 --- a/arch/arm/boot/dts/pxa27x.dtsi +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -1,5 +1,6 @@ /* The pxa3xx skeleton simply augments the 2xx version */ -/include/ "pxa2xx.dtsi" +#include "pxa2xx.dtsi" +#include "dt-bindings/clock/pxa2xx-clock.h" / { model = "Marvell PXA27x familiy SoC"; @@ -35,4 +36,21 @@ #pwm-cells = <1>; }; }; + + clocks { + /* + * The muxing of external clocks/internal dividers for osc* clock + * sources has been hidden under the carpet by now. + */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pxa2xx_clks: pxa2xx_clks@41300004 { + compatible = "marvell,pxa-clocks"; + #clock-cells = <1>; + status = "okay"; + }; + }; + }; From 9ff25d7b58d8a4374886843ed3ed21f1ef17bf16 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Wed, 30 Jul 2014 22:51:04 +0200 Subject: [PATCH 6/6] arm: pxa: Transition pxa27x to clk framework Transition the PXA27x CPUs to the clock framework. This transition still enables legacy platforms to run without device tree as before, ie relying on platform data encoded in board specific files. Signed-off-by: Robert Jarzmik Signed-off-by: Mike Turquette --- arch/arm/Kconfig | 1 + arch/arm/mach-pxa/Makefile | 9 +- arch/arm/mach-pxa/pxa27x.c | 186 +++---------------------------------- 3 files changed, 17 insertions(+), 179 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c49a775937db..cdfd37d72ff6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -621,6 +621,7 @@ config ARCH_PXA select ARCH_REQUIRE_GPIOLIB select ARM_CPU_SUSPEND if PM select AUTO_ZRELADDR + select COMMON_CLK if PXA27x select CLKDEV_LOOKUP select CLKSRC_MMIO select CLKSRC_OF diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 2fe1824c6dcb..f09259a71913 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile @@ -3,16 +3,15 @@ # # Common support (must be linked before board specific support) -obj-y += clock.o devices.o generic.o irq.o \ - reset.o +obj-y += devices.o generic.o irq.o reset.o obj-$(CONFIG_PM) += pm.o sleep.o standby.o # Generic drivers that other drivers may depend upon # SoC-specific code -obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o -obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o -obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o +obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock.o clock-pxa2xx.o pxa2xx.o pxa25x.o +obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o +obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o obj-$(CONFIG_CPU_PXA300) += pxa300.o obj-$(CONFIG_CPU_PXA320) += pxa320.o obj-$(CONFIG_CPU_PXA930) += pxa930.o diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index b040d7d14888..668087f4e492 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -37,7 +37,8 @@ #include "generic.h" #include "devices.h" -#include "clock.h" +#include +#include void pxa27x_clear_otgph(void) { @@ -73,174 +74,6 @@ void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio) } EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset); -/* Crystal clock: 13MHz */ -#define BASE_CLK 13000000 - -/* - * Get the clock frequency as reflected by CCSR and the turbo flag. - * We assume these values have been applied via a fcs. - * If info is not 0 we also display the current settings. - */ -unsigned int pxa27x_get_clk_frequency_khz(int info) -{ - unsigned long ccsr, clkcfg; - unsigned int l, L, m, M, n2, N, S; - int cccr_a, t, ht, b; - - ccsr = CCSR; - cccr_a = CCCR & (1 << 25); - - /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ - asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); - t = clkcfg & (1 << 0); - ht = clkcfg & (1 << 2); - b = clkcfg & (1 << 3); - - l = ccsr & 0x1f; - n2 = (ccsr>>7) & 0xf; - m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; - - L = l * BASE_CLK; - N = (L * n2) / 2; - M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); - S = (b) ? L : (L/2); - - if (info) { - printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n", - L / 1000000, (L % 1000000) / 10000, l ); - printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n", - N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5, - (t) ? "" : "in" ); - printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n", - M / 1000000, (M % 1000000) / 10000, m ); - printk( KERN_INFO "System bus clock: %d.%02dMHz \n", - S / 1000000, (S % 1000000) / 10000 ); - } - - return (t) ? (N/1000) : (L/1000); -} - -/* - * Return the current mem clock frequency as reflected by CCCR[A], B, and L - */ -static unsigned long clk_pxa27x_mem_getrate(struct clk *clk) -{ - unsigned long ccsr, clkcfg; - unsigned int l, L, m, M; - int cccr_a, b; - - ccsr = CCSR; - cccr_a = CCCR & (1 << 25); - - /* Read clkcfg register: it has turbo, b, half-turbo (and f) */ - asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) ); - b = clkcfg & (1 << 3); - - l = ccsr & 0x1f; - m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4; - - L = l * BASE_CLK; - M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2)); - - return M; -} - -static const struct clkops clk_pxa27x_mem_ops = { - .enable = clk_dummy_enable, - .disable = clk_dummy_disable, - .getrate = clk_pxa27x_mem_getrate, -}; - -/* - * Return the current LCD clock frequency in units of 10kHz as - */ -static unsigned int pxa27x_get_lcdclk_frequency_10khz(void) -{ - unsigned long ccsr; - unsigned int l, L, k, K; - - ccsr = CCSR; - - l = ccsr & 0x1f; - k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4; - - L = l * BASE_CLK; - K = L / k; - - return (K / 10000); -} - -static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk) -{ - return pxa27x_get_lcdclk_frequency_10khz() * 10000; -} - -static const struct clkops clk_pxa27x_lcd_ops = { - .enable = clk_pxa2xx_cken_enable, - .disable = clk_pxa2xx_cken_disable, - .getrate = clk_pxa27x_lcd_getrate, -}; - -static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1); -static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1); -static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1); -static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0); -static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0); -static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5); -static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0); -static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0); -static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0); -static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0); -static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0); -static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0); -static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0); -static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0); -static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0); -static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0); -static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0); -static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0); -static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0); -static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0); -static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0); -static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0); -static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0); - -static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops); -static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops); -static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0); - -static struct clk_lookup pxa27x_clkregs[] = { - INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL), - INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL), - INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL), - INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL), - INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL), - INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL), - INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL), - INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL), - INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL), - INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"), - INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"), - INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL), - INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL), - INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL), - INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL), - INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL), - INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL), - INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL), - INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL), - INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"), - INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"), - INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"), - INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"), - INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"), - INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"), - INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"), - INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL), - INIT_CLKREG(&clk_dummy, "pxa27x-gpio", NULL), - INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), -}; - #ifdef CONFIG_PM #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x @@ -460,8 +293,6 @@ static int __init pxa27x_init(void) reset_status = RCSR; - clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs)); - if ((ret = pxa_init_dma(IRQ_DMA, 32))) return ret; @@ -469,10 +300,17 @@ static int __init pxa27x_init(void) register_syscore_ops(&pxa_irq_syscore_ops); register_syscore_ops(&pxa2xx_mfp_syscore_ops); - register_syscore_ops(&pxa2xx_clock_syscore_ops); - pxa_register_device(&pxa27x_device_gpio, &pxa27x_gpio_info); - ret = platform_add_devices(devices, ARRAY_SIZE(devices)); + if (!of_have_populated_dt()) { + ret = clk_register_clkdev(NULL, NULL, + "pxa27x-gpio"); + if (!ret) + pxa_register_device(&pxa27x_device_gpio, + &pxa27x_gpio_info); + if (!ret) + ret = platform_add_devices(devices, + ARRAY_SIZE(devices)); + } } return ret;