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ARM: arm-soc device tree changes, part 2 

These are mostly new device tree bindings for existing drivers, as well
 as changes to the device tree source files to add support for those
 devices, and a couple of new boards, most notably Samsung's Exynos5
 based Chromebook.
 
 The changes depend on earlier platform specific updates and touch
 the usual platforms: omap, exynos, tegra, mxs, mvebu and davinci.
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Merge tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC device tree updates (part 2) from Arnd Bergmann:
 "These are mostly new device tree bindings for existing drivers, as
  well as changes to the device tree source files to add support for
  those devices, and a couple of new boards, most notably Samsung's
  Exynos5 based Chromebook.

  The changes depend on earlier platform specific updates and touch the
  usual platforms: omap, exynos, tegra, mxs, mvebu and davinci."

* tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (169 commits)
  ARM: exynos: dts: cros5250: add EC device
  ARM: dts: Add sbs-battery for exynos5250-snow
  ARM: dts: Add i2c-arbitrator bus for exynos5250-snow
  ARM: dts: add mshc controller node for Exynos4x12 SoCs
  ARM: dts: Add chip-id controller node on Exynos4/5 SoC
  ARM: EXYNOS: Create virtual I/O mapping for Chip-ID controller using device tree
  ARM: davinci: da850-evm: add SPI flash support
  ARM: davinci: da850: override SPI DT node device name
  ARM: davinci: da850: add SPI1 DT node
  spi/davinci: add DT binding documentation
  spi/davinci: no wildcards in DT compatible property
  ARM: dts: mvebu: Convert mvebu device tree files to 64 bits
  ARM: dts: mvebu: introduce internal-regs node
  ARM: dts: mvebu: Convert all the mvebu files to use the range property
  ARM: dts: mvebu: move all peripherals inside soc
  ARM: dts: mvebu: fix cpus section indentation
  ARM: davinci: da850: add EHRPWM & ECAP DT node
  ARM/dts: OMAP3: fix pinctrl-single configuration
  ARM: dts: Add OMAP3430 SDP NOR flash memory binding
  ARM: dts: Add NOR flash bindings for OMAP2420 H4
  ...
This commit is contained in:
Linus Torvalds 2013-05-07 11:06:17 -07:00
parent fcba914542 4183bef2e0
commit 38f56f33ca
143 changed files with 7803 additions and 3100 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/omap/l3-noc.txt
View File

@ -6,6 +6,7 @@ provided by Arteris.
Required properties:
- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
Should be "ti,omap4-l3-noc" for OMAP4 family
- reg: Contains L3 register address range for each noc domain.
- ti,hwmods: "l3_main_1", ... One hwmod for each noc domain.
Examples:

17
Documentation/devicetree/bindings/arm/omap/timer.txt
View File

@ -1,7 +1,20 @@
OMAP Timer bindings
Required properties:
- compatible: Must be "ti,omap2-timer" for OMAP2+ controllers.
- compatible: Should be set to one of the below. Please note that
OMAP44xx devices have timer instances that are 100%
register compatible with OMAP3xxx devices as well as
newer timers that are not 100% register compatible.
So for OMAP44xx devices timer instances may use
different compatible strings.
ti,omap2420-timer (applicable to OMAP24xx devices)
ti,omap3430-timer (applicable to OMAP3xxx/44xx devices)
ti,omap4430-timer (applicable to OMAP44xx devices)
ti,omap5430-timer (applicable to OMAP543x devices)
ti,am335x-timer (applicable to AM335x devices)
ti,am335x-timer-1ms (applicable to AM335x devices)
- reg: Contains timer register address range (base address and
length).
- interrupts: Contains the interrupt information for the timer. The
@ -22,7 +35,7 @@ Optional properties:
Example:
timer12: timer@48304000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x48304000 0x400>;
interrupts = <95>;
ti,hwmods = "timer12"

7
Documentation/devicetree/bindings/arm/samsung/sysreg.txt Normal file
View File

@ -0,0 +1,7 @@
SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
Properties:
- name : should be 'sysreg';
- compatible : should contain "samsung,<chip name>-sysreg", "syscon";
For Exynos4 SoC series it should be "samsung,exynos4-sysreg", "syscon";
- reg : offset and length of the register set.

49
Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt
View File

@ -3,17 +3,58 @@
Required properties:
- compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx"
- reg : Should contain registers location and length
- interrupts : Should contain the interrupt numbers of DMA channels.
If a channel is empty/reserved, 0 should be filled in place.
- #dma-cells : Must be <1>. The number cell specifies the channel ID.
- dma-channels : Number of channels supported by the DMA controller
Optional properties:
- interrupt-names : Name of DMA channel interrupts
Supported chips:
imx23, imx28.
Examples:
dma-apbh@80004000 {
dma_apbh: dma-apbh@80004000 {
compatible = "fsl,imx28-dma-apbh";
reg = <0x80004000 2000>;
reg = <0x80004000 0x2000>;
interrupts = <82 83 84 85
88 88 88 88
88 88 88 88
87 86 0 0>;
interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
"gpmi0", "gmpi1", "gpmi2", "gmpi3",
"gpmi4", "gmpi5", "gpmi6", "gmpi7",
"hsadc", "lcdif", "empty", "empty";
#dma-cells = <1>;
dma-channels = <16>;
};
dma-apbx@80024000 {
dma_apbx: dma-apbx@80024000 {
compatible = "fsl,imx28-dma-apbx";
reg = <0x80024000 2000>;
reg = <0x80024000 0x2000>;
interrupts = <78 79 66 0
80 81 68 69
70 71 72 73
74 75 76 77>;
interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
"saif0", "saif1", "i2c0", "i2c1",
"auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
"auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
#dma-cells = <1>;
dma-channels = <16>;
};
DMA clients connected to the MXS DMA controller must use the format
described in the dma.txt file.
Examples:
auart0: serial@8006a000 {
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006a000 0x2000>;
interrupts = <112>;
dmas = <&dma_apbx 8>, <&dma_apbx 9>;
dma-names = "rx", "tx";
};

36
Documentation/devicetree/bindings/fb/mxsfb.txt
View File

@ -5,9 +5,16 @@ Required properties:
imx23 and imx28.
- reg: Address and length of the register set for lcdif
- interrupts: Should contain lcdif interrupts
- display : phandle to display node (see below for details)
Optional properties:
- panel-enable-gpios : Should specify the gpio for panel enable
* display node
Required properties:
- bits-per-pixel : <16> for RGB565, <32> for RGB888/666.
- bus-width : number of data lines. Could be <8>, <16>, <18> or <24>.
Required sub-node:
- display-timings : Refer to binding doc display-timing.txt for details.
Examples:
@ -15,5 +22,28 @@ lcdif@80030000 {
compatible = "fsl,imx28-lcdif";
reg = <0x80030000 2000>;
interrupts = <38 86>;
panel-enable-gpios = <&gpio3 30 0>;
display: display {
bits-per-pixel = <32>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33500000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <164>;
hback-porch = <89>;
hsync-len = <10>;
vback-porch = <23>;
vfront-porch = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};

8
Documentation/devicetree/bindings/gpio/gpio-omap.txt
View File

@ -5,12 +5,12 @@ Required properties:
- "ti,omap2-gpio" for OMAP2 controllers
- "ti,omap3-gpio" for OMAP3 controllers
- "ti,omap4-gpio" for OMAP4 controllers
- gpio-controller : Marks the device node as a GPIO controller.
- #gpio-cells : Should be two.
- first cell is the pin number
- second cell is used to specify optional parameters (unused)
- gpio-controller : Marks the device node as a GPIO controller.
- interrupt-controller: Mark the device node as an interrupt controller.
- #interrupt-cells : Should be 2.
- interrupt-controller: Mark the device node as an interrupt controller
The first cell is the GPIO number.
The second cell is used to specify flags:
bits[3:0] trigger type and level flags:
@ -32,8 +32,8 @@ Example:
gpio4: gpio4 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio4";
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};

20
Documentation/devicetree/bindings/gpu/samsung-g2d.txt Normal file
View File

@ -0,0 +1,20 @@
* Samsung 2D Graphics Accelerator
Required properties:
- compatible : value should be one among the following:
(a) "samsung,s5pv210-g2d" for G2D IP present in S5PV210 & Exynos4210 SoC
(b) "samsung,exynos4212-g2d" for G2D IP present in Exynos4x12 SoCs
(c) "samsung,exynos5250-g2d" for G2D IP present in Exynos5250 SoC
- reg : Physical base address of the IP registers and length of memory
mapped region.
- interrupts : G2D interrupt number to the CPU.
Example:
g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
interrupts = <0 89 0>;
status = "disabled";
};

12
Documentation/devicetree/bindings/i2c/i2c-mxs.txt
View File

@ -3,10 +3,13 @@
Required properties:
- compatible: Should be "fsl,<chip>-i2c"
- reg: Should contain registers location and length
- interrupts: Should contain ERROR and DMA interrupts
- interrupts: Should contain ERROR interrupt number
- clock-frequency: Desired I2C bus clock frequency in Hz.
Only 100000Hz and 400000Hz modes are supported.
- fsl,i2c-dma-channel: APBX DMA channel for the I2C
- dmas: DMA specifier, consisting of a phandle to DMA controller node
and I2C DMA channel ID.
Refer to dma.txt and fsl-mxs-dma.txt for details.
- dma-names: Must be "rx-tx".
Examples:
@ -15,7 +18,8 @@ i2c0: i2c@80058000 {
#size-cells = <0>;
compatible = "fsl,imx28-i2c";
reg = <0x80058000 2000>;
interrupts = <111 68>;
interrupts = <111>;
clock-frequency = <100000>;
fsl,i2c-dma-channel = <6>;
dmas = <&dma_apbx 6>;
dma-names = "rx-tx";
};

60
Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.txt Normal file
View File

@ -0,0 +1,60 @@
NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver.
Required properties:
- compatible : should be:
"nvidia,tegra114-i2c"
"nvidia,tegra30-i2c"
"nvidia,tegra20-i2c"
"nvidia,tegra20-i2c-dvc"
Details of compatible are as follows:
nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C
controller. This only support master mode of I2C communication. Register
interface/offset and interrupts handling are different than generic I2C
controller. Driver of DVC I2C controller is only compatible with
"nvidia,tegra20-i2c-dvc".
nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support
master and slave mode of I2C communication. The i2c-tegra driver only
support master mode of I2C communication. Driver of I2C controller is
only compatible with "nvidia,tegra20-i2c".
nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is
very much similar to Tegra20 I2C controller with additional feature:
Continue Transfer Support. This feature helps to implement M_NO_START
as per I2C core API transfer flags. Driver of I2C controller is
compatible with "nvidia,tegra30-i2c" to enable the continue transfer
support. This is also compatible with "nvidia,tegra20-i2c" without
continue transfer support.
nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is
very much similar to Tegra30 I2C controller with some hardware
modification:
- Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and
fast-clk. Tegra114 has only one clock source called as div-clk and
hence clock mechanism is changed in I2C controller.
- Tegra30/Tegra20 I2C controller has enabled per packet transfer by
default and there is no way to disable it. Tegra114 has this
interrupt disable by default and SW need to enable explicitly.
Due to above changes, Tegra114 I2C driver makes incompatible with
previous hardware driver. Hence, tegra114 I2C controller is compatible
with "nvidia,tegra114-i2c".
- reg: Should contain I2C controller registers physical address and length.
- interrupts: Should contain I2C controller interrupts.
- address-cells: Address cells for I2C device address.
- size-cells: Size of the I2C device address.
- clocks: Clock ID as per
Documentation/devicetree/bindings/clock/tegra<chip-id>.txt
for I2C controller.
- clock-names: Name of the clock:
Tegra20/Tegra30 I2C controller: "div-clk and "fast-clk".
Tegra114 I2C controller: "div-clk".
Example:
i2c@7000c000 {
compatible = "nvidia,tegra20-i2c";
reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>, <&tegra_car 124>;
clock-names = "div-clk", "fast-clk";
status = "disabled";
};

12
Documentation/devicetree/bindings/mmc/mxs-mmc.txt
View File

@ -9,15 +9,19 @@ and the properties used by the mxsmmc driver.
Required properties:
- compatible: Should be "fsl,<chip>-mmc". The supported chips include
imx23 and imx28.
- interrupts: Should contain ERROR and DMA interrupts
- fsl,ssp-dma-channel: APBH DMA channel for the SSP
- interrupts: Should contain ERROR interrupt number
- dmas: DMA specifier, consisting of a phandle to DMA controller node
and SSP DMA channel ID.
Refer to dma.txt and fsl-mxs-dma.txt for details.
- dma-names: Must be "rx-tx".
Examples:
ssp0: ssp@80010000 {
compatible = "fsl,imx28-mmc";
reg = <0x80010000 2000>;
interrupts = <96 82>;
fsl,ssp-dma-channel = <0>;
interrupts = <96>;
dmas = <&dma_apbh 0>;
dma-names = "rx-tx";
bus-width = <8>;
};

17
Documentation/devicetree/bindings/mtd/gpmi-nand.txt
View File

@ -7,10 +7,12 @@ Required properties:
- compatible : should be "fsl,<chip>-gpmi-nand"
- reg : should contain registers location and length for gpmi and bch.
- reg-names: Should contain the reg names "gpmi-nand" and "bch"
- interrupts : The first is the DMA interrupt number for GPMI.
The second is the BCH interrupt number.
- interrupt-names : The interrupt names "gpmi-dma", "bch";
- fsl,gpmi-dma-channel : Should contain the dma channel it uses.
- interrupts : BCH interrupt number.
- interrupt-names : Should be "bch".
- dmas: DMA specifier, consisting of a phandle to DMA controller node
and GPMI DMA channel ID.
Refer to dma.txt and fsl-mxs-dma.txt for details.
- dma-names: Must be "rx-tx".
Optional properties:
- nand-on-flash-bbt: boolean to enable on flash bbt option if not
@ -27,9 +29,10 @@ gpmi-nand@8000c000 {
#size-cells = <1>;
reg = <0x8000c000 2000>, <0x8000a000 2000>;
reg-names = "gpmi-nand", "bch";
interrupts = <88>, <41>;
interrupt-names = "gpmi-dma", "bch";
fsl,gpmi-dma-channel = <4>;
interrupts = <41>;
interrupt-names = "bch";
dmas = <&dma_apbh 4>;
dma-names = "rx-tx";
partition@0 {
...

4
Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt
View File

@ -70,6 +70,10 @@ Optional subnode-properties:
0: Disable the internal pull-up
1: Enable the internal pull-up
Note that when enabling the pull-up, the internal pad keeper gets disabled.
Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up
will only disable the internal pad keeper.
Examples:
pinctrl@80018000 {

8
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt
View File

@ -2,6 +2,11 @@ NVIDIA Tegra audio complex
Required properties:
- compatible : "nvidia,tegra-audio-alc5632"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
@ -56,4 +61,7 @@ sound {
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&alc5632>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

7
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt
View File

@ -2,6 +2,11 @@ NVIDIA Tegra audio complex for TrimSlice
Required properties:
- compatible : "nvidia,tegra-audio-trimslice"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
- nvidia,audio-codec : The phandle of the WM8903 audio codec
@ -11,4 +16,6 @@ sound {
compatible = "nvidia,tegra-audio-trimslice";
nvidia,i2s-controller = <&tegra_i2s1>;
nvidia,audio-codec = <&codec>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

8
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt
View File

@ -2,6 +2,11 @@ NVIDIA Tegra audio complex
Required properties:
- compatible : "nvidia,tegra-audio-wm8753"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
@ -50,5 +55,8 @@ sound {
nvidia,i2s-controller = <&i2s1>;
nvidia,audio-codec = <&wm8753>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

8
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt
View File

@ -2,6 +2,11 @@ NVIDIA Tegra audio complex
Required properties:
- compatible : "nvidia,tegra-audio-wm8903"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
@ -67,5 +72,8 @@ sound {
nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

8
Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm9712.txt
View File

@ -2,6 +2,11 @@ NVIDIA Tegra audio complex
Required properties:
- compatible : "nvidia,tegra-audio-wm9712"
- clocks : Must contain an entry for each entry in clock-names.
- clock-names : Must include the following entries:
"pll_a" (The Tegra clock of that name),
"pll_a_out0" (The Tegra clock of that name),
"mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
- nvidia,model : The user-visible name of this sound complex.
- nvidia,audio-routing : A list of the connections between audio components.
Each entry is a pair of strings, the first being the connection's sink,
@ -48,4 +53,7 @@ sound {
"Mic", "MIC1";
nvidia,ac97-controller = <&ac97>;
clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 93>;
clock-names = "pll_a", "pll_a_out0", "mclk";
};

12
Documentation/devicetree/bindings/spi/mxs-spi.txt
View File

@ -3,8 +3,11 @@
Required properties:
- compatible: Should be "fsl,<soc>-spi", where soc is "imx23" or "imx28"
- reg: Offset and length of the register set for the device
- interrupts: Should contain SSP interrupts (error irq first, dma irq second)
- fsl,ssp-dma-channel: APBX DMA channel for the SSP
- interrupts: Should contain SSP ERROR interrupt
- dmas: DMA specifier, consisting of a phandle to DMA controller node
and SSP DMA channel ID.
Refer to dma.txt and fsl-mxs-dma.txt for details.
- dma-names: Must be "rx-tx".
Optional properties:
- clock-frequency : Input clock frequency to the SPI block in Hz.
@ -17,6 +20,7 @@ ssp0: ssp@80010000 {
#size-cells = <0>;
compatible = "fsl,imx28-spi";
reg = <0x80010000 0x2000>;
interrupts = <96 82>;
fsl,ssp-dma-channel = <0>;
interrupts = <96>;
dmas = <&dma_apbh 0>;
dma-names = "rx-tx";
};

51
Documentation/devicetree/bindings/spi/spi-davinci.txt Normal file
View File

@ -0,0 +1,51 @@
Davinci SPI controller device bindings
Required properties:
- #address-cells: number of cells required to define a chip select
address on the SPI bus. Should be set to 1.
- #size-cells: should be zero.
- compatible:
- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
- reg: Offset and length of SPI controller register space
- num-cs: Number of chip selects
- ti,davinci-spi-intr-line: interrupt line used to connect the SPI
IP to the interrupt controller within the SoC. Possible values
are 0 and 1. Manual says one of the two possible interrupt
lines can be tied to the interrupt controller. Set this
based on a specifc SoC configuration.
- interrupts: interrupt number mapped to CPU.
- clocks: spi clk phandle
Example of a NOR flash slave device (n25q032) connected to DaVinci
SPI controller device over the SPI bus.
spi0:spi@20BF0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,dm6446-spi";
reg = <0x20BF0000 0x1000>;
num-cs = <4>;
ti,davinci-spi-intr-line = <0>;
interrupts = <338>;
clocks = <&clkspi>;
flash: n25q032@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32";
spi-max-frequency = <25000000>;
reg = <0>;
partition@0 {
label = "u-boot-spl";
reg = <0x0 0x80000>;
read-only;
};
partition@1 {
label = "test";
reg = <0x80000 0x380000>;
};
};
};

16
Documentation/devicetree/bindings/tty/serial/fsl-mxs-auart.txt
View File

@ -5,20 +5,18 @@ Required properties:
imx23 and imx28.
- reg : Address and length of the register set for the device
- interrupts : Should contain the auart interrupt numbers
Optional properties:
- fsl,auart-dma-channel : The DMA channels, the first is for RX, the other
is for TX. If you add this property, it also means that you
will enable the DMA support for the auart.
Note: due to the hardware bug in imx23(see errata : 2836),
only the imx28 can enable the DMA support for the auart.
- dmas: DMA specifier, consisting of a phandle to DMA controller node
and AUART DMA channel ID.
Refer to dma.txt and fsl-mxs-dma.txt for details.
- dma-names: "rx" for RX channel, "tx" for TX channel.
Example:
auart0: serial@8006a000 {
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006a000 0x2000>;
interrupts = <112 70 71>;
fsl,auart-dma-channel = <8 9>;
interrupts = <112>;
dmas = <&dma_apbx 8>, <&dma_apbx 9>;
dma-names = "rx", "tx";
};
Note: Each auart port should have an alias correctly numbered in "aliases"

10
Documentation/devicetree/bindings/usb/exynos-usb.txt
View File

@ -10,6 +10,8 @@ Required properties:
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- clocks: from common clock binding: handle to usb clock.
- clock-names: from common clock binding: Shall be "usbhost".
Optional properties:
- samsung,vbus-gpio: if present, specifies the GPIO that
@ -22,6 +24,9 @@ Example:
reg = <0x12110000 0x100>;
interrupts = <0 71 0>;
samsung,vbus-gpio = <&gpx2 6 1 3 3>;
clocks = <&clock 285>;
clock-names = "usbhost";
};
OHCI
@ -31,10 +36,15 @@ Required properties:
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- clocks: from common clock binding: handle to usb clock.
- clock-names: from common clock binding: Shall be "usbhost".
Example:
usb@12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
interrupts = <0 71 0>;
clocks = <&clock 285>;
clock-names = "usbhost";
};

1
Documentation/devicetree/bindings/usb/omap-usb.txt
View File

@ -18,6 +18,7 @@ OMAP MUSB GLUE
represents PERIPHERAL.
- power : Should be "50". This signifies the controller can supply upto
100mA when operating in host mode.
- usb-phy : the phandle for the PHY device
Optional properties:
- ctrl-module : phandle of the control module this glue uses to write to

65
Documentation/devicetree/bindings/video/samsung-fimd.txt Normal file
View File

@ -0,0 +1,65 @@
Device-Tree bindings for Samsung SoC display controller (FIMD)
FIMD (Fully Interactive Mobile Display) is the Display Controller for the
Samsung series of SoCs which transfers the image data from a video memory
buffer to an external LCD interface.
Required properties:
- compatible: value should be one of the following
"samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
"samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
"samsung,s5p6440-fimd"; /* for S5P64X0 SoCs */
"samsung,s5pc100-fimd"; /* for S5PC100 SoC */
"samsung,s5pv210-fimd"; /* for S5PV210 SoC */
"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
"samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
- reg: physical base address and length of the FIMD registers set.
- interrupt-parent: should be the phandle of the fimd controller's
parent interrupt controller.
- interrupts: should contain a list of all FIMD IP block interrupts in the
order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
format depends on the interrupt controller used.
- interrupt-names: should contain the interrupt names: "fifo", "vsync",
"lcd_sys", in the same order as they were listed in the interrupts
property.
- pinctrl-0: pin control group to be used for this controller.
- pinctrl-names: must contain a "default" entry.
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
- clock-names: list of clock names sorted in the same order as the clocks
property. Must contain "sclk_fimd" and "fimd".
Optional Properties:
- samsung,power-domain: a phandle to FIMD power domain node.
Example:
SoC specific DT entry:
fimd@11c00000 {
compatible = "samsung,exynos4210-fimd";
interrupt-parent = <&combiner>;
reg = <0x11c00000 0x20000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <11 0>, <11 1>, <11 2>;
clocks = <&clock 140>, <&clock 283>;
clock-names = "sclk_fimd", "fimd";
samsung,power-domain = <&pd_lcd0>;
status = "disabled";
};
Board specific DT entry:
fimd@11c00000 {
pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
pinctrl-names = "default";
status = "okay";
};

5
arch/arm/boot/dts/Makefile
View File

@ -53,6 +53,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos4412-smdk4412.dtb \
exynos4412-origen.dtb \
exynos5250-arndale.dtb \
exynos5440-sd5v1.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5440-ssdk5440.dtb
@ -134,10 +135,14 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
imx28-tx28.dtb
dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap3430-sdp.dtb \
omap3-beagle.dtb \
omap3-devkit8000.dtb \
omap3-beagle-xm.dtb \
omap3-evm.dtb \
omap3-tobi.dtb \
omap3-igep0020.dtb \
omap3-igep0030.dtb \
omap4-panda.dtb \
omap4-panda-a4.dtb \
omap4-panda-es.dtb \

10
arch/arm/boot/dts/am335x-bone.dts
View File

@ -43,7 +43,7 @@
status = "okay";
};
i2c1: i2c@44e0b000 {
i2c0: i2c@44e0b000 {
status = "okay";
clock-frequency = <400000>;
@ -59,27 +59,27 @@
led@2 {
label = "beaglebone:green:heartbeat";
gpios = <&gpio2 21 0>;
gpios = <&gpio1 21 0>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
led@3 {
label = "beaglebone:green:mmc0";
gpios = <&gpio2 22 0>;
gpios = <&gpio1 22 0>;
linux,default-trigger = "mmc0";
default-state = "off";
};
led@4 {
label = "beaglebone:green:usr2";
gpios = <&gpio2 23 0>;
gpios = <&gpio1 23 0>;
default-state = "off";
};
led@5 {
label = "beaglebone:green:usr3";
gpios = <&gpio2 24 0>;
gpios = <&gpio1 24 0>;
default-state = "off";
};
};

18
arch/arm/boot/dts/am335x-evm.dts
View File

@ -51,7 +51,7 @@
status = "okay";
};
i2c1: i2c@44e0b000 {
i2c0: i2c@44e0b000 {
status = "okay";
clock-frequency = <400000>;
@ -60,7 +60,7 @@
};
};
i2c2: i2c@4802a000 {
i2c1: i2c@4802a000 {
status = "okay";
clock-frequency = <100000>;
@ -123,12 +123,12 @@
debounce-delay-ms = <5>;
col-scan-delay-us = <2>;
row-gpios = <&gpio2 25 0 /* Bank1, pin25 */
&gpio2 26 0 /* Bank1, pin26 */
&gpio2 27 0>; /* Bank1, pin27 */
row-gpios = <&gpio1 25 0 /* Bank1, pin25 */
&gpio1 26 0 /* Bank1, pin26 */
&gpio1 27 0>; /* Bank1, pin27 */
col-gpios = <&gpio2 21 0 /* Bank1, pin21 */
&gpio2 22 0>; /* Bank1, pin22 */
col-gpios = <&gpio1 21 0 /* Bank1, pin21 */
&gpio1 22 0>; /* Bank1, pin22 */
linux,keymap = <0x0000008b /* MENU */
0x0100009e /* BACK */
@ -147,14 +147,14 @@
switch@9 {
label = "volume-up";
linux,code = <115>;
gpios = <&gpio1 2 1>;
gpios = <&gpio0 2 1>;
gpio-key,wakeup;
};
switch@10 {
label = "volume-down";
linux,code = <114>;
gpios = <&gpio1 3 1>;
gpios = <&gpio0 3 1>;
gpio-key,wakeup;
};
};

18
arch/arm/boot/dts/am335x-evmsk.dts
View File

@ -58,7 +58,7 @@
status = "okay";
};
i2c1: i2c@44e0b000 {
i2c0: i2c@44e0b000 {
status = "okay";
clock-frequency = <400000>;
@ -115,26 +115,26 @@
led@1 {
label = "evmsk:green:usr0";
gpios = <&gpio2 4 0>;
gpios = <&gpio1 4 0>;
default-state = "off";
};
led@2 {
label = "evmsk:green:usr1";
gpios = <&gpio2 5 0>;
gpios = <&gpio1 5 0>;
default-state = "off";
};
led@3 {
label = "evmsk:green:mmc0";
gpios = <&gpio2 6 0>;
gpios = <&gpio1 6 0>;
linux,default-trigger = "mmc0";
default-state = "off";
};
led@4 {
label = "evmsk:green:heartbeat";
gpios = <&gpio2 7 0>;
gpios = <&gpio1 7 0>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
@ -148,26 +148,26 @@
switch@1 {
label = "button0";
linux,code = <0x100>;
gpios = <&gpio3 3 0>;
gpios = <&gpio2 3 0>;
};
switch@2 {
label = "button1";
linux,code = <0x101>;
gpios = <&gpio3 2 0>;
gpios = <&gpio2 2 0>;
};
switch@3 {
label = "button2";
linux,code = <0x102>;
gpios = <&gpio1 30 0>;
gpios = <&gpio0 30 0>;
gpio-key,wakeup;
};
switch@4 {
label = "button3";
linux,code = <0x103>;
gpios = <&gpio3 5 0>;
gpios = <&gpio2 5 0>;
};
};
};

40
arch/arm/boot/dts/am33xx.dtsi
View File

@ -21,6 +21,8 @@
serial3 = &uart4;
serial4 = &uart5;
serial5 = &uart6;
d_can0 = &dcan0;
d_can1 = &dcan1;
};
cpus {
@ -87,7 +89,7 @@
reg = <0x48200000 0x1000>;
};
gpio1: gpio@44e07000 {
gpio0: gpio@44e07000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio1";
gpio-controller;
@ -98,7 +100,7 @@
interrupts = <96>;
};
gpio2: gpio@4804c000 {
gpio1: gpio@4804c000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio2";
gpio-controller;
@ -109,7 +111,7 @@
interrupts = <98>;
};
gpio3: gpio@481ac000 {
gpio2: gpio@481ac000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio3";
gpio-controller;
@ -120,7 +122,7 @@
interrupts = <32>;
};
gpio4: gpio@481ae000 {
gpio3: gpio@481ae000 {
compatible = "ti,omap4-gpio";
ti,hwmods = "gpio4";
gpio-controller;
@ -185,7 +187,7 @@
status = "disabled";
};
i2c1: i2c@44e0b000 {
i2c0: i2c@44e0b000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
@ -195,7 +197,7 @@
status = "disabled";
};
i2c2: i2c@4802a000 {
i2c1: i2c@4802a000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
@ -205,7 +207,7 @@
status = "disabled";
};
i2c3: i2c@4819c000 {
i2c2: i2c@4819c000 {
compatible = "ti,omap4-i2c";
#address-cells = <1>;
#size-cells = <0>;
@ -225,7 +227,8 @@
dcan0: d_can@481cc000 {
compatible = "bosch,d_can";
ti,hwmods = "d_can0";
reg = <0x481cc000 0x2000>;
reg = <0x481cc000 0x2000
0x44e10644 0x4>;
interrupts = <52>;
status = "disabled";
};
@ -233,13 +236,14 @@
dcan1: d_can@481d0000 {
compatible = "bosch,d_can";
ti,hwmods = "d_can1";
reg = <0x481d0000 0x2000>;
reg = <0x481d0000 0x2000
0x44e10644 0x4>;
interrupts = <55>;
status = "disabled";
};
timer1: timer@44e31000 {
compatible = "ti,omap2-timer";
compatible = "ti,am335x-timer-1ms";
reg = <0x44e31000 0x400>;
interrupts = <67>;
ti,hwmods = "timer1";
@ -247,21 +251,21 @@
};
timer2: timer@48040000 {
compatible = "ti,omap2-timer";
compatible = "ti,am335x-timer";
reg = <0x48040000 0x400>;
interrupts = <68>;
ti,hwmods = "timer2";
};
timer3: timer@48042000 {
compatible = "ti,omap2-timer";
compatible = "ti,am335x-timer";
reg = <0x48042000 0x400>;
interrupts = <69>;
ti,hwmods = "timer3";
};
timer4: timer@48044000 {
compatible = "ti,omap2-timer";
compatible = "ti,am335x-timer";
reg = <0x48044000 0x400>;
interrupts = <92>;
ti,hwmods = "timer4";
@ -269,7 +273,7 @@
};
timer5: timer@48046000 {
compatible = "ti,omap2-timer";
compatible = "ti,am335x-timer";
reg = <0x48046000 0x400>;
interrupts = <93>;
ti,hwmods = "timer5";
@ -277,7 +281,7 @@
};
timer6: timer@48048000 {
compatible = "ti,omap2-timer";
compatible = "ti,am335x-timer";
reg = <0x48048000 0x400>;
interrupts = <94>;
ti,hwmods = "timer6";
@ -285,7 +289,7 @@
};
timer7: timer@4804a000 {
compatible = "ti,omap2-timer";
compatible = "ti,am335x-timer";
reg = <0x4804a000 0x400>;
interrupts = <95>;
ti,hwmods = "timer7";
@ -305,7 +309,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x48030000 0x400>;
interrupt = <65>;
interrupts = <65>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi0";
status = "disabled";
@ -316,7 +320,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x481a0000 0x400>;
interrupt = <125>;
interrupts = <125>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi1";
status = "disabled";

2
arch/arm/boot/dts/am3517-evm.dts
View File

@ -7,7 +7,7 @@
*/
/dts-v1/;
/include/ "omap3.dtsi"
/include/ "omap34xx.dtsi"
/ {
model = "TI AM3517 EVM (AM3517/05)";

2
arch/arm/boot/dts/am3517_mt_ventoux.dts
View File

@ -7,7 +7,7 @@
*/
/dts-v1/;
/include/ "omap3.dtsi"
/include/ "omap34xx.dtsi"
/ {
model = "TeeJet Mt.Ventoux";

154
arch/arm/boot/dts/armada-370-db.dts
View File

@ -30,86 +30,88 @@
};
soc {
serial@d0012000 {
clock-frequency = <200000000>;
status = "okay";
};
sata@d00a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
ethernet@d0070000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@d0074000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
mvsdio@d00d4000 {
pinctrl-0 = <&sdio_pins1>;
pinctrl-names = "default";
/*
* This device is disabled by default, because
* using the SD card connector requires
* changing the default CON40 connector
* "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
* different connector
* "DB-88F6710_MPP_RGMII_SD_Jumper".
*/
status = "disabled";
/* No CD or WP GPIOs */
};
usb@d0050000 {
status = "okay";
};
usb@d0051000 {
status = "okay";
};
spi0: spi@d0010600 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mx25l25635e";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
};
};
pcie-controller {
status = "okay";
/*
* The two PCIe units are accessible through
* both standard PCIe slots and mini-PCIe
* slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
mvsdio@d4000 {
pinctrl-0 = <&sdio_pins1>;
pinctrl-names = "default";
/*
* This device is disabled by default, because
* using the SD card connector requires
* changing the default CON40 connector
* "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
* different connector
* "DB-88F6710_MPP_RGMII_SD_Jumper".
*/
status = "disabled";
/* No CD or WP GPIOs */
};
usb@50000 {
status = "okay";
};
usb@51000 {
status = "okay";
};
spi0: spi@10600 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mx25l25635e";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
};
};
pcie-controller {
status = "okay";
/*
* The two PCIe units are accessible through
* both standard PCIe slots and mini-PCIe
* slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
};
};
};

206
arch/arm/boot/dts/armada-370-mirabox.dts
View File

@ -25,113 +25,115 @@
};
soc {
serial@d0012000 {
clock-frequency = <200000000>;
status = "okay";
};
timer@d0020300 {
clock-frequency = <600000000>;
status = "okay";
};
pinctrl {
pwr_led_pin: pwr-led-pin {
marvell,pins = "mpp63";
marvell,function = "gpo";
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
stat_led_pins: stat-led-pins {
marvell,pins = "mpp64", "mpp65";
marvell,function = "gpio";
};
};
gpio_leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pwr_led_pin &stat_led_pins>;
green_pwr_led {
label = "mirabox:green:pwr";
gpios = <&gpio1 31 1>;
linux,default-trigger = "heartbeat";
};
blue_stat_led {
label = "mirabox:blue:stat";
gpios = <&gpio2 0 1>;
linux,default-trigger = "cpu0";
};
green_stat_led {
label = "mirabox:green:stat";
gpios = <&gpio2 1 1>;
default-state = "off";
};
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
ethernet@d0070000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@d0074000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
mvsdio@d00d4000 {
pinctrl-0 = <&sdio_pins3>;
pinctrl-names = "default";
status = "okay";
/*
* No CD or WP GPIOs: SDIO interface used for
* Wifi/Bluetooth chip
*/
};
usb@d0050000 {
status = "okay";
};
usb@d0051000 {
status = "okay";
};
i2c@d0011000 {
status = "okay";
clock-frequency = <100000>;
pca9505: pca9505@25 {
compatible = "nxp,pca9505";
gpio-controller;
#gpio-cells = <2>;
reg = <0x25>;
};
};
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
timer@20300 {
clock-frequency = <600000000>;
status = "okay";
};
/* Connected on the PCB to a USB 3.0 XHCI controller */
pcie@2,0 {
/* Port 1, Lane 0 */
pinctrl {
pwr_led_pin: pwr-led-pin {
marvell,pins = "mpp63";
marvell,function = "gpo";
};
stat_led_pins: stat-led-pins {
marvell,pins = "mpp64", "mpp65";
marvell,function = "gpio";
};
};
gpio_leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pwr_led_pin &stat_led_pins>;
green_pwr_led {
label = "mirabox:green:pwr";
gpios = <&gpio1 31 1>;
linux,default-trigger = "heartbeat";
};
blue_stat_led {
label = "mirabox:blue:stat";
gpios = <&gpio2 0 1>;
linux,default-trigger = "cpu0";
};
green_stat_led {
label = "mirabox:green:stat";
gpios = <&gpio2 1 1>;
default-state = "off";
};
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
mvsdio@d4000 {
pinctrl-0 = <&sdio_pins3>;
pinctrl-names = "default";
status = "okay";
/*
* No CD or WP GPIOs: SDIO interface used for
* Wifi/Bluetooth chip
*/
};
usb@50000 {
status = "okay";
};
usb@51000 {
status = "okay";
};
i2c@11000 {
status = "okay";
clock-frequency = <100000>;
pca9505: pca9505@25 {
compatible = "nxp,pca9505";
gpio-controller;
#gpio-cells = <2>;
reg = <0x25>;
};
};
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
/* Connected on the PCB to a USB 3.0 XHCI controller */
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
};
};
};

106
arch/arm/boot/dts/armada-370-rd.dts
View File

@ -28,60 +28,62 @@
};
soc {
serial@d0012000 {
clock-frequency = <200000000>;
status = "okay";
};
sata@d00a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
internal-regs {
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
phy1: ethernet-phy@1 {
reg = <1>;
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "sgmii";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
mvsdio@d4000 {
pinctrl-0 = <&sdio_pins1>;
pinctrl-names = "default";
status = "okay";
/* No CD or WP GPIOs */
};
usb@50000 {
status = "okay";
};
usb@51000 {
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
button@1 {
label = "Software Button";
linux,code = <116>;
gpios = <&gpio0 6 1>;
};
};
};
ethernet@d0070000 {
status = "okay";
phy = <&phy0>;
phy-mode = "sgmii";
};
ethernet@d0074000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
mvsdio@d00d4000 {
pinctrl-0 = <&sdio_pins1>;
pinctrl-names = "default";
status = "okay";
/* No CD or WP GPIOs */
};
usb@d0050000 {
status = "okay";
};
usb@d0051000 {
status = "okay";
};
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
button@1 {
label = "Software Button";
linux,code = <116>;
gpios = <&gpio0 6 1>;
};
};
};
};

310
arch/arm/boot/dts/armada-370-xp.dtsi
View File

@ -16,7 +16,7 @@
* 370 and Armada XP SoC.
*/
/include/ "skeleton.dtsi"
/include/ "skeleton64.dtsi"
/ {
model = "Marvell Armada 370 and XP SoC";
@ -28,199 +28,203 @@
};
};
mpic: interrupt-controller@d0020000 {
compatible = "marvell,mpic";
#interrupt-cells = <1>;
#size-cells = <1>;
interrupt-controller;
};
coherency-fabric@d0020200 {
compatible = "marvell,coherency-fabric";
reg = <0xd0020200 0xb0>,
<0xd0021810 0x1c>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&mpic>;
ranges;
ranges = <0 0 0xd0000000 0x100000>;
serial@d0012000 {
internal-regs {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
mpic: interrupt-controller@20000 {
compatible = "marvell,mpic";
#interrupt-cells = <1>;
#size-cells = <1>;
interrupt-controller;
};
coherency-fabric@20200 {
compatible = "marvell,coherency-fabric";
reg = <0x20200 0xb0>, <0x21810 0x1c>;
};
serial@12000 {
compatible = "snps,dw-apb-uart";
reg = <0xd0012000 0x100>;
reg = <0x12000 0x100>;
reg-shift = <2>;
interrupts = <41>;
reg-io-width = <1>;
status = "disabled";
};
serial@d0012100 {
};
serial@12100 {
compatible = "snps,dw-apb-uart";
reg = <0xd0012100 0x100>;
reg = <0x12100 0x100>;
reg-shift = <2>;
interrupts = <42>;
reg-io-width = <1>;
status = "disabled";
};
};
timer@d0020300 {
compatible = "marvell,armada-370-xp-timer";
reg = <0xd0020300 0x30>,
<0xd0021040 0x30>;
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
clocks = <&coreclk 2>;
};
timer@20300 {
compatible = "marvell,armada-370-xp-timer";
reg = <0x20300 0x30>, <0x21040 0x30>;
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
clocks = <&coreclk 2>;
};
sata@d00a0000 {
compatible = "marvell,orion-sata";
reg = <0xd00a0000 0x2400>;
interrupts = <55>;
clocks = <&gateclk 15>, <&gateclk 30>;
clock-names = "0", "1";
status = "disabled";
};
sata@a0000 {
compatible = "marvell,orion-sata";
reg = <0xa0000 0x2400>;
interrupts = <55>;
clocks = <&gateclk 15>, <&gateclk 30>;
clock-names = "0", "1";
status = "disabled";
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0xd0072004 0x4>;
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x72004 0x4>;
};
ethernet@d0070000 {
ethernet@70000 {
compatible = "marvell,armada-370-neta";
reg = <0xd0070000 0x2500>;
reg = <0x70000 0x2500>;
interrupts = <8>;
clocks = <&gateclk 4>;
status = "disabled";
};
};
ethernet@d0074000 {
ethernet@74000 {
compatible = "marvell,armada-370-neta";
reg = <0xd0074000 0x2500>;
reg = <0x74000 0x2500>;
interrupts = <10>;
clocks = <&gateclk 3>;
status = "disabled";
};
};
i2c0: i2c@d0011000 {
compatible = "marvell,mv64xxx-i2c";
reg = <0xd0011000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <31>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c0: i2c@11000 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <31>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c1: i2c@d0011100 {
compatible = "marvell,mv64xxx-i2c";
reg = <0xd0011100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <32>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
i2c1: i2c@11100 {
compatible = "marvell,mv64xxx-i2c";
reg = <0x11100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <32>;
timeout-ms = <1000>;
clocks = <&coreclk 0>;
status = "disabled";
};
rtc@10300 {
compatible = "marvell,orion-rtc";
reg = <0xd0010300 0x20>;
interrupts = <50>;
};
rtc@10300 {
compatible = "marvell,orion-rtc";
reg = <0x10300 0x20>;
interrupts = <50>;
};
mvsdio@d00d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd00d4000 0x200>;
interrupts = <54>;
clocks = <&gateclk 17>;
status = "disabled";
};
mvsdio@d4000 {
compatible = "marvell,orion-sdio";
reg = <0xd4000 0x200>;
interrupts = <54>;
clocks = <&gateclk 17>;
status = "disabled";
};
usb@d0050000 {
compatible = "marvell,orion-ehci";
reg = <0xd0050000 0x500>;
interrupts = <45>;
status = "disabled";
};
usb@50000 {
compatible = "marvell,orion-ehci";
reg = <0x50000 0x500>;
interrupts = <45>;
status = "disabled";
};
usb@d0051000 {
compatible = "marvell,orion-ehci";
reg = <0xd0051000 0x500>;
interrupts = <46>;
status = "disabled";
};
usb@51000 {
compatible = "marvell,orion-ehci";
reg = <0x51000 0x500>;
interrupts = <46>;
status = "disabled";
};
spi0: spi@d0010600 {
compatible = "marvell,orion-spi";
reg = <0xd0010600 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <30>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi0: spi@10600 {
compatible = "marvell,orion-spi";
reg = <0x10600 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
interrupts = <30>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@d0010680 {
compatible = "marvell,orion-spi";
reg = <0xd0010680 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
status = "disabled";
};
spi1: spi@10680 {
compatible = "marvell,orion-spi";
reg = <0x10680 0x28>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <1>;
interrupts = <92>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-bootcs@d0010400 {
compatible = "marvell,mvebu-devbus";
reg = <0xd0010400 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-bootcs@10400 {
compatible = "marvell,mvebu-devbus";
reg = <0x10400 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs0@d0010408 {
compatible = "marvell,mvebu-devbus";
reg = <0xd0010408 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs0@10408 {
compatible = "marvell,mvebu-devbus";
reg = <0x10408 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs1@d0010410 {
compatible = "marvell,mvebu-devbus";
reg = <0xd0010410 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs1@10410 {
compatible = "marvell,mvebu-devbus";
reg = <0x10410 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs2@d0010418 {
compatible = "marvell,mvebu-devbus";
reg = <0xd0010418 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs2@10418 {
compatible = "marvell,mvebu-devbus";
reg = <0x10418 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
devbus-cs3@d0010420 {
compatible = "marvell,mvebu-devbus";
reg = <0xd0010420 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
devbus-cs3@10420 {
compatible = "marvell,mvebu-devbus";
reg = <0x10420 0x8>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&coreclk 0>;
status = "disabled";
};
};
};
};
};

320
arch/arm/boot/dts/armada-370.dtsi
View File

@ -16,16 +16,11 @@
*/
/include/ "armada-370-xp.dtsi"
/include/ "skeleton.dtsi"
/ {
model = "Marvell Armada 370 family SoC";
compatible = "marvell,armada370", "marvell,armada-370-xp";
L2: l2-cache {
compatible = "marvell,aurora-outer-cache";
reg = <0xd0008000 0x1000>;
cache-id-part = <0x100>;
wt-override;
};
aliases {
gpio0 = &gpio0;
@ -33,188 +28,197 @@
gpio2 = &gpio2;
};
mpic: interrupt-controller@d0020000 {
reg = <0xd0020a00 0x1d0>,
<0xd0021870 0x58>;
};
soc {
system-controller@d0018200 {
ranges = <0 0xd0000000 0x100000>;
internal-regs {
system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0xd0018200 0x100>;
};
pinctrl {
compatible = "marvell,mv88f6710-pinctrl";
reg = <0xd0018000 0x38>;
sdio_pins1: sdio-pins1 {
marvell,pins = "mpp9", "mpp11", "mpp12",
"mpp13", "mpp14", "mpp15";
marvell,function = "sd0";
reg = <0x18200 0x100>;
};
sdio_pins2: sdio-pins2 {
marvell,pins = "mpp47", "mpp48", "mpp49",
"mpp50", "mpp51", "mpp52";
marvell,function = "sd0";
L2: l2-cache {
compatible = "marvell,aurora-outer-cache";
reg = <0xd0008000 0x1000>;
cache-id-part = <0x100>;
wt-override;
};
sdio_pins3: sdio-pins3 {
marvell,pins = "mpp48", "mpp49", "mpp50",
"mpp51", "mpp52", "mpp53";
marvell,function = "sd0";
mpic: interrupt-controller@20000 {
reg = <0x20a00 0x1d0>, <0x21870 0x58>;
};
};
gpio0: gpio@d0018100 {
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
pinctrl {
compatible = "marvell,mv88f6710-pinctrl";
reg = <0x18000 0x38>;
gpio1: gpio@d0018140 {
compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
};
sdio_pins1: sdio-pins1 {
marvell,pins = "mpp9", "mpp11", "mpp12",
"mpp13", "mpp14", "mpp15";
marvell,function = "sd0";
};
gpio2: gpio@d0018180 {
compatible = "marvell,orion-gpio";
reg = <0xd0018180 0x40>;
ngpios = <2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <91>;
};
sdio_pins2: sdio-pins2 {
marvell,pins = "mpp47", "mpp48", "mpp49",
"mpp50", "mpp51", "mpp52";
marvell,function = "sd0";
};
coreclk: mvebu-sar@d0018230 {
compatible = "marvell,armada-370-core-clock";
reg = <0xd0018230 0x08>;
#clock-cells = <1>;
};
gateclk: clock-gating-control@d0018220 {
compatible = "marvell,armada-370-gating-clock";
reg = <0xd0018220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
xor@d0060800 {
compatible = "marvell,orion-xor";
reg = <0xd0060800 0x100
0xd0060A00 0x100>;
status = "okay";
xor00 {
interrupts = <51>;
dmacap,memcpy;
dmacap,xor;
sdio_pins3: sdio-pins3 {
marvell,pins = "mpp48", "mpp49", "mpp50",
"mpp51", "mpp52", "mpp53";
marvell,function = "sd0";
};
};
xor01 {
interrupts = <52>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
};
xor@d0060900 {
compatible = "marvell,orion-xor";
reg = <0xd0060900 0x100
0xd0060b00 0x100>;
status = "okay";
xor10 {
interrupts = <94>;
dmacap,memcpy;
dmacap,xor;
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
};
xor11 {
interrupts = <95>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
gpio2: gpio@18180 {
compatible = "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <91>;
};
};
usb@d0050000 {
clocks = <&coreclk 0>;
};
coreclk: mvebu-sar@18230 {
compatible = "marvell,armada-370-core-clock";
reg = <0x18230 0x08>;
#clock-cells = <1>;
};
usb@d0051000 {
clocks = <&coreclk 0>;
};
gateclk: clock-gating-control@18220 {
compatible = "marvell,armada-370-gating-clock";
reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
thermal@d0018300 {
compatible = "marvell,armada370-thermal";
reg = <0xd0018300 0x4
0xd0018304 0x4>;
status = "okay";
};
xor@60800 {
compatible = "marvell,orion-xor";
reg = <0x60800 0x100
0x60A00 0x100>;
status = "okay";
pcie-controller {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
xor00 {
interrupts = <51>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <52>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
#address-cells = <3>;
#size-cells = <2>;
xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
status = "okay";
bus-range = <0x00 0xff>;
xor10 {
interrupts = <94>;
dmacap,memcpy;
dmacap,xor;
};
xor11 {
interrupts = <95>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>;
usb@50000 {
clocks = <&coreclk 0>;
};
reg-names = "pcie0.0", "pcie1.0";
usb@51000 {
clocks = <&coreclk 0>;
};
ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
thermal@18300 {
compatible = "marvell,armada370-thermal";
reg = <0x18300 0x4
0x18304 0x4>;
status = "okay";
};
pcie@1,0 {
pcie-controller {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
bus-range = <0x00 0xff>;
reg = <0x40000 0x2000>, <0x80000 0x2000>;
reg-names = "pcie0.0", "pcie1.0";
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
};
};
};
};

226
arch/arm/boot/dts/armada-xp-db.dts
View File

@ -26,132 +26,134 @@
memory {
device_type = "memory";
reg = <0x00000000 0x80000000>; /* 2 GB */
reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
};
soc {
serial@d0012000 {
clock-frequency = <250000000>;
status = "okay";
};
serial@d0012100 {
clock-frequency = <250000000>;
status = "okay";
};
serial@d0012200 {
clock-frequency = <250000000>;
status = "okay";
};
serial@d0012300 {
clock-frequency = <250000000>;
status = "okay";
};
sata@d00a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <25>;
};
phy3: ethernet-phy@3 {
reg = <27>;
};
};
ethernet@d0070000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@d0074000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
ethernet@d0030000 {
status = "okay";
phy = <&phy2>;
phy-mode = "sgmii";
};
ethernet@d0034000 {
status = "okay";
phy = <&phy3>;
phy-mode = "sgmii";
};
mvsdio@d00d4000 {
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
status = "okay";
/* No CD or WP GPIOs */
};
usb@d0050000 {
status = "okay";
};
usb@d0051000 {
status = "okay";
};
usb@d0052000 {
status = "okay";
};
spi0: spi@d0010600 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;
};
};
pcie-controller {
status = "okay";
/*
* All 6 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
internal-regs {
serial@12000 {
clock-frequency = <250000000>;
status = "okay";
};
pcie@2,0 {
/* Port 0, Lane 1 */
serial@12100 {
clock-frequency = <250000000>;
status = "okay";
};
pcie@3,0 {
/* Port 0, Lane 2 */
serial@12200 {
clock-frequency = <250000000>;
status = "okay";
};
pcie@4,0 {
/* Port 0, Lane 3 */
serial@12300 {
clock-frequency = <250000000>;
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <25>;
};
phy3: ethernet-phy@3 {
reg = <27>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
ethernet@30000 {
status = "okay";
phy = <&phy2>;
phy-mode = "sgmii";
};
ethernet@34000 {
status = "okay";
phy = <&phy3>;
phy-mode = "sgmii";
};
mvsdio@d4000 {
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
status = "okay";
/* No CD or WP GPIOs */
};
usb@50000 {
status = "okay";
};
usb@51000 {
status = "okay";
};
usb@52000 {
status = "okay";
};
spi0: spi@10600 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <20000000>;
};
};
pcie-controller {
status = "okay";
/*
* All 6 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 0, Lane 1 */
status = "okay";
};
pcie@3,0 {
/* Port 0, Lane 2 */
status = "okay";
};
pcie@4,0 {
/* Port 0, Lane 3 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
};
};

246
arch/arm/boot/dts/armada-xp-gp.dts
View File

@ -26,138 +26,142 @@
memory {
device_type = "memory";
/*
* 4 GB of plug-in RAM modules by default but only 3GB
* are visible, the amount of memory available can be
* changed by the bootloader according the size of the
* module actually plugged
* 8 GB of plug-in RAM modules by default.The amount
* of memory available can be changed by the
* bootloader according the size of the module
* actually plugged. Only 7GB are usable because
* addresses from 0xC0000000 to 0xffffffff are used by
* the internal registers of the SoC.
*/
reg = <0x00000000 0xC0000000>;
reg = <0x00000000 0x00000000 0x00000000 0xC0000000>,
<0x00000001 0x00000000 0x00000001 0x00000000>;
};
soc {
serial@d0012000 {
clock-frequency = <250000000>;
status = "okay";
};
serial@d0012100 {
clock-frequency = <250000000>;
status = "okay";
};
serial@d0012200 {
clock-frequency = <250000000>;
status = "okay";
};
serial@d0012300 {
clock-frequency = <250000000>;
status = "okay";
};
sata@d00a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <16>;
};
phy1: ethernet-phy@1 {
reg = <17>;
};
phy2: ethernet-phy@2 {
reg = <18>;
};
phy3: ethernet-phy@3 {
reg = <19>;
};
};
ethernet@d0070000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@d0074000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
ethernet@d0030000 {
status = "okay";
phy = <&phy2>;
phy-mode = "rgmii-id";
};
ethernet@d0034000 {
status = "okay";
phy = <&phy3>;
phy-mode = "rgmii-id";
};
spi0: spi@d0010600 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
devbus-bootcs@d0010400 {
status = "okay";
ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 16 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x1000000>;
bank-width = <2>;
};
};
pcie-controller {
status = "okay";
/*
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
internal-regs {
serial@12000 {
clock-frequency = <250000000>;
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
serial@12100 {
clock-frequency = <250000000>;
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
serial@12200 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12300 {
clock-frequency = <250000000>;
status = "okay";
};
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
mdio {
phy0: ethernet-phy@0 {
reg = <16>;
};
phy1: ethernet-phy@1 {
reg = <17>;
};
phy2: ethernet-phy@2 {
reg = <18>;
};
phy3: ethernet-phy@3 {
reg = <19>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
ethernet@30000 {
status = "okay";
phy = <&phy2>;
phy-mode = "rgmii-id";
};
ethernet@34000 {
status = "okay";
phy = <&phy3>;
phy-mode = "rgmii-id";
};
spi0: spi@10600 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q128a13";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
devbus-bootcs@10400 {
status = "okay";
ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 16 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x1000000>;
bank-width = <2>;
};
};
pcie-controller {
status = "okay";
/*
* The 3 slots are physically present as
* standard PCIe slots on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@9,0 {
/* Port 2, Lane 0 */
status = "okay";
};
pcie@10,0 {
/* Port 3, Lane 0 */
status = "okay";
};
};
};
};
};

280
arch/arm/boot/dts/armada-xp-mv78230.dtsi
View File

@ -25,159 +25,161 @@
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <0>;
clocks = <&cpuclk 0>;
};
cpu@0 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <0>;
clocks = <&cpuclk 0>;
};
cpu@1 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <1>;
clocks = <&cpuclk 1>;
};
cpu@1 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <1>;
clocks = <&cpuclk 1>;
};
};
soc {
pinctrl {
compatible = "marvell,mv78230-pinctrl";
reg = <0xd0018000 0x38>;
internal-regs {
pinctrl {
compatible = "marvell,mv78230-pinctrl";
reg = <0x18000 0x38>;
sdio_pins: sdio-pins {
marvell,pins = "mpp30", "mpp31", "mpp32",
"mpp33", "mpp34", "mpp35";
marvell,function = "sd0";
};
};
gpio0: gpio@d0018100 {
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>;
ngpios = <17>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>;
};
/*
* MV78230 has 2 PCIe units Gen2.0: One unit can be
* configured as x4 or quad x1 lanes. One unit is
* x4/x1.
*/
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
sdio_pins: sdio-pins {
marvell,pins = "mpp30", "mpp31", "mpp32",
"mpp33", "mpp34", "mpp35";
marvell,function = "sd0";
};
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
ngpios = <17>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>;
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
/*
* MV78230 has 2 PCIe units Gen2.0: One unit can be
* configured as x4 or quad x1 lanes. One unit is
* x4/x1.
*/
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
};
device_type = "pci";
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
};
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
};
};
};
};

334
arch/arm/boot/dts/armada-xp-mv78260.dtsi
View File

@ -26,196 +26,198 @@
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <0>;
clocks = <&cpuclk 0>;
};
cpu@0 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <0>;
clocks = <&cpuclk 0>;
};
cpu@1 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <1>;
clocks = <&cpuclk 1>;
};
cpu@1 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <1>;
clocks = <&cpuclk 1>;
};
};
soc {
pinctrl {
compatible = "marvell,mv78260-pinctrl";
reg = <0xd0018000 0x38>;
internal-regs {
pinctrl {
compatible = "marvell,mv78260-pinctrl";
reg = <0x18000 0x38>;
sdio_pins: sdio-pins {
marvell,pins = "mpp30", "mpp31", "mpp32",
"mpp33", "mpp34", "mpp35";
marvell,function = "sd0";
sdio_pins: sdio-pins {
marvell,pins = "mpp30", "mpp31", "mpp32",
"mpp33", "mpp34", "mpp35";
marvell,function = "sd0";
};
};
};
gpio0: gpio@d0018100 {
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
};
gpio2: gpio@d0018180 {
compatible = "marvell,orion-gpio";
reg = <0xd0018180 0x40>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <91>;
};
gpio2: gpio@18180 {
compatible = "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <91>;
};
ethernet@d0034000 {
ethernet@34000 {
compatible = "marvell,armada-370-neta";
reg = <0xd0034000 0x2500>;
reg = <0x34000 0x2500>;
interrupts = <14>;
clocks = <&gateclk 1>;
status = "disabled";
};
/*
* MV78260 has 3 PCIe units Gen2.0: Two units can be
* configured as x4 or quad x1 lanes. One unit is
* x4/x1.
*/
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0044000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
/*
* MV78260 has 3 PCIe units Gen2.0: Two units can be
* configured as x4 or quad x1 lanes. One unit is
* x4/x1.
*/
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
};
device_type = "pci";
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0048000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd004c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
bus-range = <0x00 0xff>;
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0042000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
};
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@10,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0082000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
status = "disabled";
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
};
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
};
pcie@10,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
status = "disabled";
};
};
};
};

486
arch/arm/boot/dts/armada-xp-mv78460.dtsi
View File

@ -27,277 +27,279 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <0>;
clocks = <&cpuclk 0>;
};
cpu@0 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <0>;
clocks = <&cpuclk 0>;
};
cpu@1 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <1>;
clocks = <&cpuclk 1>;
};
cpu@1 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <1>;
clocks = <&cpuclk 1>;
};
cpu@2 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <2>;
clocks = <&cpuclk 2>;
};
cpu@2 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <2>;
clocks = <&cpuclk 2>;
};
cpu@3 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <3>;
clocks = <&cpuclk 3>;
};
cpu@3 {
device_type = "cpu";
compatible = "marvell,sheeva-v7";
reg = <3>;
clocks = <&cpuclk 3>;
};
};
soc {
pinctrl {
compatible = "marvell,mv78460-pinctrl";
reg = <0xd0018000 0x38>;
internal-regs {
pinctrl {
compatible = "marvell,mv78460-pinctrl";
reg = <0x18000 0x38>;
sdio_pins: sdio-pins {
marvell,pins = "mpp30", "mpp31", "mpp32",
"mpp33", "mpp34", "mpp35";
marvell,function = "sd0";
sdio_pins: sdio-pins {
marvell,pins = "mpp30", "mpp31", "mpp32",
"mpp33", "mpp34", "mpp35";
marvell,function = "sd0";
};
};
};
gpio0: gpio@d0018100 {
compatible = "marvell,orion-gpio";
reg = <0xd0018100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio0: gpio@18100 {
compatible = "marvell,orion-gpio";
reg = <0x18100 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <82>, <83>, <84>, <85>;
};
gpio1: gpio@d0018140 {
compatible = "marvell,orion-gpio";
reg = <0xd0018140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
};
gpio1: gpio@18140 {
compatible = "marvell,orion-gpio";
reg = <0x18140 0x40>;
ngpios = <32>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <87>, <88>, <89>, <90>;
};
gpio2: gpio@d0018180 {
compatible = "marvell,orion-gpio";
reg = <0xd0018180 0x40>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <91>;
};
gpio2: gpio@18180 {
compatible = "marvell,orion-gpio";
reg = <0x18180 0x40>;
ngpios = <3>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupts-cells = <2>;
interrupts = <91>;
};
ethernet@d0034000 {
ethernet@34000 {
compatible = "marvell,armada-370-neta";
reg = <0xd0034000 0x2500>;
reg = <0x34000 0x2500>;
interrupts = <14>;
clocks = <&gateclk 1>;
status = "disabled";
};
/*
* MV78460 has 4 PCIe units Gen2.0: Two units can be
* configured as x4 or quad x1 lanes. Two units are
* x4/x1.
*/
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0xd0042000 0xd0042000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0xd0044000 0xd0044000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0xd0048000 0xd0048000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0xd004c000 0xd004c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0xd0080000 0xd0080000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0xd0082000 0xd0082000 0 0x00002000 /* Port 3.0 registers */
0x82000000 0 0xd0084000 0xd0084000 0 0x00002000 /* Port 1.1 registers */
0x82000000 0 0xd0088000 0xd0088000 0 0x00002000 /* Port 1.2 registers */
0x82000000 0 0xd008c000 0xd008c000 0 0x00002000 /* Port 1.3 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
/*
* MV78460 has 4 PCIe units Gen2.0: Two units can be
* configured as x4 or quad x1 lanes. Two units are
* x4/x1.
*/
pcie-controller {
compatible = "marvell,armada-xp-pcie";
status = "disabled";
};
device_type = "pci";
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
};
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
bus-range = <0x00 0xff>;
pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
};
ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
pcie@6,0 {
device_type = "pci";
assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
reg = <0x3000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 63>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 10>;
status = "disabled";
};
pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
};
pcie@7,0 {
device_type = "pci";
assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
reg = <0x3800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 64>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 11>;
status = "disabled";
};
pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
};
pcie@8,0 {
device_type = "pci";
assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
reg = <0x4000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 65>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 12>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
};
pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
};
pcie@10,0 {
device_type = "pci";
assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
status = "disabled";
pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
};
pcie@5,0 {
device_type = "pci";
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
reg = <0x2800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
};
pcie@6,0 {
device_type = "pci";
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
reg = <0x3000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 63>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 10>;
status = "disabled";
};
pcie@7,0 {
device_type = "pci";
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
reg = <0x3800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 64>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 11>;
status = "disabled";
};
pcie@8,0 {
device_type = "pci";
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
reg = <0x4000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 65>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 12>;
status = "disabled";
};
pcie@9,0 {
device_type = "pci";
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
};
pcie@10,0 {
device_type = "pci";
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
reg = <0x5000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
status = "disabled";
};
};
};
};
};
};

298
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
View File

@ -23,159 +23,161 @@
memory {
device_type = "memory";
reg = <0x00000000 0xC0000000>; /* 3 GB */
reg = <0 0x00000000 0 0xC0000000>; /* 3 GB */
};
soc {
serial@d0012000 {
clock-frequency = <250000000>;
status = "okay";
};
serial@d0012100 {
clock-frequency = <250000000>;
status = "okay";
};
pinctrl {
led_pins: led-pins-0 {
marvell,pins = "mpp49", "mpp51", "mpp53";
marvell,function = "gpio";
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
red_led {
label = "red_led";
gpios = <&gpio1 17 1>;
default-state = "off";
};
yellow_led {
label = "yellow_led";
gpios = <&gpio1 19 1>;
default-state = "off";
};
green_led {
label = "green_led";
gpios = <&gpio1 21 1>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
button@1 {
label = "Init Button";
linux,code = <116>;
gpios = <&gpio1 28 0>;
};
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
phy3: ethernet-phy@3 {
reg = <3>;
};
};
ethernet@d0070000 {
status = "okay";
phy = <&phy0>;
phy-mode = "sgmii";
};
ethernet@d0074000 {
status = "okay";
phy = <&phy1>;
phy-mode = "sgmii";
};
ethernet@d0030000 {
status = "okay";
phy = <&phy2>;
phy-mode = "sgmii";
};
ethernet@d0034000 {
status = "okay";
phy = <&phy3>;
phy-mode = "sgmii";
};
i2c@d0011000 {
status = "okay";
clock-frequency = <400000>;
};
i2c@d0011100 {
status = "okay";
clock-frequency = <400000>;
s35390a: s35390a@30 {
compatible = "s35390a";
reg = <0x30>;
};
};
sata@d00a0000 {
nr-ports = <2>;
status = "okay";
};
usb@d0050000 {
status = "okay";
};
usb@d0051000 {
status = "okay";
};
devbus-bootcs@d0010400 {
status = "okay";
ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 128 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x8000000>;
bank-width = <2>;
};
};
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
internal-regs {
serial@12000 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12100 {
clock-frequency = <250000000>;
status = "okay";
};
pinctrl {
led_pins: led-pins-0 {
marvell,pins = "mpp49", "mpp51", "mpp53";
marvell,function = "gpio";
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
red_led {
label = "red_led";
gpios = <&gpio1 17 1>;
default-state = "off";
};
yellow_led {
label = "yellow_led";
gpios = <&gpio1 19 1>;
default-state = "off";
};
green_led {
label = "green_led";
gpios = <&gpio1 21 1>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
button@1 {
label = "Init Button";
linux,code = <116>;
gpios = <&gpio1 28 0>;
};
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
phy3: ethernet-phy@3 {
reg = <3>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "sgmii";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "sgmii";
};
ethernet@30000 {
status = "okay";
phy = <&phy2>;
phy-mode = "sgmii";
};
ethernet@34000 {
status = "okay";
phy = <&phy3>;
phy-mode = "sgmii";
};
i2c@11000 {
status = "okay";
clock-frequency = <400000>;
};
i2c@11100 {
status = "okay";
clock-frequency = <400000>;
s35390a: s35390a@30 {
compatible = "s35390a";
reg = <0x30>;
};
};
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
usb@50000 {
status = "okay";
};
usb@51000 {
status = "okay";
};
devbus-bootcs@10400 {
status = "okay";
ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 128 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x8000000>;
bank-width = <2>;
};
};
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
};
};
};

204
arch/arm/boot/dts/armada-xp.dtsi
View File

@ -22,140 +22,140 @@
model = "Marvell Armada XP family SoC";
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
L2: l2-cache {
compatible = "marvell,aurora-system-cache";
reg = <0xd0008000 0x1000>;
cache-id-part = <0x100>;
wt-override;
};
mpic: interrupt-controller@d0020000 {
reg = <0xd0020a00 0x2d0>,
<0xd0021070 0x58>;
};
armada-370-xp-pmsu@d0022000 {
compatible = "marvell,armada-370-xp-pmsu";
reg = <0xd0022100 0x430>,
<0xd0020800 0x20>;
};
soc {
serial@d0012200 {
internal-regs {
L2: l2-cache {
compatible = "marvell,aurora-system-cache";
reg = <0x08000 0x1000>;
cache-id-part = <0x100>;
wt-override;
};
mpic: interrupt-controller@20000 {
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
};
armada-370-xp-pmsu@22000 {
compatible = "marvell,armada-370-xp-pmsu";
reg = <0x22100 0x430>, <0x20800 0x20>;
};
serial@12200 {
compatible = "snps,dw-apb-uart";
reg = <0xd0012200 0x100>;
reg = <0x12200 0x100>;
reg-shift = <2>;
interrupts = <43>;
reg-io-width = <1>;
status = "disabled";
};
serial@d0012300 {
};
serial@12300 {
compatible = "snps,dw-apb-uart";
reg = <0xd0012300 0x100>;
reg = <0x12300 0x100>;
reg-shift = <2>;
interrupts = <44>;
reg-io-width = <1>;
status = "disabled";
};
};
timer@d0020300 {
timer@20300 {
marvell,timer-25Mhz;
};
};
coreclk: mvebu-sar@d0018230 {
compatible = "marvell,armada-xp-core-clock";
reg = <0xd0018230 0x08>;
#clock-cells = <1>;
};
coreclk: mvebu-sar@18230 {
compatible = "marvell,armada-xp-core-clock";
reg = <0x18230 0x08>;
#clock-cells = <1>;
};
cpuclk: clock-complex@d0018700 {
#clock-cells = <1>;
compatible = "marvell,armada-xp-cpu-clock";
reg = <0xd0018700 0xA0>;
clocks = <&coreclk 1>;
};
cpuclk: clock-complex@18700 {
#clock-cells = <1>;
compatible = "marvell,armada-xp-cpu-clock";
reg = <0x18700 0xA0>;
clocks = <&coreclk 1>;
};
gateclk: clock-gating-control@d0018220 {
compatible = "marvell,armada-xp-gating-clock";
reg = <0xd0018220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
gateclk: clock-gating-control@18220 {
compatible = "marvell,armada-xp-gating-clock";
reg = <0x18220 0x4>;
clocks = <&coreclk 0>;
#clock-cells = <1>;
};
system-controller@d0018200 {
system-controller@18200 {
compatible = "marvell,armada-370-xp-system-controller";
reg = <0xd0018200 0x500>;
};
reg = <0x18200 0x500>;
};
ethernet@d0030000 {
ethernet@30000 {
compatible = "marvell,armada-370-neta";
reg = <0xd0030000 0x2500>;
reg = <0x30000 0x2500>;
interrupts = <12>;
clocks = <&gateclk 2>;
status = "disabled";
};
xor@d0060900 {
compatible = "marvell,orion-xor";
reg = <0xd0060900 0x100
0xd0060b00 0x100>;
clocks = <&gateclk 22>;
status = "okay";
xor10 {
interrupts = <51>;
dmacap,memcpy;
dmacap,xor;
};
xor11 {
interrupts = <52>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
xor@60900 {
compatible = "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 22>;
status = "okay";
xor10 {
interrupts = <51>;
dmacap,memcpy;
dmacap,xor;
};
xor11 {
interrupts = <52>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
};
xor@d00f0900 {
compatible = "marvell,orion-xor";
reg = <0xd00F0900 0x100
0xd00F0B00 0x100>;
clocks = <&gateclk 28>;
status = "okay";
xor@f0900 {
compatible = "marvell,orion-xor";
reg = <0xF0900 0x100
0xF0B00 0x100>;
clocks = <&gateclk 28>;
status = "okay";
xor00 {
interrupts = <94>;
dmacap,memcpy;
dmacap,xor;
xor00 {
interrupts = <94>;
dmacap,memcpy;
dmacap,xor;
};
xor01 {
interrupts = <95>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
};
};
xor01 {
interrupts = <95>;
dmacap,memcpy;
dmacap,xor;
dmacap,memset;
usb@50000 {
clocks = <&gateclk 18>;
};
};
usb@d0050000 {
clocks = <&gateclk 18>;
};
usb@51000 {
clocks = <&gateclk 19>;
};
usb@d0051000 {
clocks = <&gateclk 19>;
};
usb@52000 {
compatible = "marvell,orion-ehci";
reg = <0x52000 0x500>;
interrupts = <47>;
clocks = <&gateclk 20>;
status = "disabled";
};
usb@d0052000 {
compatible = "marvell,orion-ehci";
reg = <0xd0052000 0x500>;
interrupts = <47>;
clocks = <&gateclk 20>;
status = "disabled";
};
thermal@d00182b0 {
compatible = "marvell,armadaxp-thermal";
reg = <0xd00182b0 0x4
0xd00184d0 0x4>;
status = "okay";
thermal@182b0 {
compatible = "marvell,armadaxp-thermal";
reg = <0x182b0 0x4
0x184d0 0x4>;
status = "okay";
};
};
};
};

54
arch/arm/boot/dts/cros5250-common.dtsi
View File

@ -19,11 +19,19 @@
chosen {
};
pinctrl@11400000 {
/*
* Disabled pullups since external part has its own pullups and
* double-pulling gets us out of spec in some cases.
*/
i2c2_bus: i2c2-bus {
samsung,pin-pud = <0>;
};
};
i2c@12C60000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <378000>;
gpios = <&gpb3 0 2 3 0>,
<&gpb3 1 2 3 0>;
max77686@09 {
compatible = "maxim,max77686";
@ -167,21 +175,12 @@
i2c@12C70000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <378000>;
gpios = <&gpb3 2 2 3 0>,
<&gpb3 3 2 3 0>;
};
i2c@12C80000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
/*
* Disabled pullups since external part has its own pullups and
* double-pulling gets us out of spec in some cases.
*/
gpios = <&gpa0 6 3 0 0>,
<&gpa0 7 3 0 0>;
hdmiddc@50 {
compatible = "samsung,exynos5-hdmiddc";
reg = <0x50>;
@ -191,19 +190,16 @@
i2c@12C90000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
gpios = <&gpa1 2 3 3 0>,
<&gpa1 3 3 3 0>;
};
i2c@12CA0000 {
status = "disabled";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
};
i2c@12CB0000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
gpios = <&gpa2 2 3 3 0>,
<&gpa2 3 3 3 0>;
};
i2c@12CC0000 {
@ -213,8 +209,6 @@
i2c@12CD0000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
gpios = <&gpb2 2 3 3 0>,
<&gpb2 3 3 3 0>;
};
i2c@12CE0000 {
@ -236,15 +230,12 @@
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>;
slot@0 {
reg = <0>;
bus-width = <8>;
gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
<&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
<&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
<&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
<&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
};
};
@ -260,15 +251,13 @@
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
slot@0 {
reg = <0>;
bus-width = <4>;
samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
wp-gpios = <&gpc2 1 0 0 3>;
gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
<&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
<&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
wp-gpios = <&gpc2 1 0>;
};
};
@ -281,11 +270,11 @@
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
/* See board-specific dts files for pin setup */
slot@0 {
reg = <0>;
bus-width = <4>;
/* See board-specific dts files for GPIOs */
};
};
@ -294,9 +283,6 @@
};
spi_1: spi@12d30000 {
gpios = <&gpa2 4 2 3 0>,
<&gpa2 6 2 3 0>,
<&gpa2 7 2 3 0>;
samsung,spi-src-clk = <0>;
num-cs = <1>;
};
@ -306,7 +292,7 @@
};
hdmi {
hpd-gpio = <&gpx3 7 0xf 1 3>;
hpd-gpio = <&gpx3 7 0>;
};
gpio-keys {
@ -314,7 +300,7 @@
power {
label = "Power";
gpios = <&gpx1 3 0 0x10000 0>;
gpios = <&gpx1 3 1>;
linux,code = <116>; /* KEY_POWER */
gpio-key,wakeup;
};

40
arch/arm/boot/dts/da850-evm.dts
View File

@ -50,6 +50,46 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
};
spi1: spi@1f0e000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins &spi1_cs0_pin>;
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "m25p64";
spi-max-frequency = <30000000>;
reg = <0>;
partition@0 {
label = "U-Boot-SPL";
reg = <0x00000000 0x00010000>;
read-only;
};
partition@1 {
label = "U-Boot";
reg = <0x00010000 0x00080000>;
read-only;
};
partition@2 {
label = "U-Boot-Env";
reg = <0x00090000 0x00010000>;
read-only;
};
partition@3 {
label = "Kernel";
reg = <0x000a0000 0x00280000>;
};
partition@4 {
label = "Filesystem";
reg = <0x00320000 0x00400000>;
};
partition@5 {
label = "MAC-Address";
reg = <0x007f0000 0x00010000>;
read-only;
};
};
};
};
nand_cs3@62000000 {
status = "okay";

94
arch/arm/boot/dts/da850.dtsi
View File

@ -71,6 +71,60 @@
0x28 0x00222222 0x00ffffff
>;
};
ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
pinctrl-single,bits = <
/* EPWM0A */
0xc 0x00000002 0x0000000f
>;
};
ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
pinctrl-single,bits = <
/* EPWM0B */
0xc 0x00000020 0x000000f0
>;
};
ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
pinctrl-single,bits = <
/* EPWM1A */
0x14 0x00000002 0x0000000f
>;
};
ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
pinctrl-single,bits = <
/* EPWM1B */
0x14 0x00000020 0x000000f0
>;
};
ecap0_pins: pinmux_ecap0_pins {
pinctrl-single,bits = <
/* ECAP0_APWM0 */
0x8 0x20000000 0xf0000000
>;
};
ecap1_pins: pinmux_ecap1_pins {
pinctrl-single,bits = <
/* ECAP1_APWM1 */
0x4 0x40000000 0xf0000000
>;
};
ecap2_pins: pinmux_ecap2_pins {
pinctrl-single,bits = <
/* ECAP2_APWM2 */
0x4 0x00000004 0x0000000f
>;
};
spi1_pins: pinmux_spi_pins {
pinctrl-single,bits = <
/* SIMO, SOMI, CLK */
0x14 0x00110100 0x00ff0f00
>;
};
spi1_cs0_pin: pinmux_spi1_cs0 {
pinctrl-single,bits = <
/* CS0 */
0x14 0x00000010 0x000000f0
>;
};
};
serial0: serial@1c42000 {
compatible = "ns16550a";
@ -122,6 +176,46 @@
interrupts = <16>;
status = "disabled";
};
ehrpwm0: ehrpwm@01f00000 {
compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x300000 0x2000>;
status = "disabled";
};
ehrpwm1: ehrpwm@01f02000 {
compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x302000 0x2000>;
status = "disabled";
};
ecap0: ecap@01f06000 {
compatible = "ti,da850-ecap", "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x306000 0x80>;
status = "disabled";
};
ecap1: ecap@01f07000 {
compatible = "ti,da850-ecap", "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x307000 0x80>;
status = "disabled";
};
ecap2: ecap@01f08000 {
compatible = "ti,da850-ecap", "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x308000 0x80>;
status = "disabled";
};
spi1: spi@1f0e000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,da830-spi";
reg = <0x30e000 0x1000>;
num-cs = <4>;
ti,davinci-spi-intr-line = <1>;
interrupts = <56>;
status = "disabled";
};
};
nand_cs3@62000000 {
compatible = "ti,davinci-nand";

32
arch/arm/boot/dts/exynos4.dtsi
View File

@ -38,6 +38,11 @@
i2c7 = &i2c_7;
};
chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};
pd_mfc: mfc-power-domain@10023C40 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C40 0x20>;
@ -82,6 +87,11 @@
reg = <0x10440000 0x1000>;
};
sys_reg: sysreg {
compatible = "samsung,exynos4-sysreg", "syscon";
reg = <0x10010000 0x400>;
};
watchdog@10060000 {
compatible = "samsung,s3c2410-wdt";
reg = <0x10060000 0x100>;
@ -197,6 +207,8 @@
interrupts = <0 58 0>;
clocks = <&clock 317>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_bus>;
status = "disabled";
};
@ -208,6 +220,8 @@
interrupts = <0 59 0>;
clocks = <&clock 318>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_bus>;
status = "disabled";
};
@ -287,6 +301,8 @@
#size-cells = <0>;
clocks = <&clock 327>, <&clock 159>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>;
status = "disabled";
};
@ -300,6 +316,8 @@
#size-cells = <0>;
clocks = <&clock 328>, <&clock 160>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
status = "disabled";
};
@ -313,6 +331,8 @@
#size-cells = <0>;
clocks = <&clock 329>, <&clock 161>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi2_bus>;
status = "disabled";
};
@ -356,4 +376,16 @@
#dma-requests = <1>;
};
};
fimd: fimd@11c00000 {
compatible = "samsung,exynos4210-fimd";
interrupt-parent = <&combiner>;
reg = <0x11c00000 0x20000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <11 0>, <11 1>, <11 2>;
clocks = <&clock 140>, <&clock 283>;
clock-names = "sclk_fimd", "fimd";
samsung,power-domain = <&pd_lcd0>;
status = "disabled";
};
};

4
arch/arm/boot/dts/exynos4210-origen.dts
View File

@ -57,6 +57,10 @@
status = "okay";
};
g2d@12800000 {
status = "okay";
};
codec@13400000 {
samsung,mfc-r = <0x43000000 0x800000>;
samsung,mfc-l = <0x51000000 0x800000>;

57
arch/arm/boot/dts/exynos4210-smdkv310.dts
View File

@ -30,16 +30,13 @@
};
sdhci@12530000 {
samsung,sdhci-bus-width = <4>;
linux,mmc_cap_4_bit_data;
samsung,sdhci-cd-internal;
gpio-cd = <&gpk2 2 2 3 3>;
gpios = <&gpk2 0 2 0 3>,
<&gpk2 1 2 0 3>,
<&gpk2 3 2 3 3>,
<&gpk2 4 2 3 3>,
<&gpk2 5 2 3 3>,
<&gpk2 6 2 3 3>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
status = "okay";
};
g2d@12800000 {
status = "okay";
};
@ -65,25 +62,32 @@
status = "okay";
};
pinctrl@11000000 {
keypad_rows: keypad-rows {
samsung,pins = "gpx2-0", "gpx2-1";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
keypad_cols: keypad-cols {
samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3",
"gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
};
keypad@100A0000 {
samsung,keypad-num-rows = <2>;
samsung,keypad-num-columns = <8>;
linux,keypad-no-autorepeat;
linux,keypad-wakeup;
pinctrl-names = "default";
pinctrl-0 = <&keypad_rows &keypad_cols>;
status = "okay";
row-gpios = <&gpx2 0 3 3 0>,
<&gpx2 1 3 3 0>;
col-gpios = <&gpx1 0 3 0 0>,
<&gpx1 1 3 0 0>,
<&gpx1 2 3 0 0>,
<&gpx1 3 3 0 0>,
<&gpx1 4 3 0 0>,
<&gpx1 5 3 0 0>,
<&gpx1 6 3 0 0>,
<&gpx1 7 3 0 0>;
key_1 {
keypad,row = <0>;
keypad,column = <3>;
@ -149,9 +153,7 @@
#address-cells = <1>;
#size-cells = <0>;
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <20000>;
gpios = <&gpd1 0 2 3 0>,
<&gpd1 1 2 3 0>;
samsung,i2c-max-bus-freq = <100000>;
status = "okay";
eeprom@50 {
@ -166,9 +168,6 @@
};
spi_2: spi@13940000 {
gpios = <&gpc1 1 5 3 0>,
<&gpc1 3 5 3 0>,
<&gpc1 4 5 3 0>;
status = "okay";
w25x80@0 {
@ -179,7 +178,7 @@
spi-max-frequency = <1000000>;
controller-data {
cs-gpio = <&gpc1 2 1 0 3>;
cs-gpio = <&gpc1 2 0>;
samsung,spi-feedback-delay = <0>;
};

7
arch/arm/boot/dts/exynos4210.dtsi
View File

@ -112,4 +112,11 @@
reg = <0x100C0000 0x100>;
interrupts = <2 4>;
};
g2d@12800000 {
compatible = "samsung,s5pv210-g2d";
reg = <0x12800000 0x1000>;
interrupts = <0 89 0>;
status = "disabled";
};
};

21
arch/arm/boot/dts/exynos4412-origen.dts
View File

@ -72,6 +72,27 @@
status = "okay";
};
fimd@11c00000 {
pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
pinctrl-names = "default";
status = "okay";
};
display-timings {
native-mode = <&timing0>;
timing0: timing {
clock-frequency = <50000>;
hactive = <1024>;
vactive = <600>;
hfront-porch = <64>;
hback-porch = <16>;
hsync-len = <48>;
vback-porch = <64>;
vfront-porch = <16>;
vsync-len = <3>;
};
};
serial@13800000 {
status = "okay";
};

8
arch/arm/boot/dts/exynos4412-smdk4412.dts
View File

@ -27,6 +27,14 @@
bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
};
g2d@10800000 {
status = "okay";
};
g2d@10800000 {
status = "okay";
};
sdhci@12530000 {
bus-width = <4>;
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;

8
arch/arm/boot/dts/exynos4412.dtsi
View File

@ -51,4 +51,12 @@
<0x7 0 &gic 1 12 0>;
};
};
mshc@12550000 {
compatible = "samsung,exynos4412-dw-mshc";
reg = <0x12550000 0x1000>;
interrupts = <0 77 0>;
#address-cells = <1>;
#size-cells = <0>;
};
};

7
arch/arm/boot/dts/exynos4x12.dtsi
View File

@ -72,4 +72,11 @@
reg = <0x106E0000 0x1000>;
interrupts = <0 72 0>;
};
g2d@10800000 {
compatible = "samsung,exynos4212-g2d";
reg = <0x10800000 0x1000>;
interrupts = <0 89 0>;
status = "disabled";
};
};

343
arch/arm/boot/dts/exynos5250-arndale.dts
View File

@ -24,8 +24,266 @@
bootargs = "console=ttySAC2,115200";
};
codec@11000000 {
samsung,mfc-r = <0x43000000 0x800000>;
samsung,mfc-l = <0x51000000 0x800000>;
};
i2c@12C60000 {
status = "disabled";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <20000>;
samsung,i2c-slave-addr = <0x66>;
s5m8767_pmic@66 {
compatible = "samsung,s5m8767-pmic";
reg = <0x66>;
s5m8767,pmic-buck2-dvs-voltage = <1300000>;
s5m8767,pmic-buck3-dvs-voltage = <1100000>;
s5m8767,pmic-buck4-dvs-voltage = <1200000>;
s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 0>,
<&gpd1 1 0>,
<&gpd1 2 0>;
s5m8767,pmic-buck-ds-gpios = <&gpx2 3 0>,
<&gpx2 4 0>,
<&gpx2 5 0>;
regulators {
ldo1_reg: LDO1 {
regulator-name = "VDD_ALIVE_1.0V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
ldo2_reg: LDO2 {
regulator-name = "VDD_28IO_DP_1.35V";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
ldo3_reg: LDO3 {
regulator-name = "VDD_COMMON1_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
ldo4_reg: LDO4 {
regulator-name = "VDD_IOPERI_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
op_mode = <1>;
};
ldo5_reg: LDO5 {
regulator-name = "VDD_EXT_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
ldo6_reg: LDO6 {
regulator-name = "VDD_MPLL_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
ldo7_reg: LDO7 {
regulator-name = "VDD_XPLL_1.1V";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
ldo8_reg: LDO8 {
regulator-name = "VDD_COMMON2_1.0V";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
ldo9_reg: LDO9 {
regulator-name = "VDD_33ON_3.0V";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
op_mode = <1>;
};
ldo10_reg: LDO10 {
regulator-name = "VDD_COMMON3_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
ldo11_reg: LDO11 {
regulator-name = "VDD_ABB2_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
ldo12_reg: LDO12 {
regulator-name = "VDD_USB_3.0V";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
ldo13_reg: LDO13 {
regulator-name = "VDDQ_C2C_W_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
ldo14_reg: LDO14 {
regulator-name = "VDD18_ABB0_3_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
ldo15_reg: LDO15 {
regulator-name = "VDD10_COMMON4_1.0V";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
ldo16_reg: LDO16 {
regulator-name = "VDD18_HSIC_1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
ldo17_reg: LDO17 {
regulator-name = "VDDQ_MMC2_3_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
ldo18_reg: LDO18 {
regulator-name = "VDD_33ON_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
op_mode = <1>;
};
ldo22_reg: LDO22 {
regulator-name = "EXT_33_OFF";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
op_mode = <1>;
};
ldo23_reg: LDO23 {
regulator-name = "EXT_28_OFF";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
op_mode = <1>;
};
ldo25_reg: LDO25 {
regulator-name = "PVDD_LDO25";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
op_mode = <1>;
};
ldo26_reg: LDO26 {
regulator-name = "EXT_18_OFF";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
op_mode = <1>;
};
buck1_reg: BUCK1 {
regulator-name = "vdd_mif";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
buck2_reg: BUCK2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
buck3_reg: BUCK3 {
regulator-name = "vdd_int";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
buck4_reg: BUCK4 {
regulator-name = "vdd_g3d";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
op_mode = <1>;
};
buck5_reg: BUCK5 {
regulator-name = "VDD_MEM_1.35V";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1355000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>;
};
buck9_reg: BUCK9 {
regulator-name = "VDD_33_OFF_EXT1";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <3000000>;
op_mode = <1>;
};
};
};
};
i2c@12C70000 {
@ -69,15 +327,13 @@
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
vmmc-supply = <&mmc_reg>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
slot@0 {
reg = <0>;
bus-width = <8>;
gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
<&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
<&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>,
<&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
<&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>;
};
};
@ -93,14 +349,14 @@
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
vmmc-supply = <&mmc_reg>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
slot@0 {
reg = <0>;
bus-width = <4>;
samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
<&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
<&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
disable-wp;
};
};
@ -120,6 +376,73 @@
status = "disabled";
};
gpio_keys {
compatible = "gpio-keys";
menu {
label = "SW-TACT2";
gpios = <&gpx1 4 1>;
linux,code = <139>;
gpio-key,wakeup;
};
home {
label = "SW-TACT3";
gpios = <&gpx1 5 1>;
linux,code = <102>;
gpio-key,wakeup;
};
up {
label = "SW-TACT4";
gpios = <&gpx1 6 1>;
linux,code = <103>;
gpio-key,wakeup;
};
down {
label = "SW-TACT5";
gpios = <&gpx1 7 1>;
linux,code = <108>;
gpio-key,wakeup;
};
back {
label = "SW-TACT6";
gpios = <&gpx2 0 1>;
linux,code = <158>;
gpio-key,wakeup;
};
wakeup {
label = "SW-TACT7";
gpios = <&gpx2 1 1>;
linux,code = <143>;
gpio-key,wakeup;
};
};
hdmi {
hpd-gpio = <&gpx3 7 2>;
vdd_osc-supply = <&ldo10_reg>;
vdd_pll-supply = <&ldo8_reg>;
vdd-supply = <&ldo8_reg>;
};
mmc_reg: voltage-regulator {
compatible = "regulator-fixed";
regulator-name = "VDD_33ON_2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&gpx1 1 1>;
enable-active-high;
};
reg_hdmi_en: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "hdmi-en";
};
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";

783
arch/arm/boot/dts/exynos5250-pinctrl.dtsi Normal file
View File

@ -0,0 +1,783 @@
/*
* Samsung's Exynos5250 SoC pin-mux and pin-config device tree source
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Samsung's Exynos5250 SoC pin-mux and pin-config optiosn are listed as device
* tree nodes are listed in this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/ {
pinctrl@11400000 {
gpa0: gpa0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpa1: gpa1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpa2: gpa2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb0: gpb0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb1: gpb1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb2: gpb2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpb3: gpb3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc0: gpc0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc1: gpc1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc2: gpc2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpc3: gpc3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd0: gpd0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpd1: gpd1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpy0: gpy0 {
gpio-controller;
#gpio-cells = <2>;
};
gpy1: gpy1 {
gpio-controller;
#gpio-cells = <2>;
};
gpy2: gpy2 {
gpio-controller;
#gpio-cells = <2>;
};
gpy3: gpy3 {
gpio-controller;
#gpio-cells = <2>;
};
gpy4: gpy4 {
gpio-controller;
#gpio-cells = <2>;
};
gpy5: gpy5 {
gpio-controller;
#gpio-cells = <2>;
};
gpy6: gpy6 {
gpio-controller;
#gpio-cells = <2>;
};
gpc4: gpc4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpx0: gpx0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&combiner>;
#interrupt-cells = <2>;
interrupts = <23 0>, <24 0>, <25 0>, <25 1>,
<26 0>, <26 1>, <27 0>, <27 1>;
};
gpx1: gpx1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&combiner>;
#interrupt-cells = <2>;
interrupts = <28 0>, <28 1>, <29 0>, <29 1>,
<30 0>, <30 1>, <31 0>, <31 1>;
};
gpx2: gpx2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpx3: gpx3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
uart0_data: uart0-data {
samsung,pins = "gpa0-0", "gpa0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart0_fctl: uart0-fctl {
samsung,pins = "gpa0-2", "gpa0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
};
i2c2_bus: i2c2-bus {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
};
i2c2_hs_bus: i2c2-hs-bus {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
};
uart2_data: uart2-data {
samsung,pins = "gpa1-0", "gpa1-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart2_fctl: uart2-fctl {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
};
i2c3_bus: i2c3-bus {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
};
i2c3_hs_bus: i2c3-hs-bus {
samsung,pins = "gpa1-2", "gpa1-3";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
};
uart3_data: uart3-data {
samsung,pins = "gpa1-4", "gpa1-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
spi0_bus: spi0-bus {
samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2c4_bus: i2c4-bus {
samsung,pins = "gpa2-0", "gpa2-1";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
};
i2c5_bus: i2c5-bus {
samsung,pins = "gpa2-2", "gpa2-3";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
};
spi1_bus: spi1-bus {
samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2s1_bus: i2s1-bus {
samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
"gpb0-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pcm1_bus: pcm1-bus {
samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
"gpb0-4";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
ac97_bus: ac97-bus {
samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
"gpb0-4";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
i2s2_bus: i2s2-bus {
samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
"gpb1-4";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
pcm2_bus: pcm2-bus {
samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
"gpb1-4";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
spdif_bus: spdif-bus {
samsung,pins = "gpb1-0", "gpb1-1";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
spi2_bus: spi2-bus {
samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4";
samsung,pin-function = <5>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2c6_bus: i2c6-bus {
samsung,pins = "gpb1-3", "gpb1-4";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2c7_bus: i2c7-bus {
samsung,pins = "gpb2-2", "gpb2-3";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2c0_bus: i2c0-bus {
samsung,pins = "gpb3-0", "gpb3-1";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2c1_bus: i2c1-bus {
samsung,pins = "gpb3-2", "gpb3-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
i2c0_hs_bus: i2c0-hs-bus {
samsung,pins = "gpb3-0", "gpb3-1";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
};
i2c1_hs_bus: i2c1-hs-bus {
samsung,pins = "gpb3-2", "gpb3-3";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
};
sd0_clk: sd0-clk {
samsung,pins = "gpc0-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd0_cmd: sd0-cmd {
samsung,pins = "gpc0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd0_cd: sd0-cd {
samsung,pins = "gpc0-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd0_bus1: sd0-bus-width1 {
samsung,pins = "gpc0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd0_bus4: sd0-bus-width4 {
samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd0_bus8: sd0-bus-width8 {
samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd1_clk: sd1-clk {
samsung,pins = "gpc2-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd1_cmd: sd1-cmd {
samsung,pins = "gpc2-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd1_cd: sd1-cd {
samsung,pins = "gpc2-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd1_bus1: sd1-bus-width1 {
samsung,pins = "gpc2-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd1_bus4: sd1-bus-width4 {
samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd2_clk: sd2-clk {
samsung,pins = "gpc3-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd2_cmd: sd2-cmd {
samsung,pins = "gpc3-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd2_cd: sd2-cd {
samsung,pins = "gpc3-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd2_bus1: sd2-bus-width1 {
samsung,pins = "gpc3-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd2_bus4: sd2-bus-width4 {
samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd2_bus8: sd2-bus-width8 {
samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6";
samsung,pin-function = <3>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd3_clk: sd3-clk {
samsung,pins = "gpc4-0";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd3_cmd: sd3-cmd {
samsung,pins = "gpc4-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <3>;
};
sd3_cd: sd3-cd {
samsung,pins = "gpc4-2";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd3_bus1: sd3-bus-width1 {
samsung,pins = "gpc4-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
sd3_bus4: sd3-bus-width4 {
samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samsung,pin-drv = <3>;
};
uart1_data: uart1-data {
samsung,pins = "gpd0-0", "gpd0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
uart1_fctl: uart1-fctl {
samsung,pins = "gpd0-2", "gpd0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
};
};
pinctrl@13400000 {
gpe0: gpe0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpe1: gpe1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf0: gpf0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpf1: gpf1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg0: gpg0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg1: gpg1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpg2: gpg2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gph0: gph0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gph1: gph1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
cam_gpio_a: cam-gpio-a {
samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
"gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
"gpe1-0", "gpe1-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
cam_gpio_b: cam-gpio-b {
samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3",
"gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
samsung,pin-function = <3>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
};
cam_i2c2_bus: cam-i2c2-bus {
samsung,pins = "gpe0-6", "gpe1-0";
samsung,pin-function = <4>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
};
cam_spi1_bus: cam-spi1-bus {
samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3";
samsung,pin-function = <4>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
};
cam_i2c1_bus: cam-i2c1-bus {
samsung,pins = "gpf0-2", "gpf0-3";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
};
cam_i2c0_bus: cam-i2c0-bus {
samsung,pins = "gpf0-0", "gpf0-1";
samsung,pin-function = <2>;
samsung,pin-pud = <3>;
samaung,pin-drv = <0>;
};
cam_spi0_bus: cam-spi0-bus {
samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
};
cam_bayrgb_bus: cam-bayrgb-bus {
samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3",
"gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7",
"gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3",
"gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7",
"gpg2-0", "gpg2-1";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
};
cam_port_a: cam-port-a {
samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3",
"gph1-0", "gph1-1", "gph1-2", "gph1-3",
"gph1-4", "gph1-5", "gph1-6", "gph1-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
};
};
pinctrl@10d10000 {
gpv0: gpv0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpv1: gpv1 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpv2: gpv2 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpv3: gpv3 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpv4: gpv4 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
c2c_rxd: c2c-rxd {
samsung,pins = "gpv0-0", "gpv0-1", "gpv0-2", "gpv0-3",
"gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7",
"gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3",
"gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
};
c2c_txd: c2c-txd {
samsung,pins = "gpv2-0", "gpv2-1", "gpv2-2", "gpv2-3",
"gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7",
"gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3",
"gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samaung,pin-drv = <0>;
};
};
pinctrl@03680000 {
gpz: gpz {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
i2s0_bus: i2s0-bus {
samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
"gpz-4", "gpz-5", "gpz-6";
samsung,pin-function = <2>;
samsung,pin-pud = <0>;
samsung,pin-drv = <0>;
};
};
};

49
arch/arm/boot/dts/exynos5250-smdk5250.dts
View File

@ -30,8 +30,6 @@
i2c@12C60000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <20000>;
gpios = <&gpb3 0 2 3 0>,
<&gpb3 1 2 3 0>;
eeprom@50 {
compatible = "samsung,s524ad0xd1";
@ -42,8 +40,6 @@
i2c@12C70000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <20000>;
gpios = <&gpb3 2 2 3 0>,
<&gpb3 3 2 3 0>;
eeprom@51 {
compatible = "samsung,s524ad0xd1";
@ -74,8 +70,6 @@
i2c@12C80000 {
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
gpios = <&gpa0 6 3 3 0>,
<&gpa0 7 3 3 0>;
hdmiddc@50 {
compatible = "samsung,exynos5-hdmiddc";
@ -122,15 +116,12 @@
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
slot@0 {
reg = <0>;
bus-width = <8>;
gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
<&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
<&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>,
<&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
<&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>;
};
};
@ -146,17 +137,13 @@
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
slot@0 {
reg = <0>;
bus-width = <4>;
samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
disable-wp;
gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
<&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
<&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>,
<&gpc4 3 3 3 3>, <&gpc4 3 3 3 3>,
<&gpc4 5 3 3 3>, <&gpc4 6 3 3 3>;
};
};
@ -169,10 +156,6 @@
};
spi_1: spi@12d30000 {
gpios = <&gpa2 4 2 3 0>,
<&gpa2 6 2 3 0>,
<&gpa2 7 2 3 0>;
w25q80bw@0 {
#address-cells = <1>;
#size-cells = <1>;
@ -181,7 +164,7 @@
spi-max-frequency = <1000000>;
controller-data {
cs-gpio = <&gpa2 5 1 0 3>;
cs-gpio = <&gpa2 5 0>;
samsung,spi-feedback-delay = <0>;
};
@ -203,7 +186,7 @@
};
hdmi {
hpd-gpio = <&gpx3 7 0xf 1 3>;
hpd-gpio = <&gpx3 7 0>;
};
codec@11000000 {
@ -212,9 +195,7 @@
};
i2s0: i2s@03830000 {
gpios = <&gpz 0 2 0 0>, <&gpz 1 2 0 0>, <&gpz 2 2 0 0>,
<&gpz 3 2 0 0>, <&gpz 4 2 0 0>, <&gpz 5 2 0 0>,
<&gpz 6 2 0 0>;
status = "okay";
};
i2s1: i2s@12D60000 {
@ -245,6 +226,22 @@
samsung,lane-count = <4>;
};
display-timings {
native-mode = <&timing0>;
timing0: timing@0 {
/* 1280x800 */
clock-frequency = <50000>;
hactive = <1280>;
vactive = <800>;
hfront-porch = <4>;
hback-porch = <4>;
hsync-len = <4>;
vback-porch = <4>;
vfront-porch = <4>;
vsync-len = <4>;
};
};
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";

149
arch/arm/boot/dts/exynos5250-snow.dts
View File

@ -16,12 +16,31 @@
model = "Google Snow";
compatible = "google,snow", "samsung,exynos5250";
aliases {
i2c104 = &i2c_104;
};
pinctrl@11400000 {
sd3_clk: sd3-clk {
samsung,pin-drv = <0>;
};
sd3_cmd: sd3-cmd {
samsung,pin-pud = <3>;
samsung,pin-drv = <0>;
};
sd3_bus4: sd3-bus-width4 {
samsung,pin-drv = <0>;
};
};
gpio-keys {
compatible = "gpio-keys";
lid-switch {
label = "Lid";
gpios = <&gpx3 5 0 0x10000 0>;
gpios = <&gpx3 5 1>;
linux,input-type = <5>; /* EV_SW */
linux,code = <0>; /* SW_LID */
debounce-interval = <1>;
@ -29,15 +48,137 @@
};
};
i2c-arbitrator {
compatible = "i2c-arb-gpio-challenge";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&{/i2c@12CA0000}>;
our-claim-gpio = <&gpf0 3 1>;
their-claim-gpios = <&gpe0 4 1>;
slew-delay-us = <10>;
wait-retry-us = <3000>;
wait-free-us = <50000>;
/* Use ID 104 as a hint that we're on physical bus 4 */
i2c_104: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
battery: sbs-battery@b {
compatible = "sbs,sbs-battery";
reg = <0xb>;
sbs,poll-retry-count = <1>;
};
ec: embedded-controller {
compatible = "google,cros-ec-i2c";
reg = <0x1e>;
interrupts = <6 0>;
interrupt-parent = <&gpx1>;
wakeup-source;
keyboard-controller {
compatible = "google,cros-ec-keyb";
keypad,num-rows = <8>;
keypad,num-columns = <13>;
google,needs-ghost-filter;
linux,keymap = <0x0001003a /* CAPSLK */
0x0002003b /* F1 */
0x00030030 /* B */
0x00040044 /* F10 */
0x00060031 /* N */
0x0008000d /* = */
0x000a0064 /* R_ALT */
0x01010001 /* ESC */
0x0102003e /* F4 */
0x01030022 /* G */
0x01040041 /* F7 */
0x01060023 /* H */
0x01080028 /* ' */
0x01090043 /* F9 */
0x010b000e /* BKSPACE */
0x0200001d /* L_CTRL */
0x0201000f /* TAB */
0x0202003d /* F3 */
0x02030014 /* T */
0x02040040 /* F6 */
0x0205001b /* ] */
0x02060015 /* Y */
0x02070056 /* 102ND */
0x0208001a /* [ */
0x02090042 /* F8 */
0x03010029 /* GRAVE */
0x0302003c /* F2 */
0x03030006 /* 5 */
0x0304003f /* F5 */
0x03060007 /* 6 */
0x0308000c /* - */
0x030b002b /* \ */
0x04000061 /* R_CTRL */
0x0401001e /* A */
0x04020020 /* D */
0x04030021 /* F */
0x0404001f /* S */
0x04050025 /* K */
0x04060024 /* J */
0x04080027 /* ; */
0x04090026 /* L */
0x040b001c /* ENTER */
0x0501002c /* Z */
0x0502002e /* C */
0x0503002f /* V */
0x0504002d /* X */
0x05050033 /* , */
0x05060032 /* M */
0x0507002a /* L_SHIFT */
0x05080035 /* / */
0x05090034 /* . */
0x050B0039 /* SPACE */
0x06010002 /* 1 */
0x06020004 /* 3 */
0x06030005 /* 4 */
0x06040003 /* 2 */
0x06050009 /* 8 */
0x06060008 /* 7 */
0x0608000b /* 0 */
0x0609000a /* 9 */
0x060a0038 /* L_ALT */
0x060b006c /* DOWN */
0x060c006a /* RIGHT */
0x07010010 /* Q */
0x07020012 /* E */
0x07030013 /* R */
0x07040011 /* W */
0x07050017 /* I */
0x07060016 /* U */
0x07070036 /* R_SHIFT */
0x07080019 /* P */
0x07090018 /* O */
0x070b0067 /* UP */
0x070c0069>; /* LEFT */
};
};
};
};
/*
* On Snow we've got SIP WiFi and so can keep drive strengths low to
* reduce EMI.
*/
dwmmc3@12230000 {
slot@0 {
gpios = <&gpc4 0 2 0 0>, <&gpc4 1 2 3 0>,
<&gpc4 3 2 3 0>, <&gpc4 4 2 3 0>,
<&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
pinctrl-names = "default";
pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>;
};
};

348
arch/arm/boot/dts/exynos5250.dtsi
View File

@ -18,6 +18,7 @@
*/
/include/ "skeleton.dtsi"
/include/ "exynos5250-pinctrl.dtsi"
/ {
compatible = "samsung,exynos5250";
@ -44,6 +45,15 @@
i2c6 = &i2c_6;
i2c7 = &i2c_7;
i2c8 = &i2c_8;
pinctrl0 = &pinctrl_0;
pinctrl1 = &pinctrl_1;
pinctrl2 = &pinctrl_2;
pinctrl3 = &pinctrl_3;
};
chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};
pd_gsc: gsc-power-domain@0x10044000 {
@ -63,10 +73,22 @@
};
gic:interrupt-controller@10481000 {
compatible = "arm,cortex-a9-gic";
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10481000 0x1000>, <0x10482000 0x2000>;
reg = <0x10481000 0x1000>,
<0x10482000 0x1000>,
<0x10484000 0x2000>,
<0x10486000 0x2000>;
interrupts = <1 9 0xf04>;
};
timer {
compatible = "arm,armv7-timer";
interrupts = <1 13 0xf08>,
<1 14 0xf08>,
<1 11 0xf08>,
<1 10 0xf08>;
};
combiner:interrupt-controller@10440000 {
@ -115,6 +137,36 @@
interrupts = <1 2>, <22 4>;
};
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <0 46 0>;
wakup_eint: wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
interrupts = <0 32 0>;
};
};
pinctrl_1: pinctrl@13400000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x13400000 0x1000>;
interrupts = <0 45 0>;
};
pinctrl_2: pinctrl@10d10000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x10d10000 0x1000>;
interrupts = <0 50 0>;
};
pinctrl_3: pinctrl@03680000 {
compatible = "samsung,exynos5250-pinctrl";
reg = <0x0368000 0x1000>;
interrupts = <0 47 0>;
};
watchdog {
compatible = "samsung,s3c2410-wdt";
reg = <0x101D0000 0x100>;
@ -200,6 +252,8 @@
#size-cells = <0>;
clocks = <&clock 294>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_bus>;
};
i2c_1: i2c@12C70000 {
@ -210,6 +264,8 @@
#size-cells = <0>;
clocks = <&clock 295>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_bus>;
};
i2c_2: i2c@12C80000 {
@ -220,6 +276,8 @@
#size-cells = <0>;
clocks = <&clock 296>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_bus>;
};
i2c_3: i2c@12C90000 {
@ -230,6 +288,8 @@
#size-cells = <0>;
clocks = <&clock 297>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c3_bus>;
};
i2c_4: i2c@12CA0000 {
@ -240,6 +300,8 @@
#size-cells = <0>;
clocks = <&clock 298>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c4_bus>;
};
i2c_5: i2c@12CB0000 {
@ -250,6 +312,8 @@
#size-cells = <0>;
clocks = <&clock 299>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c5_bus>;
};
i2c_6: i2c@12CC0000 {
@ -260,6 +324,8 @@
#size-cells = <0>;
clocks = <&clock 300>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c6_bus>;
};
i2c_7: i2c@12CD0000 {
@ -270,6 +336,8 @@
#size-cells = <0>;
clocks = <&clock 301>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c7_bus>;
};
i2c_8: i2c@12CE0000 {
@ -302,6 +370,8 @@
#size-cells = <0>;
clocks = <&clock 304>, <&clock 154>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>;
};
spi_1: spi@12d30000 {
@ -315,6 +385,8 @@
#size-cells = <0>;
clocks = <&clock 305>, <&clock 155>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
};
spi_2: spi@12d40000 {
@ -328,6 +400,8 @@
#size-cells = <0>;
clocks = <&clock 306>, <&clock 156>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi2_bus>;
};
dwmmc_0: dwmmc0@12200000 {
@ -381,6 +455,8 @@
samsung,supports-rstclr;
samsung,supports-secdai;
samsung,idma-addr = <0x03000000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
};
i2s1: i2s@12D60000 {
@ -389,6 +465,8 @@
dmas = <&pdma1 12
&pdma1 11>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&i2s1_bus>;
};
i2s2: i2s@12D70000 {
@ -397,18 +475,26 @@
dmas = <&pdma0 12
&pdma0 11>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&i2s2_bus>;
};
usb@12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
interrupts = <0 71 0>;
clocks = <&clock 285>;
clock-names = "usbhost";
};
usb@12120000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12120000 0x100>;
interrupts = <0 71 0>;
clocks = <&clock 285>;
clock-names = "usbhost";
};
amba {
@ -463,254 +549,6 @@
};
};
gpio-controllers {
#address-cells = <1>;
#size-cells = <1>;
gpio-controller;
ranges;
gpa0: gpio-controller@11400000 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400000 0x20>;
#gpio-cells = <4>;
};
gpa1: gpio-controller@11400020 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400020 0x20>;
#gpio-cells = <4>;
};
gpa2: gpio-controller@11400040 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400040 0x20>;
#gpio-cells = <4>;
};
gpb0: gpio-controller@11400060 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400060 0x20>;
#gpio-cells = <4>;
};
gpb1: gpio-controller@11400080 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400080 0x20>;
#gpio-cells = <4>;
};
gpb2: gpio-controller@114000A0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114000A0 0x20>;
#gpio-cells = <4>;
};
gpb3: gpio-controller@114000C0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114000C0 0x20>;
#gpio-cells = <4>;
};
gpc0: gpio-controller@114000E0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114000E0 0x20>;
#gpio-cells = <4>;
};
gpc1: gpio-controller@11400100 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400100 0x20>;
#gpio-cells = <4>;
};
gpc2: gpio-controller@11400120 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400120 0x20>;
#gpio-cells = <4>;
};
gpc3: gpio-controller@11400140 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400140 0x20>;
#gpio-cells = <4>;
};
gpc4: gpio-controller@114002E0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114002E0 0x20>;
#gpio-cells = <4>;
};
gpd0: gpio-controller@11400160 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400160 0x20>;
#gpio-cells = <4>;
};
gpd1: gpio-controller@11400180 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400180 0x20>;
#gpio-cells = <4>;
};
gpy0: gpio-controller@114001A0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114001A0 0x20>;
#gpio-cells = <4>;
};
gpy1: gpio-controller@114001C0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114001C0 0x20>;
#gpio-cells = <4>;
};
gpy2: gpio-controller@114001E0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114001E0 0x20>;
#gpio-cells = <4>;
};
gpy3: gpio-controller@11400200 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400200 0x20>;
#gpio-cells = <4>;
};
gpy4: gpio-controller@11400220 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400220 0x20>;
#gpio-cells = <4>;
};
gpy5: gpio-controller@11400240 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400240 0x20>;
#gpio-cells = <4>;
};
gpy6: gpio-controller@11400260 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400260 0x20>;
#gpio-cells = <4>;
};
gpx0: gpio-controller@11400C00 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400C00 0x20>;
#gpio-cells = <4>;
};
gpx1: gpio-controller@11400C20 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400C20 0x20>;
#gpio-cells = <4>;
};
gpx2: gpio-controller@11400C40 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400C40 0x20>;
#gpio-cells = <4>;
};
gpx3: gpio-controller@11400C60 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400C60 0x20>;
#gpio-cells = <4>;
};
gpe0: gpio-controller@13400000 {
compatible = "samsung,exynos4-gpio";
reg = <0x13400000 0x20>;
#gpio-cells = <4>;
};
gpe1: gpio-controller@13400020 {
compatible = "samsung,exynos4-gpio";
reg = <0x13400020 0x20>;
#gpio-cells = <4>;
};
gpf0: gpio-controller@13400040 {
compatible = "samsung,exynos4-gpio";
reg = <0x13400040 0x20>;
#gpio-cells = <4>;
};
gpf1: gpio-controller@13400060 {
compatible = "samsung,exynos4-gpio";
reg = <0x13400060 0x20>;
#gpio-cells = <4>;
};
gpg0: gpio-controller@13400080 {
compatible = "samsung,exynos4-gpio";
reg = <0x13400080 0x20>;
#gpio-cells = <4>;
};
gpg1: gpio-controller@134000A0 {
compatible = "samsung,exynos4-gpio";
reg = <0x134000A0 0x20>;
#gpio-cells = <4>;
};
gpg2: gpio-controller@134000C0 {
compatible = "samsung,exynos4-gpio";
reg = <0x134000C0 0x20>;
#gpio-cells = <4>;
};
gph0: gpio-controller@134000E0 {
compatible = "samsung,exynos4-gpio";
reg = <0x134000E0 0x20>;
#gpio-cells = <4>;
};
gph1: gpio-controller@13400100 {
compatible = "samsung,exynos4-gpio";
reg = <0x13400100 0x20>;
#gpio-cells = <4>;
};
gpv0: gpio-controller@10D10000 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10000 0x20>;
#gpio-cells = <4>;
};
gpv1: gpio-controller@10D10020 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10020 0x20>;
#gpio-cells = <4>;
};
gpv2: gpio-controller@10D10040 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10060 0x20>;
#gpio-cells = <4>;
};
gpv3: gpio-controller@10D10060 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10080 0x20>;
#gpio-cells = <4>;
};
gpv4: gpio-controller@10D10080 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D100C0 0x20>;
#gpio-cells = <4>;
};
gpz: gpio-controller@03860000 {
compatible = "samsung,exynos4-gpio";
reg = <0x03860000 0x20>;
#gpio-cells = <4>;
};
};
gsc_0: gsc@0x13e00000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
@ -776,4 +614,14 @@
samsung,enable-mask = <1>;
};
};
fimd {
compatible = "samsung,exynos5250-fimd";
interrupt-parent = <&combiner>;
reg = <0x14400000 0x40000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <18 4>, <18 5>, <18 6>;
clocks = <&clock 133>, <&clock 339>;
clock-names = "sclk_fimd", "fimd";
};
};

39
arch/arm/boot/dts/exynos5440-sd5v1.dts Normal file
View File

@ -0,0 +1,39 @@
/*
* SAMSUNG SD5v1 board device tree source
*
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/include/ "exynos5440.dtsi"
/ {
model = "SAMSUNG SD5v1 board based on EXYNOS5440";
compatible = "samsung,sd5v1", "samsung,exynos5440";
chosen {
bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
};
fixed-rate-clocks {
xtal {
compatible = "samsung,clock-xtal";
clock-frequency = <50000000>;
};
};
gmac: ethernet@00230000 {
fixed_phy;
phy_addr = <1>;
};
spi {
status = "disabled";
};
};

6
arch/arm/boot/dts/exynos5440-ssdk5440.dts
View File

@ -16,12 +16,8 @@
model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
compatible = "samsung,ssdk5440", "samsung,exynos5440";
memory {
reg = <0x80000000 0x80000000>;
};
chosen {
bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x81000000,8M console=ttySAC0,115200 init=/linuxrc";
bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
};
spi {

55
arch/arm/boot/dts/exynos5440.dtsi
View File

@ -26,7 +26,11 @@
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x2E1000 0x1000>, <0x2E2000 0x1000>;
reg = <0x2E1000 0x1000>,
<0x2E2000 0x1000>,
<0x2E4000 0x2000>,
<0x2E6000 0x2000>;
interrupts = <1 9 0xf04>;
};
cpus {
@ -51,6 +55,14 @@
};
};
arm-pmu {
compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
interrupts = <0 52 4>,
<0 53 4>,
<0 54 4>,
<0 55 4>;
};
timer {
compatible = "arm,cortex-a15-timer",
"arm,armv7-timer";
@ -61,6 +73,18 @@
clock-frequency = <50000000>;
};
cpufreq@160000 {
compatible = "samsung,exynos5440-cpufreq";
reg = <0x160000 0x1000>;
interrupts = <0 57 0>;
operating-points = <
/* KHz uV */
1200000 1025000
1000000 975000
800000 925000
>;
};
serial@B0000 {
compatible = "samsung,exynos4210-uart";
reg = <0xB0000 0x1000>;
@ -92,6 +116,8 @@
pinctrl {
compatible = "samsung,exynos5440-pinctrl";
reg = <0xE0000 0x1000>;
interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
<0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
interrupt-controller;
#interrupt-cells = <2>;
#gpio-cells = <2>;
@ -141,6 +167,17 @@
clock-names = "watchdog";
};
gmac: ethernet@00230000 {
compatible = "snps,dwmac-3.70a";
reg = <0x00230000 0x8000>;
interrupt-parent = <&gic>;
interrupts = <0 31 4>;
interrupt-names = "macirq";
phy-mode = "sgmii";
clocks = <&clock 25>;
clock-names = "stmmaceth";
};
amba {
#address-cells = <1>;
#size-cells = <1>;
@ -148,22 +185,22 @@
interrupt-parent = <&gic>;
ranges;
pdma0: pdma@121A0000 {
pdma0: pdma@00121000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x120000 0x1000>;
interrupts = <0 34 0>;
clocks = <&clock 21>;
reg = <0x121000 0x1000>;
interrupts = <0 46 0>;
clocks = <&clock 8>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@121B0000 {
pdma1: pdma@00120000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121000 0x1000>;
interrupts = <0 35 0>;
clocks = <&clock 21>;
reg = <0x120000 0x1000>;
interrupts = <0 47 0>;
clocks = <&clock 8>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;

36
arch/arm/boot/dts/imx23-evk.dts
View File

@ -59,8 +59,33 @@
lcdif@80030000 {
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a>;
panel-enable-gpios = <&gpio1 18 0>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display>;
status = "okay";
display: display {
bits-per-pixel = <32>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <9200000>;
hactive = <480>;
vactive = <272>;
hback-porch = <15>;
hfront-porch = <8>;
vback-porch = <12>;
vfront-porch = <4>;
hsync-len = <1>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
};
@ -95,6 +120,15 @@
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 29 0>;
};
reg_lcd_3v3: lcd-3v3 {
compatible = "regulator-fixed";
regulator-name = "lcd-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 18 0>;
enable-active-high;
};
};
backlight {

1
arch/arm/boot/dts/imx23-olinuxino.dts
View File

@ -29,6 +29,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
bus-width = <4>;
broken-cd;
status = "okay";
};

42
arch/arm/boot/dts/imx23.dtsi
View File

@ -49,9 +49,15 @@
reg = <0x80000000 0x2000>;
};
dma-apbh@80004000 {
dma_apbh: dma-apbh@80004000 {
compatible = "fsl,imx23-dma-apbh";
reg = <0x80004000 0x2000>;
interrupts = <0 14 20 0
13 13 13 13>;
interrupt-names = "empty", "ssp0", "ssp1", "empty",
"gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <8>;
clocks = <&clks 15>;
};
@ -70,6 +76,8 @@
interrupt-names = "gpmi-dma", "bch";
clocks = <&clks 34>;
clock-names = "gpmi_io";
dmas = <&dma_apbh 4>;
dma-names = "rx-tx";
fsl,gpmi-dma-channel = <4>;
status = "disabled";
};
@ -78,6 +86,8 @@
reg = <0x80010000 0x2000>;
interrupts = <15 14>;
clocks = <&clks 33>;
dmas = <&dma_apbh 1>;
dma-names = "rx-tx";
fsl,ssp-dma-channel = <1>;
status = "disabled";
};
@ -305,9 +315,19 @@
status = "disabled";
};
dma-apbx@80024000 {
dma_apbx: dma-apbx@80024000 {
compatible = "fsl,imx23-dma-apbx";
reg = <0x80024000 0x2000>;
interrupts = <7 5 9 26
19 0 25 23
60 58 9 0
0 0 0 0>;
interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c",
"saif0", "empty", "auart0-rx", "auart0-tx",
"auart1-rx", "auart1-tx", "saif1", "empty",
"empty", "empty", "empty", "empty";
#dma-cells = <1>;
dma-channels = <16>;
clocks = <&clks 16>;
};
@ -344,6 +364,8 @@
reg = <0x80034000 0x2000>;
interrupts = <2 20>;
clocks = <&clks 33>;
dmas = <&dma_apbh 2>;
dma-names = "rx-tx";
fsl,ssp-dma-channel = <2>;
status = "disabled";
};
@ -369,6 +391,8 @@
saif0: saif@80042000 {
reg = <0x80042000 0x2000>;
dmas = <&dma_apbx 4>;
dma-names = "rx-tx";
status = "disabled";
};
@ -379,16 +403,22 @@
saif1: saif@80046000 {
reg = <0x80046000 0x2000>;
dmas = <&dma_apbx 10>;
dma-names = "rx-tx";
status = "disabled";
};
audio-out@80048000 {
reg = <0x80048000 0x2000>;
dmas = <&dma_apbx 1>;
dma-names = "tx";
status = "disabled";
};
audio-in@8004c000 {
reg = <0x8004c000 0x2000>;
dmas = <&dma_apbx 0>;
dma-names = "rx";
status = "disabled";
};
@ -401,11 +431,15 @@
spdif@80054000 {
reg = <0x80054000 2000>;
dmas = <&dma_apbx 2>;
dma-names = "tx";
status = "disabled";
};
i2c@80058000 {
reg = <0x80058000 0x2000>;
dmas = <&dma_apbx 3>;
dma-names = "rx-tx";
status = "disabled";
};
@ -436,6 +470,8 @@
reg = <0x8006c000 0x2000>;
interrupts = <24 25 23>;
clocks = <&clks 32>;
dmas = <&dma_apbx 6>, <&dma_apbx 7>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -444,6 +480,8 @@
reg = <0x8006e000 0x2000>;
interrupts = <59 60 58>;
clocks = <&clks 32>;
dmas = <&dma_apbx 8>, <&dma_apbx 9>;
dma-names = "rx", "tx";
status = "disabled";
};

25
arch/arm/boot/dts/imx28-apf28dev.dts
View File

@ -72,7 +72,32 @@
pinctrl-names = "default";
pinctrl-0 = <&lcdif_16bit_pins_a
&lcdif_pins_apf28dev>;
display = <&display>;
status = "okay";
display: display {
bits-per-pixel = <16>;
bus-width = <16>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33000033>;
hactive = <800>;
vactive = <480>;
hback-porch = <96>;
hfront-porch = <96>;
vback-porch = <20>;
vfront-porch = <21>;
hsync-len = <64>;
vsync-len = <4>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
};

25
arch/arm/boot/dts/imx28-apx4devkit.dts
View File

@ -94,7 +94,32 @@
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_apx4>;
display = <&display>;
status = "okay";
display: display {
bits-per-pixel = <32>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <30000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <88>;
hfront-porch = <40>;
vback-porch = <32>;
vfront-porch = <13>;
hsync-len = <48>;
vsync-len = <3>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
};

50
arch/arm/boot/dts/imx28-cfa10049.dts
View File

@ -30,7 +30,6 @@
reg = <0>;
fsl,pinmux-ids = <
0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
0x1153 /* MX28_PAD_LCD_D22__GPIO_1_21 */
0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
@ -120,13 +119,48 @@
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
w1_gpio_pins: w1-gpio@0 {
reg = <0>;
fsl,pinmux-ids = <
0x1153 /* MX28_PAD_LCD_D21__GPIO_1_21 */
>;
fsl,drive-strength = <1>;
fsl,voltage = <1>;
fsl,pull-up = <0>; /* 0 will enable the keeper */
};
};
lcdif@80030000 {
pinctrl-names = "default";
pinctrl-0 = <&lcdif_18bit_pins_cfa10049
&lcdif_pins_cfa10049>;
display = <&display>;
status = "okay";
display: display {
bits-per-pixel = <32>;
bus-width = <18>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <9216000>;
hactive = <320>;
vactive = <480>;
hback-porch = <2>;
hfront-porch = <2>;
vback-porch = <2>;
vfront-porch = <2>;
hsync-len = <15>;
vsync-len = <15>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
};
};
@ -183,6 +217,11 @@
usbphy1: usbphy@8007e000 {
status = "okay";
};
lradc@80050000 {
status = "okay";
fsl,lradc-touchscreen-wires = <4>;
};
};
};
@ -304,5 +343,14 @@
pwms = <&pwm 3 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
onewire@0 {
compatible = "w1-gpio";
pinctrl-names = "default";
pinctrl-0 = <&w1_gpio_pins>;
status = "okay";
gpios = <&gpio1 21 0>;
};
};

36
arch/arm/boot/dts/imx28-evk.dts
View File

@ -123,8 +123,33 @@
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_evk>;
panel-enable-gpios = <&gpio3 30 0>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display>;
status = "okay";
display: display {
bits-per-pixel = <32>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33500000>;
hactive = <800>;
vactive = <480>;
hback-porch = <89>;
hfront-porch = <164>;
vback-porch = <23>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
can0: can@80032000 {
@ -285,6 +310,15 @@
gpio = <&gpio3 8 0>;
enable-active-high;
};
reg_lcd_3v3: lcd-3v3 {
compatible = "regulator-fixed";
regulator-name = "lcd-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 30 0>;
enable-active-high;
};
};
sound {

27
arch/arm/boot/dts/imx28-m28evk.dts
View File

@ -119,7 +119,32 @@
pinctrl-names = "default";
pinctrl-0 = <&lcdif_24bit_pins_a
&lcdif_pins_m28>;
display = <&display>;
status = "okay";
display: display {
bits-per-pixel = <16>;
bus-width = <18>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33260000>;
hactive = <800>;
vactive = <480>;
hback-porch = <0>;
hfront-porch = <256>;
vback-porch = <0>;
vfront-porch = <45>;
hsync-len = <1>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
};
can0: can@80032000 {
@ -220,6 +245,8 @@
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
clocks = <&clks 57>, <&clks 57>;
clock-names = "ipg", "ahb";
status = "okay";
};

62
arch/arm/boot/dts/imx28.dtsi
View File

@ -61,12 +61,24 @@
hsadc@80002000 {
reg = <0x80002000 0x2000>;
interrupts = <13 87>;
dmas = <&dma_apbh 12>;
dma-names = "rx";
status = "disabled";
};
dma-apbh@80004000 {
dma_apbh: dma-apbh@80004000 {
compatible = "fsl,imx28-dma-apbh";
reg = <0x80004000 0x2000>;
interrupts = <82 83 84 85
88 88 88 88
88 88 88 88
87 86 0 0>;
interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
"gpmi0", "gmpi1", "gpmi2", "gmpi3",
"gpmi4", "gmpi5", "gpmi6", "gmpi7",
"hsadc", "lcdif", "empty", "empty";
#dma-cells = <1>;
dma-channels = <16>;
clocks = <&clks 25>;
};
@ -86,6 +98,8 @@
interrupt-names = "gpmi-dma", "bch";
clocks = <&clks 50>;
clock-names = "gpmi_io";
dmas = <&dma_apbh 4>;
dma-names = "rx-tx";
fsl,gpmi-dma-channel = <4>;
status = "disabled";
};
@ -96,6 +110,8 @@
reg = <0x80010000 0x2000>;
interrupts = <96 82>;
clocks = <&clks 46>;
dmas = <&dma_apbh 0>;
dma-names = "rx-tx";
fsl,ssp-dma-channel = <0>;
status = "disabled";
};
@ -106,6 +122,8 @@
reg = <0x80012000 0x2000>;
interrupts = <97 83>;
clocks = <&clks 47>;
dmas = <&dma_apbh 1>;
dma-names = "rx-tx";
fsl,ssp-dma-channel = <1>;
status = "disabled";
};
@ -116,6 +134,8 @@
reg = <0x80014000 0x2000>;
interrupts = <98 84>;
clocks = <&clks 48>;
dmas = <&dma_apbh 2>;
dma-names = "rx-tx";
fsl,ssp-dma-channel = <2>;
status = "disabled";
};
@ -126,6 +146,8 @@
reg = <0x80016000 0x2000>;
interrupts = <99 85>;
clocks = <&clks 49>;
dmas = <&dma_apbh 3>;
dma-names = "rx-tx";
fsl,ssp-dma-channel = <3>;
status = "disabled";
};
@ -658,9 +680,19 @@
status = "disabled";
};
dma-apbx@80024000 {
dma_apbx: dma-apbx@80024000 {
compatible = "fsl,imx28-dma-apbx";
reg = <0x80024000 0x2000>;
interrupts = <78 79 66 0
80 81 68 69
70 71 72 73
74 75 76 77>;
interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
"saif0", "saif1", "i2c0", "i2c1",
"auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
"auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
#dma-cells = <1>;
dma-channels = <16>;
clocks = <&clks 26>;
};
@ -692,6 +724,8 @@
reg = <0x80030000 0x2000>;
interrupts = <38 86>;
clocks = <&clks 55>;
dmas = <&dma_apbh 13>;
dma-names = "rx";
status = "disabled";
};
@ -767,6 +801,8 @@
reg = <0x80042000 0x2000>;
interrupts = <59 80>;
clocks = <&clks 53>;
dmas = <&dma_apbx 4>;
dma-names = "rx-tx";
fsl,saif-dma-channel = <4>;
status = "disabled";
};
@ -781,6 +817,8 @@
reg = <0x80046000 0x2000>;
interrupts = <58 81>;
clocks = <&clks 54>;
dmas = <&dma_apbx 5>;
dma-names = "rx-tx";
fsl,saif-dma-channel = <5>;
status = "disabled";
};
@ -796,6 +834,8 @@
spdif@80054000 {
reg = <0x80054000 0x2000>;
interrupts = <45 66>;
dmas = <&dma_apbx 2>;
dma-names = "tx";
status = "disabled";
};
@ -812,6 +852,8 @@
reg = <0x80058000 0x2000>;
interrupts = <111 68>;
clock-frequency = <100000>;
dmas = <&dma_apbx 6>;
dma-names = "rx-tx";
fsl,i2c-dma-channel = <6>;
status = "disabled";
};
@ -823,6 +865,8 @@
reg = <0x8005a000 0x2000>;
interrupts = <110 69>;
clock-frequency = <100000>;
dmas = <&dma_apbx 7>;
dma-names = "rx-tx";
fsl,i2c-dma-channel = <7>;
status = "disabled";
};
@ -847,6 +891,8 @@
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006a000 0x2000>;
interrupts = <112 70 71>;
dmas = <&dma_apbx 8>, <&dma_apbx 9>;
dma-names = "rx", "tx";
fsl,auart-dma-channel = <8 9>;
clocks = <&clks 45>;
status = "disabled";
@ -856,6 +902,8 @@
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006c000 0x2000>;
interrupts = <113 72 73>;
dmas = <&dma_apbx 10>, <&dma_apbx 11>;
dma-names = "rx", "tx";
clocks = <&clks 45>;
status = "disabled";
};
@ -864,6 +912,8 @@
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x8006e000 0x2000>;
interrupts = <114 74 75>;
dmas = <&dma_apbx 12>, <&dma_apbx 13>;
dma-names = "rx", "tx";
clocks = <&clks 45>;
status = "disabled";
};
@ -872,6 +922,8 @@
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x80070000 0x2000>;
interrupts = <115 76 77>;
dmas = <&dma_apbx 14>, <&dma_apbx 15>;
dma-names = "rx", "tx";
clocks = <&clks 45>;
status = "disabled";
};
@ -880,6 +932,8 @@
compatible = "fsl,imx28-auart", "fsl,imx23-auart";
reg = <0x80072000 0x2000>;
interrupts = <116 78 79>;
dmas = <&dma_apbx 0>, <&dma_apbx 1>;
dma-names = "rx", "tx";
clocks = <&clks 45>;
status = "disabled";
};
@ -943,8 +997,8 @@
compatible = "fsl,imx28-fec";
reg = <0x800f0000 0x4000>;
interrupts = <101>;
clocks = <&clks 57>, <&clks 57>;
clock-names = "ipg", "ahb";
clocks = <&clks 57>, <&clks 57>, <&clks 64>;
clock-names = "ipg", "ahb", "enet_out";
status = "disabled";
};

8
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -65,9 +65,13 @@
interrupt-parent = <&intc>;
ranges;
dma-apbh@00110000 {
dma_apbh: dma-apbh@00110000 {
compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x00110000 0x2000>;
interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clks 106>;
};
@ -83,6 +87,8 @@
<&clks 150>, <&clks 149>;
clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
"gpmi_bch_apb", "per1_bch";
dmas = <&dma_apbh 0>;
dma-names = "rx-tx";
fsl,gpmi-dma-channel = <0>;
status = "disabled";
};

39
arch/arm/boot/dts/omap2.dtsi
View File

@ -26,6 +26,11 @@
};
};
pmu {
compatible = "arm,arm1136-pmu";
interrupts = <3>;
};
soc {
compatible = "ti,omap-infra";
mpu {
@ -49,6 +54,18 @@
reg = <0x480FE000 0x1000>;
};
sdma: dma-controller@48056000 {
compatible = "ti,omap2430-sdma", "ti,omap2420-sdma";
reg = <0x48056000 0x1000>;
interrupts = <12>,
<13>,
<14>,
<15>;
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <64>;
};
uart1: serial@4806a000 {
compatible = "ti,omap2-uart";
ti,hwmods = "uart1";
@ -68,28 +85,28 @@
};
timer2: timer@4802a000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap2420-timer";
reg = <0x4802a000 0x400>;
interrupts = <38>;
ti,hwmods = "timer2";
};
timer3: timer@48078000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap2420-timer";
reg = <0x48078000 0x400>;
interrupts = <39>;
ti,hwmods = "timer3";
};
timer4: timer@4807a000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap2420-timer";
reg = <0x4807a000 0x400>;
interrupts = <40>;
ti,hwmods = "timer4";
};
timer5: timer@4807c000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap2420-timer";
reg = <0x4807c000 0x400>;
interrupts = <41>;
ti,hwmods = "timer5";
@ -97,7 +114,7 @@
};
timer6: timer@4807e000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap2420-timer";
reg = <0x4807e000 0x400>;
interrupts = <42>;
ti,hwmods = "timer6";
@ -105,7 +122,7 @@
};
timer7: timer@48080000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap2420-timer";
reg = <0x48080000 0x400>;
interrupts = <43>;
ti,hwmods = "timer7";
@ -113,7 +130,7 @@
};
timer8: timer@48082000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap2420-timer";
reg = <0x48082000 0x400>;
interrupts = <44>;
ti,hwmods = "timer8";
@ -121,7 +138,7 @@
};
timer9: timer@48084000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap2420-timer";
reg = <0x48084000 0x400>;
interrupts = <45>;
ti,hwmods = "timer9";
@ -129,7 +146,7 @@
};
timer10: timer@48086000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap2420-timer";
reg = <0x48086000 0x400>;
interrupts = <46>;
ti,hwmods = "timer10";
@ -137,7 +154,7 @@
};
timer11: timer@48088000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap2420-timer";
reg = <0x48088000 0x400>;
interrupts = <47>;
ti,hwmods = "timer11";
@ -145,7 +162,7 @@
};
timer12: timer@4808a000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap2420-timer";
reg = <0x4808a000 0x400>;
interrupts = <48>;
ti,hwmods = "timer12";

46
arch/arm/boot/dts/omap2420-h4.dts
View File

@ -18,3 +18,49 @@
reg = <0x80000000 0x4000000>; /* 64 MB */
};
};
&gpmc {
ranges = <0 0 0x08000000 0x04000000>;
nor@0,0 {
compatible = "cfi-flash";
linux,mtd-name= "intel,ge28f256l18b85";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x04000000>;
bank-width = <2>;
gpmc,mux-add-data = <2>;
gpmc,cs-on-ns = <10>;
gpmc,cs-rd-off-ns = <160>;
gpmc,cs-wr-off-ns = <160>;
gpmc,adv-on-ns = <20>;
gpmc,adv-rd-off-ns = <50>;
gpmc,adv-wr-off-ns = <50>;
gpmc,oe-on-ns = <60>;
gpmc,oe-off-ns = <120>;
gpmc,we-on-ns = <60>;
gpmc,we-off-ns = <120>;
gpmc,rd-cycle-ns = <170>;
gpmc,wr-cycle-ns = <170>;
gpmc,access-ns = <150>;
gpmc,page-burst-access-ns = <10>;
partition@0 {
label = "bootloader";
reg = <0 0x20000>;
};
partition@0x20000 {
label = "params";
reg = <0x20000 0x20000>;
};
partition@0x40000 {
label = "kernel";
reg = <0x40000 0x200000>;
};
partition@0x240000 {
label = "file-system";
reg = <0x240000 0x3dc0000>;
};
};
};

67
arch/arm/boot/dts/omap2420.dtsi
View File

@ -29,6 +29,65 @@
pinctrl-single,function-mask = <0x3f>;
};
gpio1: gpio@48018000 {
compatible = "ti,omap2-gpio";
reg = <0x48018000 0x200>;
interrupts = <29>;
ti,hwmods = "gpio1";
ti,gpio-always-on;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
gpio2: gpio@4801a000 {
compatible = "ti,omap2-gpio";
reg = <0x4801a000 0x200>;
interrupts = <30>;
ti,hwmods = "gpio2";
ti,gpio-always-on;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
gpio3: gpio@4801c000 {
compatible = "ti,omap2-gpio";
reg = <0x4801c000 0x200>;
interrupts = <31>;
ti,hwmods = "gpio3";
ti,gpio-always-on;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
gpio4: gpio@4801e000 {
compatible = "ti,omap2-gpio";
reg = <0x4801e000 0x200>;
interrupts = <32>;
ti,hwmods = "gpio4";
ti,gpio-always-on;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
gpmc: gpmc@6800a000 {
compatible = "ti,omap2420-gpmc";
reg = <0x6800a000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
interrupts = <20>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
ti,hwmods = "gpmc";
};
mcbsp1: mcbsp@48074000 {
compatible = "ti,omap2420-mcbsp";
reg = <0x48074000 0xff>;
@ -37,6 +96,9 @@
<60>; /* RX interrupt */
interrupt-names = "tx", "rx";
ti,hwmods = "mcbsp1";
dmas = <&sdma 31>,
<&sdma 32>;
dma-names = "tx", "rx";
};
mcbsp2: mcbsp@48076000 {
@ -47,10 +109,13 @@
<63>; /* RX interrupt */
interrupt-names = "tx", "rx";
ti,hwmods = "mcbsp2";
dmas = <&sdma 33>,
<&sdma 34>;
dma-names = "tx", "rx";
};
timer1: timer@48028000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap2420-timer";
reg = <0x48028000 0x400>;
interrupts = <37>;
ti,hwmods = "timer1";

87
arch/arm/boot/dts/omap2430.dtsi
View File

@ -29,6 +29,76 @@
pinctrl-single,function-mask = <0x3f>;
};
gpio1: gpio@4900c000 {
compatible = "ti,omap2-gpio";
reg = <0x4900c000 0x200>;
interrupts = <29>;
ti,hwmods = "gpio1";
ti,gpio-always-on;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
gpio2: gpio@4900e000 {
compatible = "ti,omap2-gpio";
reg = <0x4900e000 0x200>;
interrupts = <30>;
ti,hwmods = "gpio2";
ti,gpio-always-on;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
gpio3: gpio@49010000 {
compatible = "ti,omap2-gpio";
reg = <0x49010000 0x200>;
interrupts = <31>;
ti,hwmods = "gpio3";
ti,gpio-always-on;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
gpio4: gpio@49012000 {
compatible = "ti,omap2-gpio";
reg = <0x49012000 0x200>;
interrupts = <32>;
ti,hwmods = "gpio4";
ti,gpio-always-on;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
gpio5: gpio@480b6000 {
compatible = "ti,omap2-gpio";
reg = <0x480b6000 0x200>;
interrupts = <33>;
ti,hwmods = "gpio5";
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
interrupt-controller;
};
gpmc: gpmc@6e000000 {
compatible = "ti,omap2430-gpmc";
reg = <0x6e000000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
interrupts = <20>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
ti,hwmods = "gpmc";
};
mcbsp1: mcbsp@48074000 {
compatible = "ti,omap2430-mcbsp";
reg = <0x48074000 0xff>;
@ -40,6 +110,9 @@
interrupt-names = "common", "tx", "rx", "rx_overflow";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp1";
dmas = <&sdma 31>,
<&sdma 32>;
dma-names = "tx", "rx";
};
mcbsp2: mcbsp@48076000 {
@ -52,6 +125,9 @@
interrupt-names = "common", "tx", "rx";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp2";
dmas = <&sdma 33>,
<&sdma 34>;
dma-names = "tx", "rx";
};
mcbsp3: mcbsp@4808c000 {
@ -64,6 +140,9 @@
interrupt-names = "common", "tx", "rx";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp3";
dmas = <&sdma 17>,
<&sdma 18>;
dma-names = "tx", "rx";
};
mcbsp4: mcbsp@4808e000 {
@ -76,6 +155,9 @@
interrupt-names = "common", "tx", "rx";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp4";
dmas = <&sdma 19>,
<&sdma 20>;
dma-names = "tx", "rx";
};
mcbsp5: mcbsp@48096000 {
@ -88,10 +170,13 @@
interrupt-names = "common", "tx", "rx";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp5";
dmas = <&sdma 21>,
<&sdma 22>;
dma-names = "tx", "rx";
};
timer1: timer@49018000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap2420-timer";
reg = <0x49018000 0x400>;
interrupts = <37>;
ti,hwmods = "timer1";

26
arch/arm/boot/dts/omap3-beagle-xm.dts
View File

@ -13,6 +13,12 @@
model = "TI OMAP3 BeagleBoard xM";
compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3";
cpus {
cpu@0 {
cpu0-supply = <&vcc>;
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
@ -20,10 +26,6 @@
leds {
compatible = "gpio-leds";
pmu_stat {
label = "beagleboard::pmu_stat";
gpios = <&twl_gpio 19 0>; /* LEDB */
};
heartbeat {
label = "beagleboard::usr0";
@ -38,6 +40,16 @@
};
};
pwmleds {
compatible = "pwm-leds";
pmu_stat {
label = "beagleboard::pmu_stat";
pwms = <&twl_pwmled 1 7812500>;
max-brightness = <127>;
};
};
sound {
compatible = "ti,omap-twl4030";
ti,model = "omap3beagle";
@ -107,3 +119,9 @@
*/
ti,pulldowns = <0x03a1c4>;
};
&usb_otg_hs {
interface-type = <0>;
mode = <3>;
power = <50>;
};

8
arch/arm/boot/dts/omap3-beagle.dts
View File

@ -7,12 +7,18 @@
*/
/dts-v1/;
/include/ "omap3.dtsi"
/include/ "omap34xx.dtsi"
/ {
model = "TI OMAP3 BeagleBoard";
compatible = "ti,omap3-beagle", "ti,omap3";
cpus {
cpu@0 {
cpu0-supply = <&vcc>;
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */

169
arch/arm/boot/dts/omap3-devkit8000.dts Normal file
View File

@ -0,0 +1,169 @@
/*
* Author: Anil Kumar <anilk4.v@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/include/ "omap34xx.dtsi"
/ {
model = "TimLL OMAP3 Devkit8000";
compatible = "timll,omap3-devkit8000", "ti,omap3";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
leds {
compatible = "gpio-leds";
heartbeat {
label = "devkit8000::led1";
gpios = <&gpio6 26 0>; /* 186 -> LED1 */
default-state = "on";
linux,default-trigger = "heartbeat";
};
mmc {
label = "devkit8000::led2";
gpios = <&gpio6 3 0>; /* 163 -> LED2 */
default-state = "on";
linux,default-trigger = "none";
};
usr {
label = "devkit8000::led3";
gpios = <&gpio6 4 0>; /* 164 -> LED3 */
default-state = "on";
linux,default-trigger = "usr";
};
};
sound {
compatible = "ti,omap-twl4030";
ti,model = "devkit8000";
ti,mcbsp = <&mcbsp2>;
ti,codec = <&twl_audio>;
ti,audio-routing =
"Ext Spk", "PREDRIVEL",
"Ext Spk", "PREDRIVER",
"MAINMIC", "Main Mic",
"Main Mic", "Mic Bias 1";
};
};
&i2c1 {
clock-frequency = <2600000>;
twl: twl@48 {
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
twl_audio: audio {
compatible = "ti,twl4030-audio";
codec {
};
};
};
};
&i2c2 {
status = "disabled";
};
&i2c3 {
status = "disabled";
};
/include/ "twl4030.dtsi"
&mmc1 {
vmmc-supply = <&vmmc1>;
vmmc_aux-supply = <&vsim>;
bus-width = <8>;
};
&mmc2 {
status = "disabled";
};
&mmc3 {
status = "disabled";
};
&wdt2 {
status = "disabled";
};
&mcbsp1 {
status = "disabled";
};
&mcbsp3 {
status = "disabled";
};
&mcbsp4 {
status = "disabled";
};
&mcbsp5 {
status = "disabled";
};
&gpmc {
ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */
nand@0,0 {
reg = <0 0 0>; /* CS0, offset 0 */
nand-bus-width = <16>;
gpmc,sync-clk = <0>;
gpmc,cs-on = <0>;
gpmc,cs-rd-off = <44>;
gpmc,cs-wr-off = <44>;
gpmc,adv-on = <6>;
gpmc,adv-rd-off = <34>;
gpmc,adv-wr-off = <44>;
gpmc,we-off = <40>;
gpmc,oe-off = <54>;
gpmc,access = <64>;
gpmc,rd-cycle = <82>;
gpmc,wr-cycle = <82>;
gpmc,wr-access = <40>;
gpmc,wr-data-mux-bus = <0>;
#address-cells = <1>;
#size-cells = <1>;
x-loader@0 {
label = "X-Loader";
reg = <0 0x80000>;
};
bootloaders@80000 {
label = "U-Boot";
reg = <0x80000 0x1e0000>;
};
bootloaders_env@260000 {
label = "U-Boot Env";
reg = <0x260000 0x20000>;
};
kernel@280000 {
label = "Kernel";
reg = <0x280000 0x400000>;
};
filesystem@680000 {
label = "File System";
reg = <0x680000 0xf980000>;
};
};
};

14
arch/arm/boot/dts/omap3-evm.dts
View File

@ -7,12 +7,18 @@
*/
/dts-v1/;
/include/ "omap3.dtsi"
/include/ "omap34xx.dtsi"
/ {
model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)";
compatible = "ti,omap3-evm", "ti,omap3";
cpus {
cpu@0 {
cpu0-supply = <&vcc>;
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
@ -59,3 +65,9 @@
&twl_gpio {
ti,use-leds;
};
&usb_otg_hs {
interface-type = <0>;
mode = <3>;
power = <50>;
};

122
arch/arm/boot/dts/omap3-igep.dtsi Normal file
View File

@ -0,0 +1,122 @@
/*
* Device Tree Source for IGEP Technology devices
*
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/include/ "omap34xx.dtsi"
/ {
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512 MB */
};
sound {
compatible = "ti,omap-twl4030";
ti,model = "igep2";
ti,mcbsp = <&mcbsp2>;
ti,codec = <&twl_audio>;
};
};
&omap3_pmx_core {
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
0x152 0x100 /* uart1_rx.uart1_rx INPUT | MODE0 */
0x14c 0 /* uart1_tx.uart1_tx OUTPUT | MODE0 */
>;
};
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
0x14a 0x100 /* uart2_rx.uart2_rx INPUT | MODE0 */
0x148 0 /* uart2_tx.uart2_tx OUTPUT | MODE0 */
>;
};
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
0x16e 0x100 /* uart3_rx.uart3_rx INPUT | MODE0 */
0x170 0 /* uart3_tx.uart3_tx OUTPUT | MODE0 */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
0x114 0x0118 /* sdmmc1_clk.sdmmc1_clk INPUT PULLUP | MODE 0 */
0x116 0x0118 /* sdmmc1_cmd.sdmmc1_cmd INPUT PULLUP | MODE 0 */
0x118 0x0118 /* sdmmc1_dat0.sdmmc1_dat0 INPUT PULLUP | MODE 0 */
0x11a 0x0118 /* sdmmc1_dat1.sdmmc1_dat1 INPUT PULLUP | MODE 0 */
0x11c 0x0118 /* sdmmc1_dat2.sdmmc1_dat2 INPUT PULLUP | MODE 0 */
0x11e 0x0118 /* sdmmc1_dat3.sdmmc1_dat3 INPUT PULLUP | MODE 0 */
0x120 0x0100 /* sdmmc1_dat4.sdmmc1_dat4 INPUT | MODE 0 */
0x122 0x0100 /* sdmmc1_dat5.sdmmc1_dat5 INPUT | MODE 0 */
0x124 0x0100 /* sdmmc1_dat6.sdmmc1_dat6 INPUT | MODE 0 */
0x126 0x0100 /* sdmmc1_dat7.sdmmc1_dat7 INPUT | MODE 0 */
>;
};
};
&i2c1 {
clock-frequency = <2600000>;
twl: twl@48 {
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>;
twl_audio: audio {
compatible = "ti,twl4030-audio";
codec {
};
};
};
};
/include/ "twl4030.dtsi"
&i2c2 {
clock-frequency = <400000>;
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
vmmc-supply = <&vmmc1>;
vmmc_aux-supply = <&vsim>;
bus-width = <8>;
};
&mmc2 {
status = "disabled";
};
&mmc3 {
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
};
&twl_gpio {
ti,use-leds;
};

56
arch/arm/boot/dts/omap3-igep0020.dts Normal file
View File

@ -0,0 +1,56 @@
/*
* Device Tree Source for IGEPv2 board
*
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/include/ "omap3-igep.dtsi"
/ {
model = "IGEPv2";
compatible = "isee,omap3-igep0020", "ti,omap3";
leds {
compatible = "gpio-leds";
boot {
label = "omap3:green:boot";
gpios = <&gpio1 26 0>;
default-state = "on";
};
user0 {
label = "omap3:red:user0";
gpios = <&gpio1 27 0>;
default-state = "off";
};
user1 {
label = "omap3:red:user1";
gpios = <&gpio1 28 0>;
default-state = "off";
};
user2 {
label = "omap3:green:user1";
gpios = <&twl_gpio 19 1>;
};
};
};
&i2c3 {
clock-frequency = <100000>;
/*
* Display monitor features are burnt in the EEPROM
* as EDID data.
*/
eeprom@50 {
compatible = "ti,eeprom";
reg = <0x50>;
};
};

44
arch/arm/boot/dts/omap3-igep0030.dts Normal file
View File

@ -0,0 +1,44 @@
/*
* Device Tree Source for IGEP COM Module
*
* Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk>
* Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/include/ "omap3-igep.dtsi"
/ {
model = "IGEP COM Module";
compatible = "isee,omap3-igep0030", "ti,omap3";
leds {
compatible = "gpio-leds";
boot {
label = "omap3:green:boot";
gpios = <&twl_gpio 13 1>;
default-state = "on";
};
user0 {
label = "omap3:red:user0";
gpios = <&twl_gpio 18 1>; /* LEDA */
default-state = "off";
};
user1 {
label = "omap3:green:user1";
gpios = <&twl_gpio 19 1>; /* LEDB */
default-state = "off";
};
user2 {
label = "omap3:red:user1";
gpios = <&gpio1 16 1>;
default-state = "off";
};
};
};

31
arch/arm/boot/dts/omap3-overo.dtsi
View File

@ -11,17 +11,26 @@
*/
/dts-v1/;
/include/ "omap3.dtsi"
/include/ "omap34xx.dtsi"
/ {
leds {
compatible = "gpio-leds";
pwmleds {
compatible = "pwm-leds";
overo {
label = "overo:blue:COM";
gpios = <&twl_gpio 19 0>;
linux,default-trigger = "mmc0";
pwms = <&twl_pwmled 1 7812500>;
max-brightness = <127>;
};
};
sound {
compatible = "ti,omap-twl4030";
ti,model = "overo";
ti,mcbsp = <&mcbsp2>;
ti,codec = <&twl_audio>;
};
};
&i2c1 {
@ -31,6 +40,12 @@
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
interrupt-parent = <&intc>;
twl_audio: audio {
compatible = "ti,twl4030-audio";
codec {
};
};
};
};
@ -55,3 +70,9 @@
&twl_gpio {
ti,use-leds;
};
&usb_otg_hs {
interface-type = <0>;
mode = <3>;
power = <50>;
};

142
arch/arm/boot/dts/omap3.dtsi
View File

@ -26,8 +26,14 @@
};
};
pmu {
compatible = "arm,cortex-a8-pmu";
interrupts = <3>;
ti,hwmods = "debugss";
};
/*
* The soc node represents the soc top level view. It is uses for IPs
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
*/
soc {
@ -75,76 +81,101 @@
reg = <0x48200000 0x1000>;
};
sdma: dma-controller@48056000 {
compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
reg = <0x48056000 0x1000>;
interrupts = <12>,
<13>,
<14>,
<15>;
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <96>;
};
omap3_pmx_core: pinmux@48002030 {
compatible = "ti,omap3-padconf", "pinctrl-single";
reg = <0x48002030 0x05cc>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
pinctrl-single,function-mask = <0x7f1f>;
};
omap3_pmx_wkup: pinmux@0x48002a58 {
omap3_pmx_wkup: pinmux@0x48002a00 {
compatible = "ti,omap3-padconf", "pinctrl-single";
reg = <0x48002a58 0x5c>;
reg = <0x48002a00 0x5c>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
pinctrl-single,function-mask = <0x7f1f>;
};
gpio1: gpio@48310000 {
compatible = "ti,omap3-gpio";
reg = <0x48310000 0x200>;
interrupts = <29>;
ti,hwmods = "gpio1";
ti,gpio-always-on;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio2: gpio@49050000 {
compatible = "ti,omap3-gpio";
reg = <0x49050000 0x200>;
interrupts = <30>;
ti,hwmods = "gpio2";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio3: gpio@49052000 {
compatible = "ti,omap3-gpio";
reg = <0x49052000 0x200>;
interrupts = <31>;
ti,hwmods = "gpio3";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio4: gpio@49054000 {
compatible = "ti,omap3-gpio";
reg = <0x49054000 0x200>;
interrupts = <32>;
ti,hwmods = "gpio4";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio5: gpio@49056000 {
compatible = "ti,omap3-gpio";
reg = <0x49056000 0x200>;
interrupts = <33>;
ti,hwmods = "gpio5";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio6: gpio@49058000 {
compatible = "ti,omap3-gpio";
reg = <0x49058000 0x200>;
interrupts = <34>;
ti,hwmods = "gpio6";
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
uart1: serial@4806a000 {
@ -192,6 +223,16 @@
#size-cells = <0>;
ti,hwmods = "mcspi1";
ti,spi-num-cs = <4>;
dmas = <&sdma 35>,
<&sdma 36>,
<&sdma 37>,
<&sdma 38>,
<&sdma 39>,
<&sdma 40>,
<&sdma 41>,
<&sdma 42>;
dma-names = "tx0", "rx0", "tx1", "rx1",
"tx2", "rx2", "tx3", "rx3";
};
mcspi2: spi@4809a000 {
@ -200,6 +241,11 @@
#size-cells = <0>;
ti,hwmods = "mcspi2";
ti,spi-num-cs = <2>;
dmas = <&sdma 43>,
<&sdma 44>,
<&sdma 45>,
<&sdma 46>;
dma-names = "tx0", "rx0", "tx1", "rx1";
};
mcspi3: spi@480b8000 {
@ -208,6 +254,11 @@
#size-cells = <0>;
ti,hwmods = "mcspi3";
ti,spi-num-cs = <2>;
dmas = <&sdma 15>,
<&sdma 16>,
<&sdma 23>,
<&sdma 24>;
dma-names = "tx0", "rx0", "tx1", "rx1";
};
mcspi4: spi@480ba000 {
@ -216,22 +267,30 @@
#size-cells = <0>;
ti,hwmods = "mcspi4";
ti,spi-num-cs = <1>;
dmas = <&sdma 70>, <&sdma 71>;
dma-names = "tx0", "rx0";
};
mmc1: mmc@4809c000 {
compatible = "ti,omap3-hsmmc";
ti,hwmods = "mmc1";
ti,dual-volt;
dmas = <&sdma 61>, <&sdma 62>;
dma-names = "tx", "rx";
};
mmc2: mmc@480b4000 {
compatible = "ti,omap3-hsmmc";
ti,hwmods = "mmc2";
dmas = <&sdma 47>, <&sdma 48>;
dma-names = "tx", "rx";
};
mmc3: mmc@480ad000 {
compatible = "ti,omap3-hsmmc";
ti,hwmods = "mmc3";
dmas = <&sdma 77>, <&sdma 78>;
dma-names = "tx", "rx";
};
wdt2: wdt@48314000 {
@ -249,6 +308,9 @@
interrupt-names = "common", "tx", "rx";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp1";
dmas = <&sdma 31>,
<&sdma 32>;
dma-names = "tx", "rx";
};
mcbsp2: mcbsp@49022000 {
@ -263,6 +325,9 @@
interrupt-names = "common", "tx", "rx", "sidetone";
ti,buffer-size = <1280>;
ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
dmas = <&sdma 33>,
<&sdma 34>;
dma-names = "tx", "rx";
};
mcbsp3: mcbsp@49024000 {
@ -277,6 +342,9 @@
interrupt-names = "common", "tx", "rx", "sidetone";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
dmas = <&sdma 17>,
<&sdma 18>;
dma-names = "tx", "rx";
};
mcbsp4: mcbsp@49026000 {
@ -289,6 +357,9 @@
interrupt-names = "common", "tx", "rx";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp4";
dmas = <&sdma 19>,
<&sdma 20>;
dma-names = "tx", "rx";
};
mcbsp5: mcbsp@48096000 {
@ -301,10 +372,13 @@
interrupt-names = "common", "tx", "rx";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp5";
dmas = <&sdma 21>,
<&sdma 22>;
dma-names = "tx", "rx";
};
timer1: timer@48318000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x48318000 0x400>;
interrupts = <37>;
ti,hwmods = "timer1";
@ -312,28 +386,28 @@
};
timer2: timer@49032000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x49032000 0x400>;
interrupts = <38>;
ti,hwmods = "timer2";
};
timer3: timer@49034000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x49034000 0x400>;
interrupts = <39>;
ti,hwmods = "timer3";
};
timer4: timer@49036000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x49036000 0x400>;
interrupts = <40>;
ti,hwmods = "timer4";
};
timer5: timer@49038000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x49038000 0x400>;
interrupts = <41>;
ti,hwmods = "timer5";
@ -341,7 +415,7 @@
};
timer6: timer@4903a000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x4903a000 0x400>;
interrupts = <42>;
ti,hwmods = "timer6";
@ -349,7 +423,7 @@
};
timer7: timer@4903c000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x4903c000 0x400>;
interrupts = <43>;
ti,hwmods = "timer7";
@ -357,7 +431,7 @@
};
timer8: timer@4903e000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x4903e000 0x400>;
interrupts = <44>;
ti,hwmods = "timer8";
@ -366,7 +440,7 @@
};
timer9: timer@49040000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x49040000 0x400>;
interrupts = <45>;
ti,hwmods = "timer9";
@ -374,7 +448,7 @@
};
timer10: timer@48086000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x48086000 0x400>;
interrupts = <46>;
ti,hwmods = "timer10";
@ -382,7 +456,7 @@
};
timer11: timer@48088000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x48088000 0x400>;
interrupts = <47>;
ti,hwmods = "timer11";
@ -390,7 +464,7 @@
};
timer12: timer@48304000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x48304000 0x400>;
interrupts = <95>;
ti,hwmods = "timer12";
@ -428,5 +502,27 @@
};
};
gpmc: gpmc@6e000000 {
compatible = "ti,omap3430-gpmc";
ti,hwmods = "gpmc";
reg = <0x6e000000 0x02d0>;
interrupts = <20>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
#address-cells = <2>;
#size-cells = <1>;
};
usb_otg_hs: usb_otg_hs@480ab000 {
compatible = "ti,omap3-musb";
reg = <0x480ab000 0x1000>;
interrupts = <0 92 0x4>, <0 93 0x4>;
interrupt-names = "mc", "dma";
ti,hwmods = "usb_otg_hs";
usb-phy = <&usb2_phy>;
multipoint = <1>;
num-eps = <16>;
ram-bits = <12>;
};
};
};

190
arch/arm/boot/dts/omap3430-sdp.dts Normal file
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@ -0,0 +1,190 @@
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/include/ "omap34xx.dtsi"
/ {
model = "TI OMAP3430 SDP";
compatible = "ti,omap3430-sdp", "ti,omap3";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
};
&i2c1 {
clock-frequency = <2600000>;
twl: twl@48 {
reg = <0x48>;
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
};
};
/include/ "twl4030.dtsi"
&mmc1 {
vmmc-supply = <&vmmc1>;
vmmc_aux-supply = <&vsim>;
bus-width = <8>;
};
&mmc2 {
status = "disabled";
};
&mmc3 {
status = "disabled";
};
&gpmc {
ranges = <0 0 0x10000000 0x08000000>,
<1 0 0x28000000 0x08000000>,
<2 0 0x20000000 0x10000000>;
nor@0,0 {
compatible = "cfi-flash";
linux,mtd-name= "intel,pf48f6000m0y1be";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x08000000>;
bank-width = <2>;
gpmc,mux-add-data = <2>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <186>;
gpmc,cs-wr-off-ns = <186>;
gpmc,adv-on-ns = <12>;
gpmc,adv-rd-off-ns = <48>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>;
gpmc,page-burst-access-ns = <6>;
gpmc,bus-turnaround-ns = <12>;
gpmc,cycle2cycle-delay-ns = <18>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
partition@0 {
label = "bootloader-nor";
reg = <0 0x40000>;
};
partition@0x40000 {
label = "params-nor";
reg = <0x40000 0x40000>;
};
partition@0x80000 {
label = "kernel-nor";
reg = <0x80000 0x200000>;
};
partition@0x280000 {
label = "filesystem-nor";
reg = <0x240000 0x7d80000>;
};
};
nand@1,0 {
linux,mtd-name= "micron,mt29f1g08abb";
#address-cells = <1>;
#size-cells = <1>;
reg = <1 0 0x08000000>;
nand-bus-width = <8>;
ti,nand-ecc-opt = "sw";
gpmc,device-nand;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <36>;
gpmc,cs-wr-off-ns = <36>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <24>;
gpmc,adv-wr-off-ns = <36>;
gpmc,oe-on-ns = <6>;
gpmc,oe-off-ns = <48>;
gpmc,we-on-ns = <6>;
gpmc,we-off-ns = <30>;
gpmc,rd-cycle-ns = <72>;
gpmc,wr-cycle-ns = <72>;
gpmc,access-ns = <54>;
gpmc,wr-access-ns = <30>;
partition@0 {
label = "xloader-nand";
reg = <0 0x80000>;
};
partition@0x80000 {
label = "bootloader-nand";
reg = <0x80000 0x140000>;
};
partition@0x1c0000 {
label = "params-nand";
reg = <0x1c0000 0xc0000>;
};
partition@0x280000 {
label = "kernel-nand";
reg = <0x280000 0x500000>;
};
partition@0x780000 {
label = "filesystem-nand";
reg = <0x780000 0x7880000>;
};
};
onenand@2,0 {
linux,mtd-name= "samsung,kfm2g16q2m-deb8";
#address-cells = <1>;
#size-cells = <1>;
reg = <2 0 0x10000000>;
gpmc,device-width = <2>;
gpmc,mux-add-data = <2>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <84>;
gpmc,cs-wr-off-ns = <72>;
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <18>;
gpmc,adv-wr-off-ns = <18>;
gpmc,oe-on-ns = <30>;
gpmc,oe-off-ns = <84>;
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <42>;
gpmc,rd-cycle-ns = <108>;
gpmc,wr-cycle-ns = <96>;
gpmc,access-ns = <78>;
gpmc,wr-data-mux-bus-ns = <30>;
partition@0 {
label = "xloader-onenand";
reg = <0 0x80000>;
};
partition@0x80000 {
label = "bootloader-onenand";
reg = <0x80000 0x40000>;
};
partition@0xc0000 {
label = "params-onenand";
reg = <0xc0000 0x20000>;
};
partition@0xe0000 {
label = "kernel-onenand";
reg = <0xe0000 0x200000>;
};
partition@0x2e0000 {
label = "filesystem-onenand";
reg = <0x2e0000 0xfd20000>;
};
};
};

28
arch/arm/boot/dts/omap34xx.dtsi Normal file
View File

@ -0,0 +1,28 @@
/*
* Device Tree Source for OMAP34xx/OMAP35xx SoC
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "omap3.dtsi"
/ {
cpus {
cpu@0 {
/* OMAP343x/OMAP35xx variants OPP1-5 */
operating-points = <
/* kHz uV */
125000 975000
250000 1075000
500000 1200000
550000 1270000
600000 1350000
>;
clock-latency = <300000>; /* From legacy driver */
};
};
};

13
arch/arm/boot/dts/omap36xx.dtsi
View File

@ -15,6 +15,19 @@
serial3 = &uart4;
};
cpus {
/* OMAP3630/OMAP37xx 'standard device' variants OPP50 to OPP130 */
cpu@0 {
operating-points = <
/* kHz uV */
300000 975000
600000 1075000
800000 1200000
>;
clock-latency = <300000>; /* From legacy driver */
};
};
ocp {
uart4: serial@49042000 {
compatible = "ti,omap3-uart";

5
arch/arm/boot/dts/omap4-panda-a4.dts
View File

@ -5,7 +5,10 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/include/ "omap4-panda.dts"
/dts-v1/;
/include/ "omap443x.dtsi"
/include/ "omap4-panda-common.dtsi"
/* Pandaboard Rev A4+ have external pullups on SCL & SDA */
&dss_hdmi_pins {

251
arch/arm/boot/dts/omap4-panda-common.dtsi Normal file
View File

@ -0,0 +1,251 @@
/*
* Copyright (C) 2011-2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/include/ "elpida_ecb240abacn.dtsi"
/ {
model = "TI OMAP4 PandaBoard";
compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
leds {
compatible = "gpio-leds";
heartbeat {
label = "pandaboard::status1";
gpios = <&gpio1 7 0>;
linux,default-trigger = "heartbeat";
};
mmc {
label = "pandaboard::status2";
gpios = <&gpio1 8 0>;
linux,default-trigger = "mmc0";
};
};
sound: sound {
compatible = "ti,abe-twl6040";
ti,model = "PandaBoard";
ti,mclk-freq = <38400000>;
ti,mcpdm = <&mcpdm>;
ti,twl6040 = <&twl6040>;
/* Audio routing */
ti,audio-routing =
"Headset Stereophone", "HSOL",
"Headset Stereophone", "HSOR",
"Ext Spk", "HFL",
"Ext Spk", "HFR",
"Line Out", "AUXL",
"Line Out", "AUXR",
"HSMIC", "Headset Mic",
"Headset Mic", "Headset Mic Bias",
"AFML", "Line In",
"AFMR", "Line In";
};
};
&omap4_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&twl6040_pins
&mcpdm_pins
&mcbsp1_pins
&dss_hdmi_pins
&tpd12s015_pins
>;
twl6040_pins: pinmux_twl6040_pins {
pinctrl-single,pins = <
0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */
0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
>;
};
mcpdm_pins: pinmux_mcpdm_pins {
pinctrl-single,pins = <
0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
>;
};
mcbsp1_pins: pinmux_mcbsp1_pins {
pinctrl-single,pins = <
0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
>;
};
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
>;
};
tpd12s015_pins: pinmux_tpd12s015_pins {
pinctrl-single,pins = <
0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0xe2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
0xe4 0x118 /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
0xe6 0x118 /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
0xe8 0x118 /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
0xea 0x118 /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
0xec 0x118 /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
>;
};
i2c4_pins: pinmux_i2c4_pins {
pinctrl-single,pins = <
0xee 0x118 /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
0xf0 0x118 /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
twl: twl@48 {
reg = <0x48>;
/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
interrupt-parent = <&gic>;
};
twl6040: twl@4b {
compatible = "ti,twl6040";
reg = <0x4b>;
/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
interrupt-parent = <&gic>;
ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */
vio-supply = <&v1v8>;
v2v1-supply = <&v2v1>;
enable-active-high;
};
};
/include/ "twl6030.dtsi"
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <100000>;
/*
* Display monitor features are burnt in their EEPROM as EDID data.
* The EEPROM is connected as I2C slave device.
*/
eeprom@50 {
compatible = "ti,eeprom";
reg = <0x50>;
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
clock-frequency = <400000>;
};
&mmc1 {
vmmc-supply = <&vmmc>;
bus-width = <8>;
};
&mmc2 {
status = "disabled";
};
&mmc3 {
status = "disabled";
};
&mmc4 {
status = "disabled";
};
&mmc5 {
ti,non-removable;
bus-width = <4>;
};
&emif1 {
cs1-used;
device-handle = <&elpida_ECB240ABACN>;
};
&emif2 {
cs1-used;
device-handle = <&elpida_ECB240ABACN>;
};
&mcbsp2 {
status = "disabled";
};
&mcbsp3 {
status = "disabled";
};
&dmic {
status = "disabled";
};
&twl_usb_comparator {
usb-supply = <&vusb>;
};
&usb_otg_hs {
interface-type = <1>;
mode = <3>;
power = <50>;
};

5
arch/arm/boot/dts/omap4-panda-es.dts
View File

@ -5,7 +5,10 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/include/ "omap4-panda.dts"
/dts-v1/;
/include/ "omap4460.dtsi"
/include/ "omap4-panda-common.dtsi"
/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
&sound {

201
arch/arm/boot/dts/omap4-panda.dts
View File

@ -7,202 +7,5 @@
*/
/dts-v1/;
/include/ "omap4.dtsi"
/include/ "elpida_ecb240abacn.dtsi"
/ {
model = "TI OMAP4 PandaBoard";
compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
leds {
compatible = "gpio-leds";
heartbeat {
label = "pandaboard::status1";
gpios = <&gpio1 7 0>;
linux,default-trigger = "heartbeat";
};
mmc {
label = "pandaboard::status2";
gpios = <&gpio1 8 0>;
linux,default-trigger = "mmc0";
};
};
sound: sound {
compatible = "ti,abe-twl6040";
ti,model = "PandaBoard";
ti,mclk-freq = <38400000>;
ti,mcpdm = <&mcpdm>;
ti,twl6040 = <&twl6040>;
/* Audio routing */
ti,audio-routing =
"Headset Stereophone", "HSOL",
"Headset Stereophone", "HSOR",
"Ext Spk", "HFL",
"Ext Spk", "HFR",
"Line Out", "AUXL",
"Line Out", "AUXR",
"HSMIC", "Headset Mic",
"Headset Mic", "Headset Mic Bias",
"AFML", "Line In",
"AFMR", "Line In";
};
};
&omap4_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&twl6040_pins
&mcpdm_pins
&mcbsp1_pins
&dss_hdmi_pins
&tpd12s015_pins
>;
twl6040_pins: pinmux_twl6040_pins {
pinctrl-single,pins = <
0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */
0x160 0x100 /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
>;
};
mcpdm_pins: pinmux_mcpdm_pins {
pinctrl-single,pins = <
0xc6 0x108 /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
0xc8 0x108 /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
0xca 0x118 /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
0xcc 0x108 /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
0xce 0x108 /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
>;
};
mcbsp1_pins: pinmux_mcbsp1_pins {
pinctrl-single,pins = <
0xbe 0x100 /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
0xc0 0x108 /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
0xc2 0x8 /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
>;
};
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
>;
};
tpd12s015_pins: pinmux_tpd12s015_pins {
pinctrl-single,pins = <
0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
>;
};
};
&i2c1 {
clock-frequency = <400000>;
twl: twl@48 {
reg = <0x48>;
/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
interrupt-parent = <&gic>;
};
twl6040: twl@4b {
compatible = "ti,twl6040";
reg = <0x4b>;
/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
interrupt-parent = <&gic>;
ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */
vio-supply = <&v1v8>;
v2v1-supply = <&v2v1>;
enable-active-high;
};
};
/include/ "twl6030.dtsi"
&i2c2 {
clock-frequency = <400000>;
};
&i2c3 {
clock-frequency = <100000>;
/*
* Display monitor features are burnt in their EEPROM as EDID data.
* The EEPROM is connected as I2C slave device.
*/
eeprom@50 {
compatible = "ti,eeprom";
reg = <0x50>;
};
};
&i2c4 {
clock-frequency = <400000>;
};
&mmc1 {
vmmc-supply = <&vmmc>;
bus-width = <8>;
};
&mmc2 {
status = "disabled";
};
&mmc3 {
status = "disabled";
};
&mmc4 {
status = "disabled";
};
&mmc5 {
ti,non-removable;
bus-width = <4>;
};
&emif1 {
cs1-used;
device-handle = <&elpida_ECB240ABACN>;
};
&emif2 {
cs1-used;
device-handle = <&elpida_ECB240ABACN>;
};
&mcbsp2 {
status = "disabled";
};
&mcbsp3 {
status = "disabled";
};
&dmic {
status = "disabled";
};
&twl_usb_comparator {
usb-supply = <&vusb>;
};
/include/ "omap443x.dtsi"
/include/ "omap4-panda-common.dtsi"

74
arch/arm/boot/dts/omap4-sdp.dts
View File

@ -7,7 +7,7 @@
*/
/dts-v1/;
/include/ "omap4.dtsi"
/include/ "omap443x.dtsi"
/include/ "elpida_ecb240abacn.dtsi"
/ {
@ -80,6 +80,32 @@
};
};
pwmleds {
compatible = "pwm-leds";
kpad {
label = "omap4::keypad";
pwms = <&twl_pwm 0 7812500>;
max-brightness = <127>;
};
charging {
label = "omap4:green:chrg";
pwms = <&twl_pwmled 0 7812500>;
max-brightness = <255>;
};
};
backlight {
compatible = "pwm-backlight";
pwms = <&twl_pwm 1 7812500>;
brightness-levels = <
0 10 20 30 40
50 60 70 80 90
100 110 120 127
>;
default-brightness-level = <13>;
};
sound {
compatible = "ti,abe-twl6040";
ti,model = "SDP4430";
@ -212,9 +238,40 @@
0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0xe2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
0xe4 0x118 /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
0xe6 0x118 /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
0xe8 0x118 /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
0xea 0x118 /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
0xec 0x118 /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
>;
};
i2c4_pins: pinmux_i2c4_pins {
pinctrl-single,pins = <
0xee 0x118 /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
0xf0 0x118 /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
twl: twl@48 {
@ -253,10 +310,16 @@
/include/ "twl6030.dtsi"
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <400000>;
/*
@ -279,6 +342,9 @@
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
clock-frequency = <400000>;
/*
@ -428,3 +494,9 @@
&twl_usb_comparator {
usb-supply = <&vusb>;
};
&usb_otg_hs {
interface-type = <1>;
mode = <3>;
power = <50>;
};

2
arch/arm/boot/dts/omap4-var-som.dts
View File

@ -7,7 +7,7 @@
*/
/dts-v1/;
/include/ "omap4.dtsi"
/include/ "omap443x.dtsi"
/ {
model = "Variscite OMAP4 SOM";

135
arch/arm/boot/dts/omap4.dtsi
View File

@ -94,6 +94,11 @@
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
reg = <0x44000000 0x1000>,
<0x44800000 0x2000>,
<0x45000000 0x1000>;
interrupts = <0 9 0x4>,
<0 10 0x4>;
counter32k: counter@4a304000 {
compatible = "ti,omap-counter32k";
@ -118,15 +123,28 @@
pinctrl-single,function-mask = <0x7fff>;
};
sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>;
interrupts = <0 12 0x4>,
<0 13 0x4>,
<0 14 0x4>,
<0 15 0x4>;
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <127>;
};
gpio1: gpio@4a310000 {
compatible = "ti,omap4-gpio";
reg = <0x4a310000 0x200>;
interrupts = <0 29 0x4>;
ti,hwmods = "gpio1";
ti,gpio-always-on;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio2: gpio@48055000 {
@ -137,7 +155,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio3: gpio@48057000 {
@ -148,7 +166,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio4: gpio@48059000 {
@ -159,7 +177,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio5: gpio@4805b000 {
@ -170,7 +188,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio6: gpio@4805d000 {
@ -181,7 +199,18 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpmc: gpmc@50000000 {
compatible = "ti,omap4430-gpmc";
reg = <0x50000000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
interrupts = <0 20 0x4>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
ti,hwmods = "gpmc";
};
uart1: serial@4806a000 {
@ -260,6 +289,16 @@
#size-cells = <0>;
ti,hwmods = "mcspi1";
ti,spi-num-cs = <4>;
dmas = <&sdma 35>,
<&sdma 36>,
<&sdma 37>,
<&sdma 38>,
<&sdma 39>,
<&sdma 40>,
<&sdma 41>,
<&sdma 42>;
dma-names = "tx0", "rx0", "tx1", "rx1",
"tx2", "rx2", "tx3", "rx3";
};
mcspi2: spi@4809a000 {
@ -270,6 +309,11 @@
#size-cells = <0>;
ti,hwmods = "mcspi2";
ti,spi-num-cs = <2>;
dmas = <&sdma 43>,
<&sdma 44>,
<&sdma 45>,
<&sdma 46>;
dma-names = "tx0", "rx0", "tx1", "rx1";
};
mcspi3: spi@480b8000 {
@ -280,6 +324,8 @@
#size-cells = <0>;
ti,hwmods = "mcspi3";
ti,spi-num-cs = <2>;
dmas = <&sdma 15>, <&sdma 16>;
dma-names = "tx0", "rx0";
};
mcspi4: spi@480ba000 {
@ -290,6 +336,8 @@
#size-cells = <0>;
ti,hwmods = "mcspi4";
ti,spi-num-cs = <1>;
dmas = <&sdma 70>, <&sdma 71>;
dma-names = "tx0", "rx0";
};
mmc1: mmc@4809c000 {
@ -299,6 +347,8 @@
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
dmas = <&sdma 61>, <&sdma 62>;
dma-names = "tx", "rx";
};
mmc2: mmc@480b4000 {
@ -307,6 +357,8 @@
interrupts = <0 86 0x4>;
ti,hwmods = "mmc2";
ti,needs-special-reset;
dmas = <&sdma 47>, <&sdma 48>;
dma-names = "tx", "rx";
};
mmc3: mmc@480ad000 {
@ -315,6 +367,8 @@
interrupts = <0 94 0x4>;
ti,hwmods = "mmc3";
ti,needs-special-reset;
dmas = <&sdma 77>, <&sdma 78>;
dma-names = "tx", "rx";
};
mmc4: mmc@480d1000 {
@ -323,6 +377,8 @@
interrupts = <0 96 0x4>;
ti,hwmods = "mmc4";
ti,needs-special-reset;
dmas = <&sdma 57>, <&sdma 58>;
dma-names = "tx", "rx";
};
mmc5: mmc@480d5000 {
@ -331,6 +387,8 @@
interrupts = <0 59 0x4>;
ti,hwmods = "mmc5";
ti,needs-special-reset;
dmas = <&sdma 59>, <&sdma 60>;
dma-names = "tx", "rx";
};
wdt2: wdt@4a314000 {
@ -347,6 +405,9 @@
reg-names = "mpu", "dma";
interrupts = <0 112 0x4>;
ti,hwmods = "mcpdm";
dmas = <&sdma 65>,
<&sdma 66>;
dma-names = "up_link", "dn_link";
};
dmic: dmic@4012e000 {
@ -356,6 +417,8 @@
reg-names = "mpu", "dma";
interrupts = <0 114 0x4>;
ti,hwmods = "dmic";
dmas = <&sdma 67>;
dma-names = "up_link";
};
mcbsp1: mcbsp@40122000 {
@ -367,6 +430,9 @@
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp1";
dmas = <&sdma 33>,
<&sdma 34>;
dma-names = "tx", "rx";
};
mcbsp2: mcbsp@40124000 {
@ -378,6 +444,9 @@
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp2";
dmas = <&sdma 17>,
<&sdma 18>;
dma-names = "tx", "rx";
};
mcbsp3: mcbsp@40126000 {
@ -389,6 +458,9 @@
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp3";
dmas = <&sdma 19>,
<&sdma 20>;
dma-names = "tx", "rx";
};
mcbsp4: mcbsp@48096000 {
@ -399,6 +471,9 @@
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp4";
dmas = <&sdma 31>,
<&sdma 32>;
dma-names = "tx", "rx";
};
keypad: keypad@4a31c000 {
@ -438,10 +513,15 @@
#size-cells = <1>;
ranges;
ti,hwmods = "ocp2scp_usb_phy";
usb2_phy: usb2phy@4a0ad080 {
compatible = "ti,omap-usb2";
reg = <0x4a0ad080 0x58>;
ctrl-module = <&omap_control_usb>;
};
};
timer1: timer@4a318000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x4a318000 0x80>;
interrupts = <0 37 0x4>;
ti,hwmods = "timer1";
@ -449,28 +529,28 @@
};
timer2: timer@48032000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x48032000 0x80>;
interrupts = <0 38 0x4>;
ti,hwmods = "timer2";
};
timer3: timer@48034000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap4430-timer";
reg = <0x48034000 0x80>;
interrupts = <0 39 0x4>;
ti,hwmods = "timer3";
};
timer4: timer@48036000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap4430-timer";
reg = <0x48036000 0x80>;
interrupts = <0 40 0x4>;
ti,hwmods = "timer4";
};
timer5: timer@40138000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap4430-timer";
reg = <0x40138000 0x80>,
<0x49038000 0x80>;
interrupts = <0 41 0x4>;
@ -479,7 +559,7 @@
};
timer6: timer@4013a000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap4430-timer";
reg = <0x4013a000 0x80>,
<0x4903a000 0x80>;
interrupts = <0 42 0x4>;
@ -488,7 +568,7 @@
};
timer7: timer@4013c000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap4430-timer";
reg = <0x4013c000 0x80>,
<0x4903c000 0x80>;
interrupts = <0 43 0x4>;
@ -497,7 +577,7 @@
};
timer8: timer@4013e000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap4430-timer";
reg = <0x4013e000 0x80>,
<0x4903e000 0x80>;
interrupts = <0 44 0x4>;
@ -507,7 +587,7 @@
};
timer9: timer@4803e000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap4430-timer";
reg = <0x4803e000 0x80>;
interrupts = <0 45 0x4>;
ti,hwmods = "timer9";
@ -515,7 +595,7 @@
};
timer10: timer@48086000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap3430-timer";
reg = <0x48086000 0x80>;
interrupts = <0 46 0x4>;
ti,hwmods = "timer10";
@ -523,7 +603,7 @@
};
timer11: timer@48088000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap4430-timer";
reg = <0x48088000 0x80>;
interrupts = <0 47 0x4>;
ti,hwmods = "timer11";
@ -559,5 +639,26 @@
interrupts = <0 77 0x4>;
};
};
omap_control_usb: omap-control-usb@4a002300 {
compatible = "ti,omap-control-usb";
reg = <0x4a002300 0x4>,
<0x4a00233c 0x4>;
reg-names = "control_dev_conf", "otghs_control";
ti,type = <1>;
};
usb_otg_hs: usb_otg_hs@4a0ab000 {
compatible = "ti,omap4-musb";
reg = <0x4a0ab000 0x7ff>;
interrupts = <0 92 0x4>, <0 93 0x4>;
interrupt-names = "mc", "dma";
ti,hwmods = "usb_otg_hs";
usb-phy = <&usb2_phy>;
multipoint = <1>;
num-eps = <16>;
ram-bits = <12>;
ti,has-mailbox;
};
};
};

27
arch/arm/boot/dts/omap443x.dtsi Normal file
View File

@ -0,0 +1,27 @@
/*
* Device Tree Source for OMAP443x SoC
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "omap4.dtsi"
/ {
cpus {
cpu@0 {
/* OMAP443x variants OPP50-OPPNT */
operating-points = <
/* kHz uV */
300000 1025000
600000 1200000
800000 1313000
1008000 1375000
>;
clock-latency = <300000>; /* From legacy driver */
};
};
};

32
arch/arm/boot/dts/omap4460.dtsi Normal file
View File

@ -0,0 +1,32 @@
/*
* Device Tree Source for OMAP4460 SoC
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "omap4.dtsi"
/ {
cpus {
/* OMAP446x 'standard device' variants OPP50 to OPPTurbo */
cpu@0 {
operating-points = <
/* kHz uV */
350000 975000
700000 1075000
920000 1200000
>;
clock-latency = <300000>; /* From legacy driver */
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 54 0x4>,
<0 55 0x4>;
ti,hwmods = "debugss";
};
};

110
arch/arm/boot/dts/omap5-evm.dts
View File

@ -16,7 +16,7 @@
memory {
device_type = "memory";
reg = <0x80000000 0x80000000>; /* 2 GB */
reg = <0x80000000 0x7F000000>; /* 2032 MB */
};
vmmcsd_fixed: fixedregulator-mmcsd {
@ -80,6 +80,68 @@
0x15a 0x100 /* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x1b2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
0x1b4 0x118 /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
0x178 0x100 /* i2c2_scl INPUTENABLE | MODE0 */
0x17a 0x100 /* i2c2_sda INPUTENABLE | MODE0 */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
0x13a 0x100 /* i2c3_scl INPUTENABLE | MODE0 */
0x13c 0x100 /* i2c3_sda INPUTENABLE | MODE0 */
>;
};
i2c4_pins: pinmux_i2c4_pins {
pinctrl-single,pins = <
0xb8 0x100 /* i2c4_scl INPUTENABLE | MODE0 */
0xba 0x100 /* i2c4_sda INPUTENABLE | MODE0 */
>;
};
i2c5_pins: pinmux_i2c5_pins {
pinctrl-single,pins = <
0x184 0x100 /* i2c5_scl INPUTENABLE | MODE0 */
0x186 0x100 /* i2c5_sda INPUTENABLE | MODE0 */
>;
};
mcspi2_pins: pinmux_mcspi2_pins {
pinctrl-single,pins = <
0xbc 0x100 /* MCSPI2_CLK INPUTENABLE | MODE0 */
0xbe 0x100 /* MCSPI2_SIMO INPUTENABLE | MODE0 */
0xc0 0x118 /* MCSPI2_SOMI PULLUP | INPUTENABLE | MODE0*/
0xc2 0x0 /* MCSPI2_CS MODE0*/
>;
};
mcspi3_pins: pinmux_mcspi3_pins {
pinctrl-single,pins = <
0x78 0x101 /* MCSPI2_SOMI INPUTENABLE | MODE1 */
0x7a 0x101 /* MCSPI2_CS INPUTENABLE | MODE1 */
0x7c 0x101 /* MCSPI2_SIMO INPUTENABLE | MODE1 */
0x7e 0x101 /* MCSPI2_CLK INPUTENABLE | MODE1 */
>;
};
mcspi4_pins: pinmux_mcspi4_pins {
pinctrl-single,pins = <
0x164 0x101 /* MCSPI2_CLK INPUTENABLE | MODE1 */
0x168 0x101 /* MCSPI2_SIMO INPUTENABLE | MODE1 */
0x16a 0x101 /* MCSPI2_SOMI INPUTENABLE | MODE1 */
0x16c 0x101 /* MCSPI2_CS INPUTENABLE | MODE1 */
>;
};
};
&mmc1 {
@ -106,7 +168,17 @@
status = "disabled";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
/* Pressure Sensor */
@ -116,7 +188,17 @@
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <400000>;
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
clock-frequency = <400000>;
/* Temperature Sensor */
@ -126,6 +208,13 @@
};
};
&i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
clock-frequency = <400000>;
};
&keypad {
keypad,num-rows = <8>;
keypad,num-columns = <8>;
@ -151,3 +240,22 @@
cs1-used;
device-handle = <&samsung_K3PE0E000B>;
};
&mcspi1 {
};
&mcspi2 {
pinctrl-names = "default";
pinctrl-0 = <&mcspi2_pins>;
};
&mcspi3 {
pinctrl-names = "default";
pinctrl-0 = <&mcspi3_pins>;
};
&mcspi4 {
pinctrl-names = "default";
pinctrl-0 = <&mcspi4_pins>;
};

245
arch/arm/boot/dts/omap5.dtsi
View File

@ -18,6 +18,9 @@
/include/ "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "ti,omap5";
interrupt-parent = <&gic>;
@ -33,24 +36,32 @@
cpus {
cpu@0 {
compatible = "arm,cortex-a15";
timer {
compatible = "arm,armv7-timer";
/* 14th PPI IRQ, active low level-sensitive */
interrupts = <1 14 0x308>;
clock-frequency = <6144000>;
};
};
cpu@1 {
compatible = "arm,cortex-a15";
timer {
compatible = "arm,armv7-timer";
/* 14th PPI IRQ, active low level-sensitive */
interrupts = <1 14 0x308>;
clock-frequency = <6144000>;
};
};
};
timer {
compatible = "arm,armv7-timer";
/* PPI secure/nonsecure IRQ, active low level-sensitive */
interrupts = <1 13 0x308>,
<1 14 0x308>,
<1 11 0x308>,
<1 10 0x308>;
clock-frequency = <6144000>;
};
gic: interrupt-controller@48211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x48211000 0x1000>,
<0x48212000 0x1000>,
<0x48214000 0x2000>,
<0x48216000 0x2000>;
};
/*
* The soc node represents the soc top level view. It is uses for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
@ -76,6 +87,11 @@
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
reg = <0x44000000 0x2000>,
<0x44800000 0x3000>,
<0x45000000 0x4000>;
interrupts = <0 9 0x4>,
<0 10 0x4>;
counter32k: counter@4ae04000 {
compatible = "ti,omap-counter32k";
@ -100,12 +116,16 @@
pinctrl-single,function-mask = <0x7fff>;
};
gic: interrupt-controller@48211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x48211000 0x1000>,
<0x48212000 0x1000>;
sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>;
interrupts = <0 12 0x4>,
<0 13 0x4>,
<0 14 0x4>,
<0 15 0x4>;
#dma-cells = <1>;
#dma-channels = <32>;
#dma-requests = <127>;
};
gpio1: gpio@4ae10000 {
@ -113,10 +133,11 @@
reg = <0x4ae10000 0x200>;
interrupts = <0 29 0x4>;
ti,hwmods = "gpio1";
ti,gpio-always-on;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio2: gpio@48055000 {
@ -127,7 +148,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio3: gpio@48057000 {
@ -138,7 +159,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio4: gpio@48059000 {
@ -149,7 +170,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio5: gpio@4805b000 {
@ -160,7 +181,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio6: gpio@4805d000 {
@ -171,7 +192,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio7: gpio@48051000 {
@ -182,7 +203,7 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio8: gpio@48053000 {
@ -193,7 +214,18 @@
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpmc: gpmc@50000000 {
compatible = "ti,omap4430-gpmc";
reg = <0x50000000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
interrupts = <0 20 0x4>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
ti,hwmods = "gpmc";
};
i2c1: i2c@48070000 {
@ -241,6 +273,65 @@
ti,hwmods = "i2c5";
};
mcspi1: spi@48098000 {
compatible = "ti,omap4-mcspi";
reg = <0x48098000 0x200>;
interrupts = <0 65 0x4>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi1";
ti,spi-num-cs = <4>;
dmas = <&sdma 35>,
<&sdma 36>,
<&sdma 37>,
<&sdma 38>,
<&sdma 39>,
<&sdma 40>,
<&sdma 41>,
<&sdma 42>;
dma-names = "tx0", "rx0", "tx1", "rx1",
"tx2", "rx2", "tx3", "rx3";
};
mcspi2: spi@4809a000 {
compatible = "ti,omap4-mcspi";
reg = <0x4809a000 0x200>;
interrupts = <0 66 0x4>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi2";
ti,spi-num-cs = <2>;
dmas = <&sdma 43>,
<&sdma 44>,
<&sdma 45>,
<&sdma 46>;
dma-names = "tx0", "rx0", "tx1", "rx1";
};
mcspi3: spi@480b8000 {
compatible = "ti,omap4-mcspi";
reg = <0x480b8000 0x200>;
interrupts = <0 91 0x4>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi3";
ti,spi-num-cs = <2>;
dmas = <&sdma 15>, <&sdma 16>;
dma-names = "tx0", "rx0";
};
mcspi4: spi@480ba000 {
compatible = "ti,omap4-mcspi";
reg = <0x480ba000 0x200>;
interrupts = <0 48 0x4>;
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "mcspi4";
ti,spi-num-cs = <1>;
dmas = <&sdma 70>, <&sdma 71>;
dma-names = "tx0", "rx0";
};
uart1: serial@4806a000 {
compatible = "ti,omap4-uart";
reg = <0x4806a000 0x100>;
@ -296,6 +387,8 @@
ti,hwmods = "mmc1";
ti,dual-volt;
ti,needs-special-reset;
dmas = <&sdma 61>, <&sdma 62>;
dma-names = "tx", "rx";
};
mmc2: mmc@480b4000 {
@ -304,6 +397,8 @@
interrupts = <0 86 0x4>;
ti,hwmods = "mmc2";
ti,needs-special-reset;
dmas = <&sdma 47>, <&sdma 48>;
dma-names = "tx", "rx";
};
mmc3: mmc@480ad000 {
@ -312,6 +407,8 @@
interrupts = <0 94 0x4>;
ti,hwmods = "mmc3";
ti,needs-special-reset;
dmas = <&sdma 77>, <&sdma 78>;
dma-names = "tx", "rx";
};
mmc4: mmc@480d1000 {
@ -320,6 +417,8 @@
interrupts = <0 96 0x4>;
ti,hwmods = "mmc4";
ti,needs-special-reset;
dmas = <&sdma 57>, <&sdma 58>;
dma-names = "tx", "rx";
};
mmc5: mmc@480d5000 {
@ -328,10 +427,13 @@
interrupts = <0 59 0x4>;
ti,hwmods = "mmc5";
ti,needs-special-reset;
dmas = <&sdma 59>, <&sdma 60>;
dma-names = "tx", "rx";
};
keypad: keypad@4ae1c000 {
compatible = "ti,omap4-keypad";
reg = <0x4ae1c000 0x400>;
ti,hwmods = "kbd";
};
@ -342,6 +444,9 @@
reg-names = "mpu", "dma";
interrupts = <0 112 0x4>;
ti,hwmods = "mcpdm";
dmas = <&sdma 65>,
<&sdma 66>;
dma-names = "up_link", "dn_link";
};
dmic: dmic@4012e000 {
@ -351,6 +456,8 @@
reg-names = "mpu", "dma";
interrupts = <0 114 0x4>;
ti,hwmods = "dmic";
dmas = <&sdma 67>;
dma-names = "up_link";
};
mcbsp1: mcbsp@40122000 {
@ -362,6 +469,9 @@
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp1";
dmas = <&sdma 33>,
<&sdma 34>;
dma-names = "tx", "rx";
};
mcbsp2: mcbsp@40124000 {
@ -373,6 +483,9 @@
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp2";
dmas = <&sdma 17>,
<&sdma 18>;
dma-names = "tx", "rx";
};
mcbsp3: mcbsp@40126000 {
@ -384,10 +497,13 @@
interrupt-names = "common";
ti,buffer-size = <128>;
ti,hwmods = "mcbsp3";
dmas = <&sdma 19>,
<&sdma 20>;
dma-names = "tx", "rx";
};
timer1: timer@4ae18000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap5430-timer";
reg = <0x4ae18000 0x80>;
interrupts = <0 37 0x4>;
ti,hwmods = "timer1";
@ -395,28 +511,28 @@
};
timer2: timer@48032000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap5430-timer";
reg = <0x48032000 0x80>;
interrupts = <0 38 0x4>;
ti,hwmods = "timer2";
};
timer3: timer@48034000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap5430-timer";
reg = <0x48034000 0x80>;
interrupts = <0 39 0x4>;
ti,hwmods = "timer3";
};
timer4: timer@48036000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap5430-timer";
reg = <0x48036000 0x80>;
interrupts = <0 40 0x4>;
ti,hwmods = "timer4";
};
timer5: timer@40138000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap5430-timer";
reg = <0x40138000 0x80>,
<0x49038000 0x80>;
interrupts = <0 41 0x4>;
@ -425,7 +541,7 @@
};
timer6: timer@4013a000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap5430-timer";
reg = <0x4013a000 0x80>,
<0x4903a000 0x80>;
interrupts = <0 42 0x4>;
@ -435,7 +551,7 @@
};
timer7: timer@4013c000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap5430-timer";
reg = <0x4013c000 0x80>,
<0x4903c000 0x80>;
interrupts = <0 43 0x4>;
@ -444,7 +560,7 @@
};
timer8: timer@4013e000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap5430-timer";
reg = <0x4013e000 0x80>,
<0x4903e000 0x80>;
interrupts = <0 44 0x4>;
@ -454,27 +570,34 @@
};
timer9: timer@4803e000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap5430-timer";
reg = <0x4803e000 0x80>;
interrupts = <0 45 0x4>;
ti,hwmods = "timer9";
};
timer10: timer@48086000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap5430-timer";
reg = <0x48086000 0x80>;
interrupts = <0 46 0x4>;
ti,hwmods = "timer10";
};
timer11: timer@48088000 {
compatible = "ti,omap2-timer";
compatible = "ti,omap5430-timer";
reg = <0x48088000 0x80>;
interrupts = <0 47 0x4>;
ti,hwmods = "timer11";
ti,timer-pwm;
};
wdt2: wdt@4ae14000 {
compatible = "ti,omap5-wdt", "ti,omap3-wdt";
reg = <0x4ae14000 0x80>;
interrupts = <0 80 0x4>;
ti,hwmods = "wd_timer2";
};
emif1: emif@0x4c000000 {
compatible = "ti,emif-4d5";
ti,hwmods = "emif1";
@ -496,5 +619,53 @@
hw-caps-ll-interface;
hw-caps-temp-alert;
};
omap_control_usb: omap-control-usb@4a002300 {
compatible = "ti,omap-control-usb";
reg = <0x4a002300 0x4>,
<0x4a002370 0x4>;
reg-names = "control_dev_conf", "phy_power_usb";
ti,type = <2>;
};
omap_dwc3@4a020000 {
compatible = "ti,dwc3";
ti,hwmods = "usb_otg_ss";
reg = <0x4a020000 0x1000>;
interrupts = <0 93 4>;
#address-cells = <1>;
#size-cells = <1>;
utmi-mode = <2>;
ranges;
dwc3@4a030000 {
compatible = "synopsys,dwc3";
reg = <0x4a030000 0x1000>;
interrupts = <0 92 4>;
usb-phy = <&usb2_phy>, <&usb3_phy>;
tx-fifo-resize;
};
};
ocp2scp {
compatible = "ti,omap-ocp2scp";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "ocp2scp1";
usb2_phy: usb2phy@4a084000 {
compatible = "ti,omap-usb2";
reg = <0x4a084000 0x7c>;
ctrl-module = <&omap_control_usb>;
};
usb3_phy: usb3phy@4a084400 {
compatible = "ti,omap-usb3";
reg = <0x4a084400 0x80>,
<0x4a084800 0x64>,
<0x4a084c00 0x40>;
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
ctrl-module = <&omap_control_usb>;
};
};
};
};

891
arch/arm/boot/dts/tegra114-dalmore.dts
View File

@ -10,14 +10,835 @@
reg = <0x80000000 0x40000000>;
};
pinmux {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
clk1_out_pw4 {
nvidia,pins = "clk1_out_pw4";
nvidia,function = "extperiph1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
dap1_din_pn1 {
nvidia,pins = "dap1_din_pn1";
nvidia,function = "i2s0";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
dap1_dout_pn2 {
nvidia,pins = "dap1_dout_pn2",
"dap1_fs_pn0",
"dap1_sclk_pn3";
nvidia,function = "i2s0";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
dap2_din_pa4 {
nvidia,pins = "dap2_din_pa4";
nvidia,function = "i2s1";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
dap2_dout_pa5 {
nvidia,pins = "dap2_dout_pa5",
"dap2_fs_pa2",
"dap2_sclk_pa3";
nvidia,function = "i2s1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
dap4_din_pp5 {
nvidia,pins = "dap4_din_pp5",
"dap4_dout_pp6",
"dap4_fs_pp4",
"dap4_sclk_pp7";
nvidia,function = "i2s3";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
dvfs_pwm_px0 {
nvidia,pins = "dvfs_pwm_px0",
"dvfs_clk_px2";
nvidia,function = "cldvfs";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
ulpi_clk_py0 {
nvidia,pins = "ulpi_clk_py0",
"ulpi_data0_po1",
"ulpi_data1_po2",
"ulpi_data2_po3",
"ulpi_data3_po4",
"ulpi_data4_po5",
"ulpi_data5_po6",
"ulpi_data6_po7",
"ulpi_data7_po0";
nvidia,function = "ulpi";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
ulpi_dir_py1 {
nvidia,pins = "ulpi_dir_py1",
"ulpi_nxt_py2";
nvidia,function = "ulpi";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
ulpi_stp_py3 {
nvidia,pins = "ulpi_stp_py3";
nvidia,function = "ulpi";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
cam_i2c_scl_pbb1 {
nvidia,pins = "cam_i2c_scl_pbb1",
"cam_i2c_sda_pbb2";
nvidia,function = "i2c3";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
nvidia,open-drain = <0>;
};
cam_mclk_pcc0 {
nvidia,pins = "cam_mclk_pcc0",
"pbb0";
nvidia,function = "vi_alt3";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
nvidia,lock = <0>;
};
gen2_i2c_scl_pt5 {
nvidia,pins = "gen2_i2c_scl_pt5",
"gen2_i2c_sda_pt6";
nvidia,function = "i2c2";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
nvidia,open-drain = <0>;
};
gmi_a16_pj7 {
nvidia,pins = "gmi_a16_pj7";
nvidia,function = "uartd";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gmi_a17_pb0 {
nvidia,pins = "gmi_a17_pb0",
"gmi_a18_pb1";
nvidia,function = "uartd";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
gmi_a19_pk7 {
nvidia,pins = "gmi_a19_pk7";
nvidia,function = "uartd";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gmi_ad5_pg5 {
nvidia,pins = "gmi_ad5_pg5",
"gmi_cs6_n_pi3",
"gmi_wr_n_pi0";
nvidia,function = "spi4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gmi_ad6_pg6 {
nvidia,pins = "gmi_ad6_pg6",
"gmi_ad7_pg7";
nvidia,function = "spi4";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gmi_ad12_ph4 {
nvidia,pins = "gmi_ad12_ph4";
nvidia,function = "rsvd4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gmi_ad9_ph1 {
nvidia,pins = "gmi_ad9_ph1";
nvidia,function = "pwm1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gmi_cs1_n_pj2 {
nvidia,pins = "gmi_cs1_n_pj2",
"gmi_oe_n_pi1";
nvidia,function = "soc";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
clk2_out_pw5 {
nvidia,pins = "clk2_out_pw5";
nvidia,function = "extperiph2";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
sdmmc1_clk_pz0 {
nvidia,pins = "sdmmc1_clk_pz0";
nvidia,function = "sdmmc1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
sdmmc1_cmd_pz1 {
nvidia,pins = "sdmmc1_cmd_pz1",
"sdmmc1_dat0_py7",
"sdmmc1_dat1_py6",
"sdmmc1_dat2_py5",
"sdmmc1_dat3_py4";
nvidia,function = "sdmmc1";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
sdmmc1_wp_n_pv3 {
nvidia,pins = "sdmmc1_wp_n_pv3";
nvidia,function = "spi4";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
sdmmc3_clk_pa6 {
nvidia,pins = "sdmmc3_clk_pa6";
nvidia,function = "sdmmc3";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
sdmmc3_cmd_pa7 {
nvidia,pins = "sdmmc3_cmd_pa7",
"sdmmc3_dat0_pb7",
"sdmmc3_dat1_pb6",
"sdmmc3_dat2_pb5",
"sdmmc3_dat3_pb4",
"kb_col4_pq4",
"sdmmc3_clk_lb_out_pee4",
"sdmmc3_clk_lb_in_pee5";
nvidia,function = "sdmmc3";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4";
nvidia,function = "sdmmc4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
sdmmc4_cmd_pt7 {
nvidia,pins = "sdmmc4_cmd_pt7",
"sdmmc4_dat0_paa0",
"sdmmc4_dat1_paa1",
"sdmmc4_dat2_paa2",
"sdmmc4_dat3_paa3",
"sdmmc4_dat4_paa4",
"sdmmc4_dat5_paa5",
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
clk_32k_out_pa0 {
nvidia,pins = "clk_32k_out_pa0";
nvidia,function = "blink";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
kb_col0_pq0 {
nvidia,pins = "kb_col0_pq0",
"kb_col1_pq1",
"kb_col2_pq2",
"kb_row0_pr0",
"kb_row1_pr1",
"kb_row2_pr2";
nvidia,function = "kbc";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
dap3_din_pp1 {
nvidia,pins = "dap3_din_pp1",
"dap3_sclk_pp3";
nvidia,function = "displayb";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <0>;
};
pv0 {
nvidia,pins = "pv0";
nvidia,function = "rsvd4";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <0>;
};
kb_row7_pr7 {
nvidia,pins = "kb_row7_pr7";
nvidia,function = "rsvd2";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
kb_row10_ps2 {
nvidia,pins = "kb_row10_ps2";
nvidia,function = "uarta";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
kb_row9_ps1 {
nvidia,pins = "kb_row9_ps1";
nvidia,function = "uarta";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
pwr_i2c_scl_pz6 {
nvidia,pins = "pwr_i2c_scl_pz6",
"pwr_i2c_sda_pz7";
nvidia,function = "i2cpwr";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
nvidia,open-drain = <0>;
};
sys_clk_req_pz5 {
nvidia,pins = "sys_clk_req_pz5";
nvidia,function = "sysclk";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
core_pwr_req {
nvidia,pins = "core_pwr_req";
nvidia,function = "pwron";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
cpu_pwr_req {
nvidia,pins = "cpu_pwr_req";
nvidia,function = "cpu";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
pwr_int_n {
nvidia,pins = "pwr_int_n";
nvidia,function = "pmi";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
reset_out_n {
nvidia,pins = "reset_out_n";
nvidia,function = "reset_out_n";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
clk3_out_pee0 {
nvidia,pins = "clk3_out_pee0";
nvidia,function = "extperiph3";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gen1_i2c_scl_pc4 {
nvidia,pins = "gen1_i2c_scl_pc4",
"gen1_i2c_sda_pc5";
nvidia,function = "i2c1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
nvidia,open-drain = <0>;
};
uart2_cts_n_pj5 {
nvidia,pins = "uart2_cts_n_pj5";
nvidia,function = "uartb";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
uart2_rts_n_pj6 {
nvidia,pins = "uart2_rts_n_pj6";
nvidia,function = "uartb";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
uart2_rxd_pc3 {
nvidia,pins = "uart2_rxd_pc3";
nvidia,function = "irda";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
uart2_txd_pc2 {
nvidia,pins = "uart2_txd_pc2";
nvidia,function = "irda";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
uart3_cts_n_pa1 {
nvidia,pins = "uart3_cts_n_pa1",
"uart3_rxd_pw7";
nvidia,function = "uartc";
nvidia,pull = <0>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
uart3_rts_n_pc0 {
nvidia,pins = "uart3_rts_n_pc0",
"uart3_txd_pw6";
nvidia,function = "uartc";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
owr {
nvidia,pins = "owr";
nvidia,function = "owr";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
hdmi_cec_pee3 {
nvidia,pins = "hdmi_cec_pee3";
nvidia,function = "cec";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
nvidia,open-drain = <0>;
};
ddc_scl_pv4 {
nvidia,pins = "ddc_scl_pv4",
"ddc_sda_pv5";
nvidia,function = "i2c4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
nvidia,rcv-sel = <1>;
};
spdif_in_pk6 {
nvidia,pins = "spdif_in_pk6";
nvidia,function = "usb";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
};
usb_vbus_en0_pn4 {
nvidia,pins = "usb_vbus_en0_pn4";
nvidia,function = "usb";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
nvidia,lock = <0>;
nvidia,open-drain = <1>;
};
gpio_x6_aud_px6 {
nvidia,pins = "gpio_x6_aud_px6";
nvidia,function = "spi6";
nvidia,pull = <2>;
nvidia,tristate = <1>;
nvidia,enable-input = <1>;
};
gpio_x4_aud_px4 {
nvidia,pins = "gpio_x4_aud_px4",
"gpio_x7_aud_px7";
nvidia,function = "rsvd1";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gpio_x5_aud_px5 {
nvidia,pins = "gpio_x5_aud_px5";
nvidia,function = "rsvd1";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gpio_w2_aud_pw2 {
nvidia,pins = "gpio_w2_aud_pw2";
nvidia,function = "rsvd2";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gpio_w3_aud_pw3 {
nvidia,pins = "gpio_w3_aud_pw3";
nvidia,function = "spi6";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gpio_x1_aud_px1 {
nvidia,pins = "gpio_x1_aud_px1";
nvidia,function = "rsvd4";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gpio_x3_aud_px3 {
nvidia,pins = "gpio_x3_aud_px3";
nvidia,function = "rsvd4";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
dap3_fs_pp0 {
nvidia,pins = "dap3_fs_pp0";
nvidia,function = "i2s2";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
dap3_dout_pp2 {
nvidia,pins = "dap3_dout_pp2";
nvidia,function = "i2s2";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
pv1 {
nvidia,pins = "pv1";
nvidia,function = "rsvd1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
pbb3 {
nvidia,pins = "pbb3",
"pbb5",
"pbb6",
"pbb7";
nvidia,function = "rsvd4";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
pcc1 {
nvidia,pins = "pcc1",
"pcc2";
nvidia,function = "rsvd4";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gmi_ad0_pg0 {
nvidia,pins = "gmi_ad0_pg0",
"gmi_ad1_pg1";
nvidia,function = "gmi";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gmi_ad10_ph2 {
nvidia,pins = "gmi_ad10_ph2",
"gmi_ad11_ph3",
"gmi_ad13_ph5",
"gmi_ad8_ph0",
"gmi_clk_pk1";
nvidia,function = "gmi";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
gmi_ad2_pg2 {
nvidia,pins = "gmi_ad2_pg2",
"gmi_ad3_pg3";
nvidia,function = "gmi";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gmi_adv_n_pk0 {
nvidia,pins = "gmi_adv_n_pk0",
"gmi_cs0_n_pj0",
"gmi_cs2_n_pk3",
"gmi_cs4_n_pk2",
"gmi_cs7_n_pi6",
"gmi_dqs_p_pj3",
"gmi_iordy_pi5",
"gmi_wp_n_pc7";
nvidia,function = "gmi";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
gmi_cs3_n_pk4 {
nvidia,pins = "gmi_cs3_n_pk4";
nvidia,function = "gmi";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
clk2_req_pcc5 {
nvidia,pins = "clk2_req_pcc5";
nvidia,function = "rsvd4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
kb_col3_pq3 {
nvidia,pins = "kb_col3_pq3",
"kb_col6_pq6",
"kb_col7_pq7";
nvidia,function = "kbc";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
kb_col5_pq5 {
nvidia,pins = "kb_col5_pq5";
nvidia,function = "kbc";
nvidia,pull = <2>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
kb_row3_pr3 {
nvidia,pins = "kb_row3_pr3",
"kb_row4_pr4",
"kb_row6_pr6",
"kb_row8_ps0";
nvidia,function = "kbc";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
clk3_req_pee1 {
nvidia,pins = "clk3_req_pee1";
nvidia,function = "rsvd4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
pu4 {
nvidia,pins = "pu4";
nvidia,function = "displayb";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <0>;
};
pu5 {
nvidia,pins = "pu5",
"pu6";
nvidia,function = "displayb";
nvidia,pull = <0>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
hdmi_int_pn7 {
nvidia,pins = "hdmi_int_pn7";
nvidia,function = "rsvd1";
nvidia,pull = <1>;
nvidia,tristate = <0>;
nvidia,enable-input = <1>;
};
clk1_req_pee2 {
nvidia,pins = "clk1_req_pee2",
"usb_vbus_en1_pn5";
nvidia,function = "rsvd4";
nvidia,pull = <1>;
nvidia,tristate = <1>;
nvidia,enable-input = <0>;
};
drive_sdio1 {
nvidia,pins = "drive_sdio1";
nvidia,high-speed-mode = <1>;
nvidia,schmitt = <0>;
nvidia,low-power-mode = <3>;
nvidia,pull-down-strength = <36>;
nvidia,pull-up-strength = <20>;
nvidia,slew-rate-rising = <2>;
nvidia,slew-rate-falling = <2>;
};
drive_sdio3 {
nvidia,pins = "drive_sdio3";
nvidia,high-speed-mode = <1>;
nvidia,schmitt = <0>;
nvidia,low-power-mode = <3>;
nvidia,pull-down-strength = <22>;
nvidia,pull-up-strength = <36>;
nvidia,slew-rate-rising = <0>;
nvidia,slew-rate-falling = <0>;
};
drive_gma {
nvidia,pins = "drive_gma";
nvidia,high-speed-mode = <1>;
nvidia,schmitt = <0>;
nvidia,low-power-mode = <3>;
nvidia,pull-down-strength = <2>;
nvidia,pull-up-strength = <1>;
nvidia,slew-rate-rising = <0>;
nvidia,slew-rate-falling = <0>;
nvidia,drive-type = <1>;
};
};
};
serial@70006300 {
status = "okay";
};
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
battery: smart-battery {
compatible = "ti,bq20z45", "sbs,sbs-battery";
reg = <0xb>;
battery-name = "battery";
sbs,i2c-retry-count = <2>;
sbs,poll-retry-count = <100>;
};
};
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
tps51632 {
compatible = "ti,tps51632";
reg = <0x43>;
regulator-name = "vdd-cpu";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1520000>;
regulator-boot-on;
regulator-always-on;
};
tps65090 {
compatible = "ti,tps65090";
reg = <0x48>;
interrupt-parent = <&gpio>;
interrupts = <72 0x04>; /* gpio PJ0 */
vsys1-supply = <&vdd_ac_bat_reg>;
vsys2-supply = <&vdd_ac_bat_reg>;
vsys3-supply = <&vdd_ac_bat_reg>;
infet1-supply = <&vdd_ac_bat_reg>;
infet2-supply = <&vdd_ac_bat_reg>;
infet3-supply = <&tps65090_dcdc2_reg>;
infet4-supply = <&tps65090_dcdc2_reg>;
infet5-supply = <&tps65090_dcdc2_reg>;
infet6-supply = <&tps65090_dcdc2_reg>;
infet7-supply = <&tps65090_dcdc2_reg>;
vsys-l1-supply = <&vdd_ac_bat_reg>;
vsys-l2-supply = <&vdd_ac_bat_reg>;
regulators {
tps65090_dcdc1_reg: dcdc1 {
regulator-name = "vdd-sys-5v0";
regulator-always-on;
regulator-boot-on;
};
tps65090_dcdc2_reg: dcdc2 {
regulator-name = "vdd-sys-3v3";
regulator-always-on;
regulator-boot-on;
};
dcdc3 {
regulator-name = "vdd-ao";
regulator-always-on;
regulator-boot-on;
};
fet1 {
regulator-name = "vdd-lcd-bl";
};
fet3 {
regulator-name = "vdd-modem-3v3";
};
fet4 {
regulator-name = "avdd-lcd";
};
fet5 {
regulator-name = "vdd-lvds";
};
fet6 {
regulator-name = "vdd-sd-slot";
regulator-always-on;
regulator-boot-on;
};
fet7 {
regulator-name = "vdd-com-3v3";
};
ldo1 {
regulator-name = "vdd-sby-5v0";
regulator-always-on;
regulator-boot-on;
};
ldo2 {
regulator-name = "vdd-sby-3v3";
regulator-always-on;
regulator-boot-on;
};
};
};
};
pmc {
nvidia,invert-interrupt;
};
sdhci@78000400 {
cd-gpios = <&gpio 170 1>; /* gpio PV2 */
bus-width = <4>;
status = "okay";
};
sdhci@78000600 {
bus-width = <8>;
status = "okay";
non-removable;
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
@ -30,4 +851,74 @@
clock-frequency = <32768>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vdd_ac_bat_reg: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "vdd_ac_bat";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
dvdd_ts_reg: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "dvdd_ts";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
enable-active-high;
gpio = <&gpio 61 0>; /* GPIO PH5 */
};
lcd_bl_en_reg: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "lcd_bl_en";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 58 0>; /* GPIO PH2 */
};
usb1_vbus_reg: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 108 0>; /* GPIO PN4 */
gpio-open-drain;
vin-supply = <&tps65090_dcdc1_reg>;
};
usb3_vbus_reg: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "usb2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 86 0>; /* GPIO PK6 */
gpio-open-drain;
vin-supply = <&tps65090_dcdc1_reg>;
};
vdd_hdmi_reg: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
regulator-name = "vdd_hdmi_5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 81 0>; /* GPIO PK1 */
vin-supply = <&tps65090_dcdc1_reg>;
};
};
};

240
arch/arm/boot/dts/tegra114.dtsi
View File

@ -4,6 +4,13 @@
compatible = "nvidia,tegra114";
interrupt-parent = <&gic>;
aliases {
serial0 = &uarta;
serial1 = &uartb;
serial2 = &uartc;
serial3 = &uartd;
};
gic: interrupt-controller {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
@ -33,6 +40,44 @@
#clock-cells = <1>;
};
apbdma: dma {
compatible = "nvidia,tegra114-apbdma";
reg = <0x6000a000 0x1400>;
interrupts = <0 104 0x04
0 105 0x04
0 106 0x04
0 107 0x04
0 108 0x04
0 109 0x04
0 110 0x04
0 111 0x04
0 112 0x04
0 113 0x04
0 114 0x04
0 115 0x04
0 116 0x04
0 117 0x04
0 118 0x04
0 119 0x04
0 128 0x04
0 129 0x04
0 130 0x04
0 131 0x04
0 132 0x04
0 133 0x04
0 134 0x04
0 135 0x04
0 136 0x04
0 137 0x04
0 138 0x04
0 139 0x04
0 140 0x04
0 141 0x04
0 142 0x04
0 143 0x04>;
clocks = <&tegra_car 34>;
};
ahb: ahb {
compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
reg = <0x6000c004 0x14c>;
@ -61,42 +106,189 @@
0x70003000 0x40c>; /* Mux registers */
};
serial@70006000 {
/*
* There are two serial driver i.e. 8250 based simple serial
* driver and APB DMA based serial driver for higher baudrate
* and performace. To enable the 8250 based driver, the compatible
* is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
* the APB DMA based serial driver, the comptible is
* "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
*/
uarta: serial@70006000 {
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = <0 36 0x04>;
nvidia,dma-request-selector = <&apbdma 8>;
status = "disabled";
clocks = <&tegra_car 6>;
};
serial@70006040 {
uartb: serial@70006040 {
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
interrupts = <0 37 0x04>;
nvidia,dma-request-selector = <&apbdma 9>;
status = "disabled";
clocks = <&tegra_car 192>;
};
serial@70006200 {
uartc: serial@70006200 {
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006200 0x100>;
reg-shift = <2>;
interrupts = <0 46 0x04>;
nvidia,dma-request-selector = <&apbdma 10>;
status = "disabled";
clocks = <&tegra_car 55>;
};
serial@70006300 {
uartd: serial@70006300 {
compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
reg = <0x70006300 0x100>;
reg-shift = <2>;
interrupts = <0 90 0x04>;
nvidia,dma-request-selector = <&apbdma 19>;
status = "disabled";
clocks = <&tegra_car 65>;
};
pwm: pwm {
compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
#pwm-cells = <2>;
clocks = <&tegra_car 17>;
status = "disabled";
};
i2c@7000c000 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c000 0x100>;
interrupts = <0 38 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 12>;
clock-names = "div-clk";
status = "disabled";
};
i2c@7000c400 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c400 0x100>;
interrupts = <0 84 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 54>;
clock-names = "div-clk";
status = "disabled";
};
i2c@7000c500 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c500 0x100>;
interrupts = <0 92 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 67>;
clock-names = "div-clk";
status = "disabled";
};
i2c@7000c700 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000c700 0x100>;
interrupts = <0 120 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 103>;
clock-names = "div-clk";
status = "disabled";
};
i2c@7000d000 {
compatible = "nvidia,tegra114-i2c";
reg = <0x7000d000 0x100>;
interrupts = <0 53 0x04>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 47>;
clock-names = "div-clk";
status = "disabled";
};
spi@7000d400 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d400 0x200>;
interrupts = <0 59 0x04>;
nvidia,dma-request-selector = <&apbdma 15>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 41>;
clock-names = "spi";
status = "disabled";
};
spi@7000d600 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d600 0x200>;
interrupts = <0 82 0x04>;
nvidia,dma-request-selector = <&apbdma 16>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 44>;
clock-names = "spi";
status = "disabled";
};
spi@7000d800 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000d800 0x200>;
interrupts = <0 83 0x04>;
nvidia,dma-request-selector = <&apbdma 17>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 46>;
clock-names = "spi";
status = "disabled";
};
spi@7000da00 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000da00 0x200>;
interrupts = <0 93 0x04>;
nvidia,dma-request-selector = <&apbdma 18>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 68>;
clock-names = "spi";
status = "disabled";
};
spi@7000dc00 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000dc00 0x200>;
interrupts = <0 94 0x04>;
nvidia,dma-request-selector = <&apbdma 27>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 104>;
clock-names = "spi";
status = "disabled";
};
spi@7000de00 {
compatible = "nvidia,tegra114-spi";
reg = <0x7000de00 0x200>;
interrupts = <0 79 0x04>;
nvidia,dma-request-selector = <&apbdma 28>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&tegra_car 105>;
clock-names = "spi";
status = "disabled";
};
rtc {
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
@ -104,6 +296,14 @@
clocks = <&tegra_car 4>;
};
kbc {
compatible = "nvidia,tegra114-kbc";
reg = <0x7000e200 0x100>;
interrupts = <0 85 0x04>;
clocks = <&tegra_car 36>;
status = "disabled";
};
pmc {
compatible = "nvidia,tegra114-pmc";
reg = <0x7000e400 0x400>;
@ -122,6 +322,38 @@
nvidia,ahb = <&ahb>;
};
sdhci@78000000 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000000 0x200>;
interrupts = <0 14 0x04>;
clocks = <&tegra_car 14>;
status = "disable";
};
sdhci@78000200 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000200 0x200>;
interrupts = <0 15 0x04>;
clocks = <&tegra_car 9>;
status = "disable";
};
sdhci@78000400 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000400 0x200>;
interrupts = <0 19 0x04>;
clocks = <&tegra_car 69>;
status = "disable";
};
sdhci@78000600 {
compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
reg = <0x78000600 0x200>;
interrupts = <0 31 0x04>;
clocks = <&tegra_car 15>;
status = "disable";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;

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