ARM: OMAP: OMAP2 dmtimer power management support
GPT1 will be set into non-posted mode, and the wakeup register is set for all timers. Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -161,7 +161,7 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
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{
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u32 l;
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if (timer != &dm_timers[0]) {
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if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
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omap_dm_timer_wait_for_reset(timer);
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}
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@ -170,6 +170,13 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
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/* Set to smart-idle mode */
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l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
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l |= 0x02 << 3;
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if (cpu_class_is_omap2() && timer == &dm_timers[0]) {
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/* Enable wake-up only for GPT1 on OMAP2 CPUs*/
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l |= 1 << 2;
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/* Non-posted mode */
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omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0);
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}
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omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
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}
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@ -431,6 +438,7 @@ void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
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unsigned int value)
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{
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omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
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omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
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}
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unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
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