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Merge remote-tracking branch 'net-next/master'

This commit is contained in:
Stefan Schmidt 2017-10-18 17:40:18 +02:00
parent d01174fcd2 b9f1f1ce86
commit 396665e832
1466 changed files with 53057 additions and 16208 deletions
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2
.mailmap
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@ -68,6 +68,8 @@ Jacob Shin <Jacob.Shin@amd.com>
James Bottomley <jejb@mulgrave.(none)>
James Bottomley <jejb@titanic.il.steeleye.com>
James E Wilson <wilson@specifix.com>
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
James Hogan <jhogan@kernel.org> <james@albanarts.com>
James Ketrenos <jketreno@io.(none)>
Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com>
<javier@osg.samsung.com> <javier.martinez@collabora.co.uk>

48
Documentation/ABI/testing/sysfs-bus-thunderbolt
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@ -110,3 +110,51 @@ Description: When new NVM image is written to the non-active NVM
is directly the status value from the DMA configuration
based mailbox before the device is power cycled. Writing
0 here clears the status.
What: /sys/bus/thunderbolt/devices/<xdomain>.<service>/key
Date: Jan 2018
KernelVersion: 4.15
Contact: thunderbolt-software@lists.01.org
Description: This contains name of the property directory the XDomain
service exposes. This entry describes the protocol in
question. Following directories are already reserved by
the Apple XDomain specification:
network: IP/ethernet over Thunderbolt
targetdm: Target disk mode protocol over Thunderbolt
extdisp: External display mode protocol over Thunderbolt
What: /sys/bus/thunderbolt/devices/<xdomain>.<service>/modalias
Date: Jan 2018
KernelVersion: 4.15
Contact: thunderbolt-software@lists.01.org
Description: Stores the same MODALIAS value emitted by uevent for
the XDomain service. Format: tbtsvc:kSpNvNrN
What: /sys/bus/thunderbolt/devices/<xdomain>.<service>/prtcid
Date: Jan 2018
KernelVersion: 4.15
Contact: thunderbolt-software@lists.01.org
Description: This contains XDomain protocol identifier the XDomain
service supports.
What: /sys/bus/thunderbolt/devices/<xdomain>.<service>/prtcvers
Date: Jan 2018
KernelVersion: 4.15
Contact: thunderbolt-software@lists.01.org
Description: This contains XDomain protocol version the XDomain
service supports.
What: /sys/bus/thunderbolt/devices/<xdomain>.<service>/prtcrevs
Date: Jan 2018
KernelVersion: 4.15
Contact: thunderbolt-software@lists.01.org
Description: This contains XDomain software version the XDomain
service supports.
What: /sys/bus/thunderbolt/devices/<xdomain>.<service>/prtcstns
Date: Jan 2018
KernelVersion: 4.15
Contact: thunderbolt-software@lists.01.org
Description: This contains XDomain service specific settings as
bitmask. Format: %x

2
Documentation/ABI/testing/sysfs-power
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@ -127,7 +127,7 @@ Description:
What; /sys/power/pm_trace_dev_match
Date: October 2010
Contact: James Hogan <james@albanarts.com>
Contact: James Hogan <jhogan@kernel.org>
Description:
The /sys/power/pm_trace_dev_match file contains the name of the
device associated with the last PM event point saved in the RTC

24
Documentation/admin-guide/thunderbolt.rst
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@ -197,3 +197,27 @@ information is missing.
To recover from this mode, one needs to flash a valid NVM image to the
host host controller in the same way it is done in the previous chapter.
Networking over Thunderbolt cable
---------------------------------
Thunderbolt technology allows software communication across two hosts
connected by a Thunderbolt cable.
It is possible to tunnel any kind of traffic over Thunderbolt link but
currently we only support Apple ThunderboltIP protocol.
If the other host is running Windows or macOS only thing you need to
do is to connect Thunderbolt cable between the two hosts, the
``thunderbolt-net`` is loaded automatically. If the other host is also
Linux you should load ``thunderbolt-net`` manually on one host (it does
not matter which one)::
# modprobe thunderbolt-net
This triggers module load on the other host automatically. If the driver
is built-in to the kernel image, there is no need to do anything.
The driver will create one virtual ethernet interface per Thunderbolt
port which are named like ``thunderbolt0`` and so on. From this point
you can either use standard userspace tools like ``ifconfig`` to
configure the interface or let your GUI to handle it automatically.

12
Documentation/core-api/workqueue.rst
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@ -39,8 +39,8 @@ up.
Although MT wq wasted a lot of resource, the level of concurrency
provided was unsatisfactory. The limitation was common to both ST and
MT wq albeit less severe on MT. Each wq maintained its own separate
worker pool. A MT wq could provide only one execution context per CPU
while a ST wq one for the whole system. Work items had to compete for
worker pool. An MT wq could provide only one execution context per CPU
while an ST wq one for the whole system. Work items had to compete for
those very limited execution contexts leading to various problems
including proneness to deadlocks around the single execution context.
@ -151,7 +151,7 @@ Application Programming Interface (API)
``alloc_workqueue()`` allocates a wq. The original
``create_*workqueue()`` functions are deprecated and scheduled for
removal. ``alloc_workqueue()`` takes three arguments - @``name``,
removal. ``alloc_workqueue()`` takes three arguments - ``@name``,
``@flags`` and ``@max_active``. ``@name`` is the name of the wq and
also used as the name of the rescuer thread if there is one.
@ -197,7 +197,7 @@ resources, scheduled and executed.
served by worker threads with elevated nice level.
Note that normal and highpri worker-pools don't interact with
each other. Each maintain its separate pool of workers and
each other. Each maintains its separate pool of workers and
implements concurrency management among its workers.
``WQ_CPU_INTENSIVE``
@ -249,8 +249,8 @@ unbound worker-pools and only one work item could be active at any given
time thus achieving the same ordering property as ST wq.
In the current implementation the above configuration only guarantees
ST behavior within a given NUMA node. Instead alloc_ordered_queue should
be used to achieve system wide ST behavior.
ST behavior within a given NUMA node. Instead ``alloc_ordered_queue()`` should
be used to achieve system-wide ST behavior.
Example Execution Scenarios

2
Documentation/cpu-freq/index.txt
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@ -32,8 +32,6 @@ cpufreq-stats.txt - General description of sysfs cpufreq stats.
index.txt - File index, Mailing list and Links (this document)
intel-pstate.txt - Intel pstate cpufreq driver specific file.
pcc-cpufreq.txt - PCC cpufreq driver specific file.

1
Documentation/device-mapper/dm-raid.txt
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@ -344,3 +344,4 @@ Version History
(wrong raid10_copies/raid10_format sequence)
1.11.1 Add raid4/5/6 journal write-back support via journal_mode option
1.12.1 fix for MD deadlock between mddev_suspend() and md_write_start() available
1.13.0 Fix dev_health status at end of "recover" (was 'a', now 'A')

2
Documentation/devicetree/bindings/clock/st,stm32h7-rcc.txt
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@ -32,7 +32,7 @@ Example:
compatible = "st,stm32h743-rcc", "st,stm32-rcc";
reg = <0x58024400 0x400>;
#reset-cells = <1>;
#clock-cells = <2>;
#clock-cells = <1>;
clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>;
st,syscfg = <&pwrcfg>;

28
Documentation/devicetree/bindings/leds/ams,as3645a.txt
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@ -15,11 +15,14 @@ Required properties
compatible : Must be "ams,as3645a".
reg : The I2C address of the device. Typically 0x30.
#address-cells : 1
#size-cells : 0
Required properties of the "flash" child node
=============================================
Required properties of the flash child node (0)
===============================================
reg: 0
flash-timeout-us: Flash timeout in microseconds. The value must be in
the range [100000, 850000] and divisible by 50000.
flash-max-microamp: Maximum flash current in microamperes. Has to be
@ -33,20 +36,21 @@ ams,input-max-microamp: Maximum flash controller input current. The
and divisible by 50000.
Optional properties of the "flash" child node
=============================================
Optional properties of the flash child node
===========================================
label : The label of the flash LED.
Required properties of the "indicator" child node
=================================================
Required properties of the indicator child node (1)
===================================================
reg: 1
led-max-microamp: Maximum indicator current. The allowed values are
2500, 5000, 7500 and 10000.
Optional properties of the "indicator" child node
=================================================
Optional properties of the indicator child node
===============================================
label : The label of the indicator LED.
@ -55,16 +59,20 @@ Example
=======
as3645a@30 {
#address-cells: 1
#size-cells: 0
reg = <0x30>;
compatible = "ams,as3645a";
flash {
flash@0 {
reg = <0x0>;
flash-timeout-us = <150000>;
flash-max-microamp = <320000>;
led-max-microamp = <60000>;
ams,input-max-microamp = <1750000>;
label = "as3645a:flash";
};
indicator {
indicator@1 {
reg = <0x1>;
led-max-microamp = <10000>;
label = "as3645a:indicator";
};

12
Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.txt
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@ -16,11 +16,13 @@ Required Properties:
- clocks:
Array of clocks required for SDHC.
Require at least input clock for Xenon IP core.
Require at least input clock for Xenon IP core. For Armada AP806 and
CP110, the AXI clock is also mandatory.
- clock-names:
Array of names corresponding to clocks property.
The input clock for Xenon IP core should be named as "core".
The input clock for the AXI bus must be named as "axi".
- reg:
* For "marvell,armada-3700-sdhci", two register areas.
@ -106,8 +108,8 @@ Example:
compatible = "marvell,armada-ap806-sdhci";
reg = <0xaa0000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
clocks = <&emmc_clk>;
clock-names = "core";
clocks = <&emmc_clk>,<&axi_clk>;
clock-names = "core", "axi";
bus-width = <4>;
marvell,xenon-phy-slow-mode;
marvell,xenon-tun-count = <11>;
@ -126,8 +128,8 @@ Example:
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
vqmmc-supply = <&sd_vqmmc_regulator>;
vmmc-supply = <&sd_vmmc_regulator>;
clocks = <&sdclk>;
clock-names = "core";
clocks = <&sdclk>, <&axi_clk>;
clock-names = "core", "axi";
bus-width = <4>;
marvell,xenon-tun-count = <9>;
};

10
Documentation/devicetree/bindings/net/marvell-pp2.txt
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@ -21,8 +21,9 @@ Required properties:
- main controller clock (for both armada-375-pp2 and armada-7k-pp2)
- GOP clock (for both armada-375-pp2 and armada-7k-pp2)
- MG clock (only for armada-7k-pp2)
- clock-names: names of used clocks, must be "pp_clk", "gop_clk" and
"mg_clk" (the latter only for armada-7k-pp2).
- AXI clock (only for armada-7k-pp2)
- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk"
and "axi_clk" (the 2 latter only for armada-7k-pp2).
The ethernet ports are represented by subnodes. At least one port is
required.
@ -78,8 +79,9 @@ Example for marvell,armada-7k-pp2:
cpm_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
clock-names = "pp_clk", "gop_clk", "gp_clk";
clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>,
<&cpm_syscon0 1 5>, <&cpm_syscon0 1 18>;
clock-names = "pp_clk", "gop_clk", "gp_clk", "axi_clk";
eth0: eth0 {
interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,

1
Documentation/devicetree/bindings/net/rockchip-dwmac.txt
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@ -4,6 +4,7 @@ The device node has following properties.
Required properties:
- compatible: should be "rockchip,<name>-gamc"
"rockchip,rk3128-gmac": found on RK312x SoCs
"rockchip,rk3228-gmac": found on RK322x SoCs
"rockchip,rk3288-gmac": found on RK3288 SoCs
"rockchip,rk3328-gmac": found on RK3328 SoCs

28
Documentation/devicetree/bindings/reset/snps,hsdk-reset.txt Normal file
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@ -0,0 +1,28 @@
Binding for the Synopsys HSDK reset controller
This binding uses the common reset binding[1].
[1] Documentation/devicetree/bindings/reset/reset.txt
Required properties:
- compatible: should be "snps,hsdk-reset".
- reg: should always contain 2 pairs address - length: first for reset
configuration register and second for corresponding SW reset and status bits
register.
- #reset-cells: from common reset binding; Should always be set to 1.
Example:
reset: reset@880 {
compatible = "snps,hsdk-reset";
#reset-cells = <1>;
reg = <0x8A0 0x4>, <0xFF0 0x4>;
};
Specifying reset lines connected to IP modules:
ethernet@.... {
....
resets = <&reset HSDK_V1_ETH_RESET>;
....
};
The index could be found in <dt-bindings/reset/snps,hsdk-reset.h>

6
Documentation/devicetree/bindings/security/tpm/tpm-i2c.txt
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@ -8,6 +8,12 @@ Required properties:
the firmware event log
- linux,sml-size : size of the memory allocated for the firmware event log
Optional properties:
- powered-while-suspended: present when the TPM is left powered on between
suspend and resume (makes the suspend/resume
callbacks do nothing).
Example (for OpenPower Systems with Nuvoton TPM 2.0 on I2C)
----------------------------------------------------------

2
Documentation/devicetree/bindings/serial/renesas,sci-serial.txt
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@ -41,6 +41,8 @@ Required properties:
- "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART.
- "renesas,scif-r8a7796" for R8A7796 (R-Car M3-W) SCIF compatible UART.
- "renesas,hscif-r8a7796" for R8A7796 (R-Car M3-W) HSCIF compatible UART.
- "renesas,scif-r8a77970" for R8A77970 (R-Car V3M) SCIF compatible UART.
- "renesas,hscif-r8a77970" for R8A77970 (R-Car V3M) HSCIF compatible UART.
- "renesas,scif-r8a77995" for R8A77995 (R-Car D3) SCIF compatible UART.
- "renesas,hscif-r8a77995" for R8A77995 (R-Car D3) HSCIF compatible UART.
- "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.

2
Documentation/devicetree/bindings/vendor-prefixes.txt
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@ -3,8 +3,8 @@ Device tree binding vendor prefix registry. Keep list in alphabetical order.
This isn't an exhaustive list, but you should add new prefixes to it before
using them to avoid name-space collisions.
abcn Abracon Corporation
abilis Abilis Systems
abracon Abracon Corporation
actions Actions Semiconductor Co., Ltd.
active-semi Active-Semi International Inc
ad Avionic Design GmbH

3
Documentation/driver-api/80211/cfg80211.rst
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@ -299,9 +299,6 @@ Data path helpers
.. kernel-doc:: include/net/cfg80211.h
:functions: ieee80211_data_to_8023
.. kernel-doc:: include/net/cfg80211.h
:functions: ieee80211_data_from_8023
.. kernel-doc:: include/net/cfg80211.h
:functions: ieee80211_amsdu_to_8023s

7
Documentation/driver-model/driver.txt
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@ -196,12 +196,13 @@ struct driver_attribute {
};
Device drivers can export attributes via their sysfs directories.
Drivers can declare attributes using a DRIVER_ATTR macro that works
identically to the DEVICE_ATTR macro.
Drivers can declare attributes using a DRIVER_ATTR_RW and DRIVER_ATTR_RO
macro that works identically to the DEVICE_ATTR_RW and DEVICE_ATTR_RO
macros.
Example:
DRIVER_ATTR(debug,0644,show_debug,store_debug);
DRIVER_ATTR_RW(debug);
This is equivalent to declaring:

5
Documentation/filesystems/overlayfs.txt
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@ -210,8 +210,11 @@ path as another overlay mount and it may use a lower layer path that is
beneath or above the path of another overlay lower layer path.
Using an upper layer path and/or a workdir path that are already used by
another overlay mount is not allowed and will fail with EBUSY. Using
another overlay mount is not allowed and may fail with EBUSY. Using
partially overlapping paths is not allowed but will not fail with EBUSY.
If files are accessed from two overlayfs mounts which share or overlap the
upper layer and/or workdir path the behavior of the overlay is undefined,
though it will not result in a crash or deadlock.
Mounting an overlay using an upper layer path, where the upper layer path
was previously used by another mounted overlay in combination with a

3
Documentation/filesystems/sysfs.txt
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@ -366,7 +366,8 @@ struct driver_attribute {
Declaring:
DRIVER_ATTR(_name, _mode, _show, _store)
DRIVER_ATTR_RO(_name)
DRIVER_ATTR_RW(_name)
Creation/Removal:

1
Documentation/i2c/busses/i2c-i801
View File

@ -36,6 +36,7 @@ Supported adapters:
* Intel Gemini Lake (SOC)
* Intel Cannon Lake-H (PCH)
* Intel Cannon Lake-LP (PCH)
* Intel Cedar Fork (PCH)
Datasheets: Publicly available at the Intel website
On Intel Patsburg and later chipsets, both the normal host SMBus controller

2
Documentation/networking/bonding.txt
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@ -2387,7 +2387,7 @@ broadcast: Like active-backup, there is not much advantage to this
and packet type ID), so in a "gatewayed" configuration, all
outgoing traffic will generally use the same device. Incoming
traffic may also end up on a single device, but that is
dependent upon the balancing policy of the peer's 8023.ad
dependent upon the balancing policy of the peer's 802.3ad
implementation. In a "local" configuration, traffic will be
distributed across the devices in the bond.

8
Documentation/networking/netvsc.txt
View File

@ -19,12 +19,12 @@ Features
Receive Side Scaling
--------------------
Hyper-V supports receive side scaling. For TCP, packets are
distributed among available queues based on IP address and port
Hyper-V supports receive side scaling. For TCP & UDP, packets can
be distributed among available queues based on IP address and port
number.
For UDP, we can switch UDP hash level between L3 and L4 by ethtool
command. UDP over IPv4 and v6 can be set differently. The default
For TCP & UDP, we can switch hash level between L3 and L4 by ethtool
command. TCP/UDP over IPv4 and v6 can be set differently. The default
hash level is L4. We currently only allow switching TX hash level
from within the guests.

30
Documentation/networking/regulatory.txt
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@ -19,6 +19,14 @@ core regulatory domain all wireless devices should adhere to.
How to get regulatory domains to the kernel
-------------------------------------------
When the regulatory domain is first set up, the kernel will request a
database file (regulatory.db) containing all the regulatory rules. It
will then use that database when it needs to look up the rules for a
given country.
How to get regulatory domains to the kernel (old CRDA solution)
---------------------------------------------------------------
Userspace gets a regulatory domain in the kernel by having
a userspace agent build it and send it via nl80211. Only
expected regulatory domains will be respected by the kernel.
@ -192,23 +200,5 @@ Then in some part of your code after your wiphy has been registered:
Statically compiled regulatory database
---------------------------------------
In most situations the userland solution using CRDA as described
above is the preferred solution. However in some cases a set of
rules built into the kernel itself may be desirable. To account
for this situation, a configuration option has been provided
(i.e. CONFIG_CFG80211_INTERNAL_REGDB). With this option enabled,
the wireless database information contained in net/wireless/db.txt is
used to generate a data structure encoded in net/wireless/regdb.c.
That option also enables code in net/wireless/reg.c which queries
the data in regdb.c as an alternative to using CRDA.
The file net/wireless/db.txt should be kept up-to-date with the db.txt
file available in the git repository here:
git://git.kernel.org/pub/scm/linux/kernel/git/sforshee/wireless-regdb.git
Again, most users in most situations should be using the CRDA package
provided with their distribution, and in most other situations users
should be building and using CRDA on their own rather than using
this option. If you are not absolutely sure that you should be using
CONFIG_CFG80211_INTERNAL_REGDB then _DO_NOT_USE_IT_.
When a database should be fixed into the kernel, it can be provided as a
firmware file at build time that is then linked into the kernel.

57
MAINTAINERS
View File

@ -2725,7 +2725,7 @@ F: net/core/filter.c
F: net/sched/act_bpf.c
F: net/sched/cls_bpf.c
F: samples/bpf/
F: tools/net/bpf*
F: tools/bpf/
F: tools/testing/selftests/bpf/
BROADCOM B44 10/100 ETHERNET DRIVER
@ -3329,17 +3329,22 @@ S: Maintained
F: drivers/auxdisplay/cfag12864bfb.c
F: include/linux/cfag12864b.h
CFG80211 and NL80211
802.11 (including CFG80211/NL80211)
M: Johannes Berg <johannes@sipsolutions.net>
L: linux-wireless@vger.kernel.org
W: http://wireless.kernel.org/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
S: Maintained
F: net/wireless/
F: include/uapi/linux/nl80211.h
F: include/linux/ieee80211.h
F: include/net/wext.h
F: include/net/cfg80211.h
F: net/wireless/*
X: net/wireless/wext*
F: include/net/iw_handler.h
F: include/net/ieee80211_radiotap.h
F: Documentation/driver-api/80211/cfg80211.rst
F: Documentation/networking/regulatory.txt
CHAR and MISC DRIVERS
M: Arnd Bergmann <arnd@arndb.de>
@ -5259,7 +5264,8 @@ S: Maintained
F: drivers/iommu/exynos-iommu.c
EZchip NPS platform support
M: Noam Camus <noamc@ezchip.com>
M: Elad Kanfi <eladkan@mellanox.com>
M: Vineet Gupta <vgupta@synopsys.com>
S: Supported
F: arch/arc/plat-eznps
F: arch/arc/boot/dts/eznps.dts
@ -6738,7 +6744,7 @@ F: Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt
F: drivers/auxdisplay/img-ascii-lcd.c
IMGTEC IR DECODER DRIVER
M: James Hogan <james.hogan@imgtec.com>
M: James Hogan <jhogan@kernel.org>
S: Maintained
F: drivers/media/rc/img-ir/
@ -7562,7 +7568,7 @@ F: arch/arm64/include/asm/kvm*
F: arch/arm64/kvm/
KERNEL VIRTUAL MACHINE FOR MIPS (KVM/mips)
M: James Hogan <james.hogan@imgtec.com>
M: James Hogan <jhogan@kernel.org>
L: linux-mips@linux-mips.org
S: Supported
F: arch/mips/include/uapi/asm/kvm*
@ -8207,6 +8213,7 @@ F: Documentation/networking/mac80211-injection.txt
F: include/net/mac80211.h
F: net/mac80211/
F: drivers/net/wireless/mac80211_hwsim.[ch]
F: Documentation/networking/mac80211_hwsim/README
MAILBOX API
M: Jassi Brar <jassisinghbrar@gmail.com>
@ -8264,6 +8271,12 @@ L: libertas-dev@lists.infradead.org
S: Orphan
F: drivers/net/wireless/marvell/libertas/
MARVELL MACCHIATOBIN SUPPORT
M: Russell King <rmk@armlinux.org.uk>
L: linux-arm-kernel@lists.infradead.org
S: Maintained
F: arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
MARVELL MV643XX ETHERNET DRIVER
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
L: netdev@vger.kernel.org
@ -8597,6 +8610,12 @@ M: Sean Wang <sean.wang@mediatek.com>
S: Maintained
F: drivers/media/rc/mtk-cir.c
MEDIATEK PMIC LED DRIVER
M: Sean Wang <sean.wang@mediatek.com>
S: Maintained
F: drivers/leds/leds-mt6323.c
F: Documentation/devicetree/bindings/leds/leds-mt6323.txt
MEDIATEK ETHERNET DRIVER
M: Felix Fietkau <nbd@openwrt.org>
M: John Crispin <john@phrozen.org>
@ -8879,7 +8898,7 @@ F: Documentation/devicetree/bindings/media/meson-ao-cec.txt
T: git git://linuxtv.org/media_tree.git
METAG ARCHITECTURE
M: James Hogan <james.hogan@imgtec.com>
M: James Hogan <jhogan@kernel.org>
L: linux-metag@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/metag.git
S: Odd Fixes
@ -9348,7 +9367,7 @@ NETWORK BLOCK DEVICE (NBD)
M: Josef Bacik <jbacik@fb.com>
S: Maintained
L: linux-block@vger.kernel.org
L: nbd-general@lists.sourceforge.net
L: nbd@other.debian.org
F: Documentation/blockdev/nbd.txt
F: drivers/block/nbd.c
F: include/uapi/linux/nbd.h
@ -9416,7 +9435,6 @@ F: include/uapi/linux/in.h
F: include/uapi/linux/net.h
F: include/uapi/linux/netdevice.h
F: include/uapi/linux/net_namespace.h
F: tools/net/
F: tools/testing/selftests/net/
F: lib/random32.c
@ -11480,6 +11498,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211-next.git
S: Maintained
F: Documentation/rfkill.txt
F: Documentation/ABI/stable/sysfs-class-rfkill
F: net/rfkill/
RHASHTABLE
@ -12925,9 +12944,9 @@ F: drivers/mmc/host/dw_mmc*
SYNOPSYS HSDK RESET CONTROLLER DRIVER
M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
S: Supported
F: drivers/reset/reset-hsdk-v1.c
F: include/dt-bindings/reset/snps,hsdk-v1-reset.h
F: Documentation/devicetree/bindings/reset/snps,hsdk-v1-reset.txt
F: drivers/reset/reset-hsdk.c
F: include/dt-bindings/reset/snps,hsdk-reset.h
F: Documentation/devicetree/bindings/reset/snps,hsdk-reset.txt
SYSTEM CONFIGURATION (SYSCON)
M: Lee Jones <lee.jones@linaro.org>
@ -13278,6 +13297,15 @@ M: Mika Westerberg <mika.westerberg@linux.intel.com>
M: Yehezkel Bernat <yehezkel.bernat@intel.com>
S: Maintained
F: drivers/thunderbolt/
F: include/linux/thunderbolt.h
THUNDERBOLT NETWORK DRIVER
M: Michael Jamet <michael.jamet@intel.com>
M: Mika Westerberg <mika.westerberg@linux.intel.com>
M: Yehezkel Bernat <yehezkel.bernat@intel.com>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/thunderbolt.c
THUNDERX GPIO DRIVER
M: David Daney <david.daney@cavium.com>
@ -14266,12 +14294,15 @@ S: Maintained
F: include/linux/virtio_vsock.h
F: include/uapi/linux/virtio_vsock.h
F: include/uapi/linux/vsockmon.h
F: include/uapi/linux/vm_sockets_diag.h
F: net/vmw_vsock/diag.c
F: net/vmw_vsock/af_vsock_tap.c
F: net/vmw_vsock/virtio_transport_common.c
F: net/vmw_vsock/virtio_transport.c
F: drivers/net/vsockmon.c
F: drivers/vhost/vsock.c
F: drivers/vhost/vsock.h
F: tools/testing/vsock/
VIRTIO CONSOLE DRIVER
M: Amit Shah <amit@kernel.org>

6
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 4
PATCHLEVEL = 14
SUBLEVEL = 0
EXTRAVERSION = -rc1
EXTRAVERSION = -rc4
NAME = Fearless Coyote
# *DOCUMENTATION*
@ -1172,11 +1172,11 @@ headers_check: headers_install
PHONY += kselftest
kselftest:
$(Q)$(MAKE) -C tools/testing/selftests run_tests
$(Q)$(MAKE) -C $(srctree)/tools/testing/selftests run_tests
PHONY += kselftest-clean
kselftest-clean:
$(Q)$(MAKE) -C tools/testing/selftests clean
$(Q)$(MAKE) -C $(srctree)/tools/testing/selftests clean
PHONY += kselftest-merge
kselftest-merge:

3
arch/Kconfig
View File

@ -937,9 +937,6 @@ config STRICT_MODULE_RWX
and non-text memory will be made non-executable. This provides
protection against certain security exploits (e.g. writing to text)
config ARCH_WANT_RELAX_ORDER
bool
config ARCH_HAS_REFCOUNT
bool
help

1
arch/alpha/include/asm/mmu_context.h
View File

@ -8,6 +8,7 @@
*/
#include <linux/mm_types.h>
#include <linux/sched.h>
#include <asm/machvec.h>
#include <asm/compiler.h>

2
arch/arc/Kconfig
View File

@ -24,7 +24,7 @@ config ARC
select GENERIC_SMP_IDLE_THREAD
select HAVE_ARCH_KGDB
select HAVE_ARCH_TRACEHOOK
select HAVE_FUTEX_CMPXCHG
select HAVE_FUTEX_CMPXCHG if FUTEX
select HAVE_IOREMAP_PROT
select HAVE_KPROBES
select HAVE_KRETPROBES

2
arch/arc/Makefile
View File

@ -6,8 +6,6 @@
# published by the Free Software Foundation.
#
UTS_MACHINE := arc
ifeq ($(CROSS_COMPILE),)
ifndef CONFIG_CPU_BIG_ENDIAN
CROSS_COMPILE := arc-linux-

9
arch/arc/boot/dts/axs10x_mb.dtsi
View File

@ -44,7 +44,14 @@
mmcclk: mmcclk {
compatible = "fixed-clock";
clock-frequency = <50000000>;
/*
* DW sdio controller has external ciu clock divider
* controlled via register in SDIO IP. It divides
* sdio_ref_clk (which comes from CGU) by 16 for
* default. So default mmcclk clock (which comes
* to sdk_in) is 25000000 Hz.
*/
clock-frequency = <25000000>;
#clock-cells = <0>;
};

32
arch/arc/boot/dts/hsdk.dts
View File

@ -12,6 +12,7 @@
/dts-v1/;
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/reset/snps,hsdk-reset.h>
/ {
model = "snps,hsdk";
@ -57,10 +58,10 @@
};
};
core_clk: core-clk {
input_clk: input-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <500000000>;
clock-frequency = <33333333>;
};
cpu_intc: cpu-interrupt-controller {
@ -102,6 +103,19 @@
ranges = <0x00000000 0xf0000000 0x10000000>;
cgu_rst: reset-controller@8a0 {
compatible = "snps,hsdk-reset";
#reset-cells = <1>;
reg = <0x8A0 0x4>, <0xFF0 0x4>;
};
core_clk: core-clk@0 {
compatible = "snps,hsdk-core-pll-clock";
reg = <0x00 0x10>, <0x14B8 0x4>;
#clock-cells = <0>;
clocks = <&input_clk>;
};
serial: serial@5000 {
compatible = "snps,dw-apb-uart";
reg = <0x5000 0x100>;
@ -120,7 +134,17 @@
mmcclk_ciu: mmcclk-ciu {
compatible = "fixed-clock";
clock-frequency = <100000000>;
/*
* DW sdio controller has external ciu clock divider
* controlled via register in SDIO IP. Due to its
* unexpected default value (it should devide by 1
* but it devides by 8) SDIO IP uses wrong clock and
* works unstable (see STAR 9001204800)
* So add temporary fix and change clock frequency
* from 100000000 to 12500000 Hz until we fix dw sdio
* driver itself.
*/
clock-frequency = <12500000>;
#clock-cells = <0>;
};
@ -141,6 +165,8 @@
clocks = <&gmacclk>;
clock-names = "stmmaceth";
phy-handle = <&phy0>;
resets = <&cgu_rst HSDK_ETH_RESET>;
reset-names = "stmmaceth";
mdio {
#address-cells = <1>;

2
arch/arc/configs/axs101_defconfig
View File

@ -105,7 +105,7 @@ CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set

2
arch/arc/configs/axs103_defconfig
View File

@ -104,7 +104,7 @@ CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set

2
arch/arc/configs/axs103_smp_defconfig
View File

@ -107,7 +107,7 @@ CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set

2
arch/arc/configs/haps_hs_smp_defconfig
View File

@ -84,5 +84,5 @@ CONFIG_TMPFS=y
CONFIG_NFS_FS=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
# CONFIG_DEBUG_PREEMPT is not set

3
arch/arc/configs/hsdk_defconfig
View File

@ -63,6 +63,7 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_DW=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_RESET_HSDK=y
CONFIG_EXT3_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
@ -72,7 +73,7 @@ CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set

2
arch/arc/configs/vdk_hs38_defconfig
View File

@ -94,7 +94,7 @@ CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set

2
arch/arc/configs/vdk_hs38_smp_defconfig
View File

@ -98,7 +98,7 @@ CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_LOCKUP_DETECTOR=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set

11
arch/arc/include/asm/arcregs.h
View File

@ -98,6 +98,7 @@
/* Auxiliary registers */
#define AUX_IDENTITY 4
#define AUX_EXEC_CTRL 8
#define AUX_INTR_VEC_BASE 0x25
#define AUX_VOL 0x5e
@ -135,12 +136,12 @@ struct bcr_identity {
#endif
};
struct bcr_isa {
struct bcr_isa_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
pad1:11, atomic1:1, ver:8;
pad1:12, ver:8;
#else
unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1,
unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
ldd:1, pad2:4, div_rem:4;
#endif
};
@ -263,13 +264,13 @@ struct cpuinfo_arc {
struct cpuinfo_arc_mmu mmu;
struct cpuinfo_arc_bpu bpu;
struct bcr_identity core;
struct bcr_isa isa;
struct bcr_isa_arcv2 isa;
const char *details, *name;
unsigned int vec_base;
struct cpuinfo_arc_ccm iccm, dccm;
struct {
unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
fpu_sp:1, fpu_dp:1, pad2:6,
fpu_sp:1, fpu_dp:1, dual_iss_enb:1, dual_iss_exist:1, pad2:4,
debug:1, ap:1, smart:1, rtt:1, pad3:4,
timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
} extn;

32
arch/arc/kernel/setup.c
View File

@ -51,6 +51,7 @@ static const struct id_to_str arc_cpu_rel[] = {
{ 0x51, "R2.0" },
{ 0x52, "R2.1" },
{ 0x53, "R3.0" },
{ 0x54, "R4.0" },
#endif
{ 0x00, NULL }
};
@ -62,6 +63,7 @@ static const struct id_to_str arc_cpu_nm[] = {
#else
{ 0x40, "ARC EM" },
{ 0x50, "ARC HS38" },
{ 0x54, "ARC HS48" },
#endif
{ 0x00, "Unknown" }
};
@ -119,11 +121,11 @@ static void read_arc_build_cfg_regs(void)
struct bcr_generic bcr;
struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
const struct id_to_str *tbl;
struct bcr_isa_arcv2 isa;
FIX_PTR(cpu);
READ_BCR(AUX_IDENTITY, cpu->core);
READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) {
if (cpu->core.family == tbl->id) {
@ -133,7 +135,7 @@ static void read_arc_build_cfg_regs(void)
}
for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) {
if ((cpu->core.family & 0xF0) == tbl->id)
if ((cpu->core.family & 0xF4) == tbl->id)
break;
}
cpu->name = tbl->str;
@ -192,6 +194,14 @@ static void read_arc_build_cfg_regs(void)
cpu->bpu.full = bpu.ft;
cpu->bpu.num_cache = 256 << bpu.bce;
cpu->bpu.num_pred = 2048 << bpu.pte;
if (cpu->core.family >= 0x54) {
unsigned int exec_ctrl;
READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
cpu->extn.dual_iss_exist = 1;
cpu->extn.dual_iss_enb = exec_ctrl & 1;
}
}
READ_BCR(ARC_REG_AP_BCR, bcr);
@ -205,18 +215,25 @@ static void read_arc_build_cfg_regs(void)
cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt;
READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
/* some hacks for lack of feature BCR info in old ARC700 cores */
if (is_isa_arcompact()) {
if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */
if (!isa.ver) /* ISA BCR absent, use Kconfig info */
cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
else
cpu->isa.atomic = cpu->isa.atomic1;
else {
/* ARC700_BUILD only has 2 bits of isa info */
struct bcr_generic bcr = *(struct bcr_generic *)&isa;
cpu->isa.atomic = bcr.info & 1;
}
cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
/* there's no direct way to distinguish 750 vs. 770 */
if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
cpu->name = "ARC750";
} else {
cpu->isa = isa;
}
}
@ -232,10 +249,11 @@ static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
"\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
core->family, core->cpu_id, core->chip_id);
n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s\n",
n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
cpu_id, cpu->name, cpu->details,
is_isa_arcompact() ? "ARCompact" : "ARCv2",
IS_AVAIL1(cpu->isa.be, "[Big-Endian]"));
IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
IS_AVAIL3(cpu->extn.dual_iss_exist, cpu->extn.dual_iss_enb, " Dual-Issue"));
n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",
IS_AVAIL1(cpu->extn.timer0, "Timer0 "),

7
arch/arc/plat-axs10x/axs10x.c
View File

@ -111,6 +111,13 @@ static void __init axs10x_early_init(void)
axs10x_enable_gpio_intc_wire();
/*
* Reset ethernet IP core.
* TODO: get rid of this quirk after axs10x reset driver (or simple
* reset driver) will be available in upstream.
*/
iowrite32((1 << 5), (void __iomem *) CREG_MB_SW_RESET);
scnprintf(mb, 32, "MainBoard v%d", mb_rev);
axs10x_print_board_ver(CREG_MB_VER, mb);
}

3
arch/arc/plat-hsdk/Kconfig
View File

@ -6,4 +6,5 @@
#
menuconfig ARC_SOC_HSDK
bool "ARC HS Development Kit SOC"
bool "ARC HS Development Kit SOC"
select CLK_HSDK

42
arch/arc/plat-hsdk/platform.c
View File

@ -38,6 +38,42 @@ static void __init hsdk_init_per_cpu(unsigned int cpu)
#define CREG_PAE (CREG_BASE + 0x180)
#define CREG_PAE_UPDATE (CREG_BASE + 0x194)
#define CREG_CORE_IF_CLK_DIV (CREG_BASE + 0x4B8)
#define CREG_CORE_IF_CLK_DIV_2 0x1
#define CGU_BASE ARC_PERIPHERAL_BASE
#define CGU_PLL_STATUS (ARC_PERIPHERAL_BASE + 0x4)
#define CGU_PLL_CTRL (ARC_PERIPHERAL_BASE + 0x0)
#define CGU_PLL_STATUS_LOCK BIT(0)
#define CGU_PLL_STATUS_ERR BIT(1)
#define CGU_PLL_CTRL_1GHZ 0x3A10
#define HSDK_PLL_LOCK_TIMEOUT 500
#define HSDK_PLL_LOCKED() \
!!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK)
#define HSDK_PLL_ERR() \
!!(ioread32((void __iomem *) CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR)
static void __init hsdk_set_cpu_freq_1ghz(void)
{
u32 timeout = HSDK_PLL_LOCK_TIMEOUT;
/*
* As we set cpu clock which exceeds 500MHz, the divider for the interface
* clock must be programmed to div-by-2.
*/
iowrite32(CREG_CORE_IF_CLK_DIV_2, (void __iomem *) CREG_CORE_IF_CLK_DIV);
/* Set cpu clock to 1GHz */
iowrite32(CGU_PLL_CTRL_1GHZ, (void __iomem *) CGU_PLL_CTRL);
while (!HSDK_PLL_LOCKED() && timeout--)
cpu_relax();
if (!HSDK_PLL_LOCKED() || HSDK_PLL_ERR())
pr_err("Failed to setup CPU frequency to 1GHz!");
}
static void __init hsdk_init_early(void)
{
/*
@ -52,6 +88,12 @@ static void __init hsdk_init_early(void)
/* Really apply settings made above */
writel(1, (void __iomem *) CREG_PAE_UPDATE);
/*
* Setup CPU frequency to 1GHz.
* TODO: remove it after smart hsdk pll driver will be introduced.
*/
hsdk_set_cpu_freq_1ghz();
}
static const char *hsdk_compat[] __initconst = {

2
arch/arm/boot/dts/am33xx.dtsi
View File

@ -36,6 +36,8 @@
phy1 = &usb1_phy;
ethernet0 = &cpsw_emac0;
ethernet1 = &cpsw_emac1;
spi0 = &spi0;
spi1 = &spi1;
};
cpus {

6
arch/arm/boot/dts/am43x-epos-evm.dts
View File

@ -388,6 +388,7 @@
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
slaves = <1>;
};
&davinci_mdio {
@ -402,11 +403,6 @@
phy-mode = "rmii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "rmii";
};
&phy_sel {
rmii-clock-ext;
};

19
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
View File

@ -67,7 +67,10 @@
usb1: ohci@00400000 {
num-ports = <3>;
atmel,vbus-gpio = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>;
atmel,vbus-gpio = <0 /* &pioA PIN_PD20 GPIO_ACTIVE_HIGH */
&pioA PIN_PA27 GPIO_ACTIVE_HIGH
0
>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
@ -120,7 +123,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus2_uart>;
atmel,use-dma-rx;
atmel-use-dma-tx;
atmel,use-dma-tx;
status = "okay";
};
@ -178,7 +181,7 @@
uart4: serial@fc00c000 {
atmel,use-dma-rx;
atmel,use-dma-tx;
pinctrl-name = "default";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus1_uart>;
status = "okay";
};
@ -330,7 +333,7 @@
};
pinctrl_led_gpio_default: led_gpio_default {
pinmux = <PIN_PA27__GPIO>,
pinmux = <PIN_PA10__GPIO>,
<PIN_PB1__GPIO>,
<PIN_PA31__GPIO>;
bias-pull-up;
@ -396,7 +399,7 @@
};
pinctrl_usb_default: usb_default {
pinmux = <PIN_PA10__GPIO>,
pinmux = <PIN_PA27__GPIO>,
<PIN_PD19__GPIO>;
bias-disable;
};
@ -520,17 +523,17 @@
red {
label = "red";
gpios = <&pioA PIN_PA27 GPIO_ACTIVE_LOW>;
gpios = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>;
};
green {
label = "green";
gpios = <&pioA PIN_PB1 GPIO_ACTIVE_LOW>;
gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>;
};
blue {
label = "blue";
gpios = <&pioA PIN_PA31 GPIO_ACTIVE_LOW>;
gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};

7
arch/arm/boot/dts/da850-evm.dts
View File

@ -15,6 +15,13 @@
compatible = "ti,da850-evm", "ti,da850";
model = "DA850/AM1808/OMAP-L138 EVM";
aliases {
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
ethernet0 = &eth0;
};
soc@1c00000 {
pmx_core: pinmux@14120 {
status = "okay";

2
arch/arm/boot/dts/dra7xx-clocks.dtsi
View File

@ -1817,6 +1817,8 @@
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
ti,bit-shift = <24>;
reg = <0x1868>;
assigned-clocks = <&mcasp3_ahclkx_mux>;
assigned-clock-parents = <&abe_24m_fclk>;
};
mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {

11
arch/arm/boot/dts/omap3-n900.dts
View File

@ -144,15 +144,6 @@
io-channel-names = "temp", "bsi", "vbat";
};
rear_camera: camera@0 {
compatible = "linux,camera";
module {
model = "TCM8341MD";
sensor = <&cam1>;
};
};
pwm9: dmtimer-pwm {
compatible = "ti,omap-dmtimer-pwm";
#pwm-cells = <3>;
@ -189,10 +180,8 @@
clock-lanes = <1>;
data-lanes = <0>;
lane-polarity = <0 0>;
clock-inv = <0>;
/* Select strobe = <1> for back camera, <0> for front camera */
strobe = <1>;
crc = <0>;
};
};
};

10
arch/arm/boot/dts/omap3-n950-n9.dtsi
View File

@ -267,15 +267,19 @@
clock-frequency = <400000>;
as3645a@30 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30>;
compatible = "ams,as3645a";
flash {
flash@0 {
reg = <0x0>;
flash-timeout-us = <150000>;
flash-max-microamp = <320000>;
led-max-microamp = <60000>;
peak-current-limit = <1750000>;
ams,input-max-microamp = <1750000>;
};
indicator {
indicator@1 {
reg = <0x1>;
led-max-microamp = <10000>;
};
};

5
arch/arm/boot/dts/stm32429i-eval.dts
View File

@ -47,6 +47,7 @@
/dts-v1/;
#include "stm32f429.dtsi"
#include "stm32f429-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
@ -202,10 +203,8 @@
stmpe1600: stmpe1600@42 {
compatible = "st,stmpe1600";
reg = <0x42>;
irq-gpio = <&gpioi 8 0>;
irq-trigger = <3>;
interrupts = <8 3>;
interrupt-parent = <&exti>;
interrupt-parent = <&gpioi>;
interrupt-controller;
wakeup-source;

343
arch/arm/boot/dts/stm32f4-pinctrl.dtsi Normal file
View File

@ -0,0 +1,343 @@
/*
* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
#include <dt-bindings/mfd/stm32f4-rcc.h>
/ {
soc {
pinctrl: pin-controller {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40020000 0x3000>;
interrupt-parent = <&exti>;
st,syscfg = <&syscfg 0x8>;
pins-are-numbered;
gpioa: gpio@40020000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
};
gpiob: gpio@40020400 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
};
gpioc: gpio@40020800 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
};
gpiod: gpio@40020c00 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xc00 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
};
gpioe: gpio@40021000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
};
gpiof: gpio@40021400 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
};
gpiog: gpio@40021800 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
};
gpioh: gpio@40021c00 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1c00 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
};
gpioi: gpio@40022000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
};
gpioj: gpio@40022400 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
};
gpiok: gpio@40022800 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
};
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
bias-disable;
};
};
usart3_pins_a: usart3@0 {
pins1 {
pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
bias-disable;
};
};
usbotg_fs_pins_a: usbotg_fs@0 {
pins {
pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
<STM32F429_PA11_FUNC_OTG_FS_DM>,
<STM32F429_PA12_FUNC_OTG_FS_DP>;
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
usbotg_fs_pins_b: usbotg_fs@1 {
pins {
pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
<STM32F429_PB14_FUNC_OTG_HS_DM>,
<STM32F429_PB15_FUNC_OTG_HS_DP>;
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
<STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
<STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
<STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
<STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
<STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
<STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
<STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
<STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
<STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
<STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
<STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
ethernet_mii: mii@0 {
pins {
pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
<STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
<STM32F429_PC2_FUNC_ETH_MII_TXD2>,
<STM32F429_PB8_FUNC_ETH_MII_TXD3>,
<STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
<STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
<STM32F429_PA2_FUNC_ETH_MDIO>,
<STM32F429_PC1_FUNC_ETH_MDC>,
<STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
<STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
<STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
<STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
<STM32F429_PH6_FUNC_ETH_MII_RXD2>,
<STM32F429_PH7_FUNC_ETH_MII_RXD3>;
slew-rate = <2>;
};
};
adc3_in8_pin: adc@200 {
pins {
pinmux = <STM32F429_PF10_FUNC_ANALOG>;
};
};
pwm1_pins: pwm@1 {
pins {
pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
<STM32F429_PB13_FUNC_TIM1_CH1N>,
<STM32F429_PB12_FUNC_TIM1_BKIN>;
};
};
pwm3_pins: pwm@3 {
pins {
pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
<STM32F429_PB5_FUNC_TIM3_CH2>;
};
};
i2c1_pins: i2c1@0 {
pins {
pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
<STM32F429_PB6_FUNC_I2C1_SCL>;
bias-disable;
drive-open-drain;
slew-rate = <3>;
};
};
ltdc_pins: ltdc@0 {
pins {
pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
<STM32F429_PI13_FUNC_LCD_VSYNC>,
<STM32F429_PI14_FUNC_LCD_CLK>,
<STM32F429_PI15_FUNC_LCD_R0>,
<STM32F429_PJ0_FUNC_LCD_R1>,
<STM32F429_PJ1_FUNC_LCD_R2>,
<STM32F429_PJ2_FUNC_LCD_R3>,
<STM32F429_PJ3_FUNC_LCD_R4>,
<STM32F429_PJ4_FUNC_LCD_R5>,
<STM32F429_PJ5_FUNC_LCD_R6>,
<STM32F429_PJ6_FUNC_LCD_R7>,
<STM32F429_PJ7_FUNC_LCD_G0>,
<STM32F429_PJ8_FUNC_LCD_G1>,
<STM32F429_PJ9_FUNC_LCD_G2>,
<STM32F429_PJ10_FUNC_LCD_G3>,
<STM32F429_PJ11_FUNC_LCD_G4>,
<STM32F429_PJ12_FUNC_LCD_B0>,
<STM32F429_PJ13_FUNC_LCD_B1>,
<STM32F429_PJ14_FUNC_LCD_B2>,
<STM32F429_PJ15_FUNC_LCD_B3>,
<STM32F429_PK0_FUNC_LCD_G5>,
<STM32F429_PK1_FUNC_LCD_G6>,
<STM32F429_PK2_FUNC_LCD_G7>,
<STM32F429_PK3_FUNC_LCD_B4>,
<STM32F429_PK4_FUNC_LCD_B5>,
<STM32F429_PK5_FUNC_LCD_B6>,
<STM32F429_PK6_FUNC_LCD_B7>,
<STM32F429_PK7_FUNC_LCD_DE>;
slew-rate = <2>;
};
};
dcmi_pins: dcmi@0 {
pins {
pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>,
<STM32F429_PB7_FUNC_DCMI_VSYNC>,
<STM32F429_PA6_FUNC_DCMI_PIXCLK>,
<STM32F429_PC6_FUNC_DCMI_D0>,
<STM32F429_PC7_FUNC_DCMI_D1>,
<STM32F429_PC8_FUNC_DCMI_D2>,
<STM32F429_PC9_FUNC_DCMI_D3>,
<STM32F429_PC11_FUNC_DCMI_D4>,
<STM32F429_PD3_FUNC_DCMI_D5>,
<STM32F429_PB8_FUNC_DCMI_D6>,
<STM32F429_PE6_FUNC_DCMI_D7>,
<STM32F429_PC10_FUNC_DCMI_D8>,
<STM32F429_PC12_FUNC_DCMI_D9>,
<STM32F429_PD6_FUNC_DCMI_D10>,
<STM32F429_PD2_FUNC_DCMI_D11>;
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
};
};
};
};

1
arch/arm/boot/dts/stm32f429-disco.dts
View File

@ -47,6 +47,7 @@
/dts-v1/;
#include "stm32f429.dtsi"
#include "stm32f429-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
/ {

95
arch/arm/boot/dts/stm32f429-pinctrl.dtsi Normal file
View File

@ -0,0 +1,95 @@
/*
* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "stm32f4-pinctrl.dtsi"
/ {
soc {
pinctrl: pin-controller {
compatible = "st,stm32f429-pinctrl";
gpioa: gpio@40020000 {
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@40020400 {
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@40020800 {
gpio-ranges = <&pinctrl 0 32 16>;
};
gpiod: gpio@40020c00 {
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@40021000 {
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@40021400 {
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@40021800 {
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@40021c00 {
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioi: gpio@40022000 {
gpio-ranges = <&pinctrl 0 128 16>;
};
gpioj: gpio@40022400 {
gpio-ranges = <&pinctrl 0 144 16>;
};
gpiok: gpio@40022800 {
gpio-ranges = <&pinctrl 0 160 8>;
};
};
};
};

297
arch/arm/boot/dts/stm32f429.dtsi
View File

@ -47,7 +47,6 @@
#include "skeleton.dtsi"
#include "armv7-m.dtsi"
#include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
#include <dt-bindings/clock/stm32fx-clock.h>
#include <dt-bindings/mfd/stm32f4-rcc.h>
@ -591,302 +590,6 @@
status = "disabled";
};
pinctrl: pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f429-pinctrl";
ranges = <0 0x40020000 0x3000>;
interrupt-parent = <&exti>;
st,syscfg = <&syscfg 0x8>;
pins-are-numbered;
gpioa: gpio@40020000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
st,bank-name = "GPIOA";
};
gpiob: gpio@40020400 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
st,bank-name = "GPIOB";
};
gpioc: gpio@40020800 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
st,bank-name = "GPIOC";
};
gpiod: gpio@40020c00 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xc00 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
st,bank-name = "GPIOD";
};
gpioe: gpio@40021000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1000 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
st,bank-name = "GPIOE";
};
gpiof: gpio@40021400 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
st,bank-name = "GPIOF";
};
gpiog: gpio@40021800 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
st,bank-name = "GPIOG";
};
gpioh: gpio@40021c00 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x1c00 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
st,bank-name = "GPIOH";
};
gpioi: gpio@40022000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2000 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
st,bank-name = "GPIOI";
};
gpioj: gpio@40022400 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2400 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
st,bank-name = "GPIOJ";
};
gpiok: gpio@40022800 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x2800 0x400>;
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
st,bank-name = "GPIOK";
};
usart1_pins_a: usart1@0 {
pins1 {
pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
bias-disable;
};
};
usart3_pins_a: usart3@0 {
pins1 {
pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
bias-disable;
};
};
usbotg_fs_pins_a: usbotg_fs@0 {
pins {
pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
<STM32F429_PA11_FUNC_OTG_FS_DM>,
<STM32F429_PA12_FUNC_OTG_FS_DP>;
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
usbotg_fs_pins_b: usbotg_fs@1 {
pins {
pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
<STM32F429_PB14_FUNC_OTG_HS_DM>,
<STM32F429_PB15_FUNC_OTG_HS_DP>;
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
usbotg_hs_pins_a: usbotg_hs@0 {
pins {
pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
<STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
<STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
<STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
<STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
<STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
<STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
<STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
<STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
<STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
<STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
<STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
};
ethernet_mii: mii@0 {
pins {
pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
<STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
<STM32F429_PC2_FUNC_ETH_MII_TXD2>,
<STM32F429_PB8_FUNC_ETH_MII_TXD3>,
<STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
<STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
<STM32F429_PA2_FUNC_ETH_MDIO>,
<STM32F429_PC1_FUNC_ETH_MDC>,
<STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
<STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
<STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
<STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
<STM32F429_PH6_FUNC_ETH_MII_RXD2>,
<STM32F429_PH7_FUNC_ETH_MII_RXD3>;
slew-rate = <2>;
};
};
adc3_in8_pin: adc@200 {
pins {
pinmux = <STM32F429_PF10_FUNC_ANALOG>;
};
};
pwm1_pins: pwm@1 {
pins {
pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
<STM32F429_PB13_FUNC_TIM1_CH1N>,
<STM32F429_PB12_FUNC_TIM1_BKIN>;
};
};
pwm3_pins: pwm@3 {
pins {
pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
<STM32F429_PB5_FUNC_TIM3_CH2>;
};
};
i2c1_pins: i2c1@0 {
pins {
pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
<STM32F429_PB6_FUNC_I2C1_SCL>;
bias-disable;
drive-open-drain;
slew-rate = <3>;
};
};
ltdc_pins: ltdc@0 {
pins {
pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
<STM32F429_PI13_FUNC_LCD_VSYNC>,
<STM32F429_PI14_FUNC_LCD_CLK>,
<STM32F429_PI15_FUNC_LCD_R0>,
<STM32F429_PJ0_FUNC_LCD_R1>,
<STM32F429_PJ1_FUNC_LCD_R2>,
<STM32F429_PJ2_FUNC_LCD_R3>,
<STM32F429_PJ3_FUNC_LCD_R4>,
<STM32F429_PJ4_FUNC_LCD_R5>,
<STM32F429_PJ5_FUNC_LCD_R6>,
<STM32F429_PJ6_FUNC_LCD_R7>,
<STM32F429_PJ7_FUNC_LCD_G0>,
<STM32F429_PJ8_FUNC_LCD_G1>,
<STM32F429_PJ9_FUNC_LCD_G2>,
<STM32F429_PJ10_FUNC_LCD_G3>,
<STM32F429_PJ11_FUNC_LCD_G4>,
<STM32F429_PJ12_FUNC_LCD_B0>,
<STM32F429_PJ13_FUNC_LCD_B1>,
<STM32F429_PJ14_FUNC_LCD_B2>,
<STM32F429_PJ15_FUNC_LCD_B3>,
<STM32F429_PK0_FUNC_LCD_G5>,
<STM32F429_PK1_FUNC_LCD_G6>,
<STM32F429_PK2_FUNC_LCD_G7>,
<STM32F429_PK3_FUNC_LCD_B4>,
<STM32F429_PK4_FUNC_LCD_B5>,
<STM32F429_PK5_FUNC_LCD_B6>,
<STM32F429_PK6_FUNC_LCD_B7>,
<STM32F429_PK7_FUNC_LCD_DE>;
slew-rate = <2>;
};
};
dcmi_pins: dcmi@0 {
pins {
pinmux = <STM32F429_PA4_FUNC_DCMI_HSYNC>,
<STM32F429_PB7_FUNC_DCMI_VSYNC>,
<STM32F429_PA6_FUNC_DCMI_PIXCLK>,
<STM32F429_PC6_FUNC_DCMI_D0>,
<STM32F429_PC7_FUNC_DCMI_D1>,
<STM32F429_PC8_FUNC_DCMI_D2>,
<STM32F429_PC9_FUNC_DCMI_D3>,
<STM32F429_PC11_FUNC_DCMI_D4>,
<STM32F429_PD3_FUNC_DCMI_D5>,
<STM32F429_PB8_FUNC_DCMI_D6>,
<STM32F429_PE6_FUNC_DCMI_D7>,
<STM32F429_PC10_FUNC_DCMI_D8>,
<STM32F429_PC12_FUNC_DCMI_D9>,
<STM32F429_PD6_FUNC_DCMI_D10>,
<STM32F429_PD2_FUNC_DCMI_D11>;
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
};
};
crc: crc@40023000 {
compatible = "st,stm32f4-crc";
reg = <0x40023000 0x400>;

1
arch/arm/boot/dts/stm32f469-disco.dts
View File

@ -47,6 +47,7 @@
/dts-v1/;
#include "stm32f429.dtsi"
#include "stm32f469-pinctrl.dtsi"
/ {
model = "STMicroelectronics STM32F469i-DISCO board";

96
arch/arm/boot/dts/stm32f469-pinctrl.dtsi Normal file
View File

@ -0,0 +1,96 @@
/*
* Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "stm32f4-pinctrl.dtsi"
/ {
soc {
pinctrl: pin-controller {
compatible = "st,stm32f469-pinctrl";
gpioa: gpio@40020000 {
gpio-ranges = <&pinctrl 0 0 16>;
};
gpiob: gpio@40020400 {
gpio-ranges = <&pinctrl 0 16 16>;
};
gpioc: gpio@40020800 {
gpio-ranges = <&pinctrl 0 32 16>;
};
gpiod: gpio@40020c00 {
gpio-ranges = <&pinctrl 0 48 16>;
};
gpioe: gpio@40021000 {
gpio-ranges = <&pinctrl 0 64 16>;
};
gpiof: gpio@40021400 {
gpio-ranges = <&pinctrl 0 80 16>;
};
gpiog: gpio@40021800 {
gpio-ranges = <&pinctrl 0 96 16>;
};
gpioh: gpio@40021c00 {
gpio-ranges = <&pinctrl 0 112 16>;
};
gpioi: gpio@40022000 {
gpio-ranges = <&pinctrl 0 128 16>;
};
gpioj: gpio@40022400 {
gpio-ranges = <&pinctrl 0 144 6>,
<&pinctrl 12 156 4>;
};
gpiok: gpio@40022800 {
gpio-ranges = <&pinctrl 3 163 5>;
};
};
};
};

3
arch/arm/configs/gemini_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_ATA=y
CONFIG_PATA_FTIDE010=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
@ -55,8 +56,8 @@ CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_GEMINI=y
CONFIG_DMADEVICES=y
CONFIG_AMBA_PL08X=y
# CONFIG_DNOTIFY is not set
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y

2
arch/arm/configs/pxa_defconfig
View File

@ -471,7 +471,7 @@ CONFIG_LCD_PLATFORM=m
CONFIG_LCD_TOSA=m
CONFIG_BACKLIGHT_PWM=m
CONFIG_BACKLIGHT_TOSA=m
CONFIG_FRAMEBUFFER_CONSOLE=m
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_LOGO=y
CONFIG_SOUND=m

2
arch/arm/configs/viper_defconfig
View File

@ -113,7 +113,7 @@ CONFIG_FB_PXA_PARAMETERS=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_PWM=m
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=m
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
CONFIG_SOUND=m
CONFIG_SND=m

2
arch/arm/configs/zeus_defconfig
View File

@ -112,7 +112,7 @@ CONFIG_FB_PXA=m
CONFIG_FB_PXA_PARAMETERS=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=m
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
CONFIG_SOUND=m
CONFIG_SND=m

15
arch/arm/include/asm/thread_info.h
View File

@ -139,11 +139,10 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
#define TIF_NEED_RESCHED 1 /* rescheduling necessary */
#define TIF_NOTIFY_RESUME 2 /* callback before returning to user */
#define TIF_UPROBE 3 /* breakpointed or singlestepping */
#define TIF_FSCHECK 4 /* Check FS is USER_DS on return */
#define TIF_SYSCALL_TRACE 5 /* syscall trace active */
#define TIF_SYSCALL_AUDIT 6 /* syscall auditing active */
#define TIF_SYSCALL_TRACEPOINT 7 /* syscall tracepoint instrumentation */
#define TIF_SECCOMP 8 /* seccomp syscall filtering active */
#define TIF_SYSCALL_TRACE 4 /* syscall trace active */
#define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */
#define TIF_SYSCALL_TRACEPOINT 6 /* syscall tracepoint instrumentation */
#define TIF_SECCOMP 7 /* seccomp syscall filtering active */
#define TIF_NOHZ 12 /* in adaptive nohz mode */
#define TIF_USING_IWMMXT 17
@ -154,7 +153,6 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
#define _TIF_UPROBE (1 << TIF_UPROBE)
#define _TIF_FSCHECK (1 << TIF_FSCHECK)
#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
#define _TIF_SYSCALL_TRACEPOINT (1 << TIF_SYSCALL_TRACEPOINT)
@ -168,9 +166,8 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
/*
* Change these and you break ASM code in entry-common.S
*/
#define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | \
_TIF_NOTIFY_RESUME | _TIF_UPROBE | \
_TIF_FSCHECK)
#define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | \
_TIF_NOTIFY_RESUME | _TIF_UPROBE)
#endif /* __KERNEL__ */
#endif /* __ASM_ARM_THREAD_INFO_H */

2
arch/arm/include/asm/uaccess.h
View File

@ -70,8 +70,6 @@ static inline void set_fs(mm_segment_t fs)
{
current_thread_info()->addr_limit = fs;
modify_domain(DOMAIN_KERNEL, fs ? DOMAIN_CLIENT : DOMAIN_MANAGER);
/* On user-mode return, check fs is correct */
set_thread_flag(TIF_FSCHECK);
}
#define segment_eq(a, b) ((a) == (b))

20
arch/arm/kernel/entry-common.S
View File

@ -12,6 +12,7 @@
#include <asm/unistd.h>
#include <asm/ftrace.h>
#include <asm/unwind.h>
#include <asm/memory.h>
#ifdef CONFIG_AEABI
#include <asm/unistd-oabi.h>
#endif
@ -48,12 +49,14 @@ ret_fast_syscall:
UNWIND(.fnstart )
UNWIND(.cantunwind )
disable_irq_notrace @ disable interrupts
ldr r2, [tsk, #TI_ADDR_LIMIT]
cmp r2, #TASK_SIZE
blne addr_limit_check_failed
ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing
tst r1, #_TIF_SYSCALL_WORK
bne fast_work_pending
tst r1, #_TIF_WORK_MASK
tst r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK
bne fast_work_pending
/* perform architecture specific actions before user return */
arch_ret_to_user r1, lr
@ -76,16 +79,16 @@ ret_fast_syscall:
UNWIND(.cantunwind )
str r0, [sp, #S_R0 + S_OFF]! @ save returned r0
disable_irq_notrace @ disable interrupts
ldr r2, [tsk, #TI_ADDR_LIMIT]
cmp r2, #TASK_SIZE
blne addr_limit_check_failed
ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing
tst r1, #_TIF_SYSCALL_WORK
bne fast_work_pending
tst r1, #_TIF_WORK_MASK
tst r1, #_TIF_SYSCALL_WORK | _TIF_WORK_MASK
beq no_work_pending
UNWIND(.fnend )
ENDPROC(ret_fast_syscall)
/* Slower path - fall through to work_pending */
fast_work_pending:
#endif
tst r1, #_TIF_SYSCALL_WORK
@ -111,6 +114,9 @@ ENTRY(ret_to_user)
ret_slow_syscall:
disable_irq_notrace @ disable interrupts
ENTRY(ret_to_user_from_irq)
ldr r2, [tsk, #TI_ADDR_LIMIT]
cmp r2, #TASK_SIZE
blne addr_limit_check_failed
ldr r1, [tsk, #TI_FLAGS]
tst r1, #_TIF_WORK_MASK
bne slow_work_pending

10
arch/arm/kernel/signal.c
View File

@ -614,10 +614,6 @@ do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall)
* Update the trace code with the current status.
*/
trace_hardirqs_off();
/* Check valid user FS if needed */
addr_limit_user_check();
do {
if (likely(thread_flags & _TIF_NEED_RESCHED)) {
schedule();
@ -678,3 +674,9 @@ struct page *get_signal_page(void)
return page;
}
/* Defer to generic check */
asmlinkage void addr_limit_check_failed(void)
{
addr_limit_user_check();
}

4
arch/arm/mach-at91/pm.c
View File

@ -533,8 +533,8 @@ static void __init at91_pm_backup_init(void)
}
pm_bu->suspended = 0;
pm_bu->canary = virt_to_phys(&canary);
pm_bu->resume = virt_to_phys(cpu_resume);
pm_bu->canary = __pa_symbol(&canary);
pm_bu->resume = __pa_symbol(cpu_resume);
return;

4
arch/arm/mach-omap2/hsmmc.c
View File

@ -58,10 +58,10 @@ void omap_hsmmc_late_init(struct omap2_hsmmc_info *c)
struct platform_device *pdev;
int res;
if (omap_hsmmc_done != 1)
if (omap_hsmmc_done)
return;
omap_hsmmc_done++;
omap_hsmmc_done = 1;
for (; c->mmc; c++) {
pdev = c->pdev;

1
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View File

@ -839,6 +839,7 @@ static struct omap_hwmod dra7xx_gpio1_hwmod = {
.name = "gpio1",
.class = &dra7xx_gpio_hwmod_class,
.clkdm_name = "wkupaon_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.main_clk = "wkupaon_iclk_mux",
.prcm = {
.omap4 = {

10
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
View File

@ -168,7 +168,8 @@
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdio_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
#address-cells = <1>;
#size-cells = <0>;
@ -194,7 +195,8 @@
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdcard_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
@ -212,10 +214,10 @@
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;

19
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
View File

@ -107,6 +107,9 @@
states = <3300000 0>,
<1800000 1>;
regulator-settling-time-up-us = <100>;
regulator-settling-time-down-us = <5000>;
};
wifi_32k: wifi-32k {
@ -250,7 +253,8 @@
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>, <&sdio_irq_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdio_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
#address-cells = <1>;
#size-cells = <0>;
@ -276,11 +280,16 @@
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdcard_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
max-frequency = <100000000>;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
max-frequency = <200000000>;
disable-wp;
cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
@ -294,10 +303,10 @@
&sd_emmc_c {
status = "disabled";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-sd-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;

12
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts
View File

@ -51,7 +51,7 @@
/ {
compatible = "nexbox,a95x", "amlogic,meson-gxbb";
model = "NEXBOX A95X";
aliases {
serial0 = &uart_AO;
};
@ -232,7 +232,8 @@
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdio_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
#address-cells = <1>;
#size-cells = <0>;
@ -253,7 +254,8 @@
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdcard_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
@ -271,10 +273,10 @@
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;

9
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
View File

@ -50,7 +50,7 @@
/ {
compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
model = "Hardkernel ODROID-C2";
aliases {
serial0 = &uart_AO;
};
@ -253,7 +253,8 @@
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdcard_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
@ -271,10 +272,10 @@
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-sd-highspeed;
max-frequency = <200000000>;
non-removable;
disable-wp;

13
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi
View File

@ -194,7 +194,8 @@
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdio_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
#address-cells = <1>;
#size-cells = <0>;
@ -220,10 +221,14 @@
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdcard_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
max-frequency = <100000000>;
disable-wp;
@ -238,10 +243,10 @@
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;

10
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi
View File

@ -155,7 +155,8 @@
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins &sdio_irq_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdio_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
#address-cells = <1>;
#size-cells = <0>;
@ -181,7 +182,8 @@
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdcard_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
@ -198,10 +200,10 @@
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;

39
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
View File

@ -392,6 +392,17 @@
};
};
emmc_clk_gate_pins: emmc_clk_gate {
mux {
groups = "BOOT_8";
function = "gpio_periphs";
};
cfg-pull-down {
pins = "BOOT_8";
bias-pull-down;
};
};
nor_pins: nor {
mux {
groups = "nor_d",
@ -430,6 +441,17 @@
};
};
sdcard_clk_gate_pins: sdcard_clk_gate {
mux {
groups = "CARD_2";
function = "gpio_periphs";
};
cfg-pull-down {
pins = "CARD_2";
bias-pull-down;
};
};
sdio_pins: sdio {
mux {
groups = "sdio_d0",
@ -442,6 +464,17 @@
};
};
sdio_clk_gate_pins: sdio_clk_gate {
mux {
groups = "GPIOX_4";
function = "gpio_periphs";
};
cfg-pull-down {
pins = "GPIOX_4";
bias-pull-down;
};
};
sdio_irq_pins: sdio_irq {
mux {
groups = "sdio_irq";
@ -661,21 +694,21 @@
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
<&clkc CLKID_SD_EMMC_A_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
};
&sd_emmc_b {
clocks = <&clkc CLKID_SD_EMMC_B>,
<&xtal>,
<&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
};
&sd_emmc_c {
clocks = <&clkc CLKID_SD_EMMC_C>,
<&xtal>,
<&clkc CLKID_SD_EMMC_C_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
};

7
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-hwacom-amazetv.dts
View File

@ -123,7 +123,8 @@
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdcard_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
@ -141,10 +142,10 @@
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <100000000>;
non-removable;

13
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
View File

@ -91,6 +91,9 @@
states = <3300000 0>,
<1800000 1>;
regulator-settling-time-up-us = <200>;
regulator-settling-time-down-us = <50000>;
};
vddio_boot: regulator-vddio_boot {
@ -197,10 +200,14 @@
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdcard_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
max-frequency = <100000000>;
disable-wp;
@ -215,10 +222,12 @@
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-mmc-highspeed;
mmc-ddr-3_3v;
max-frequency = <50000000>;
non-removable;
disable-wp;

10
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts
View File

@ -189,7 +189,8 @@
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdio_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
#address-cells = <1>;
#size-cells = <0>;
@ -210,7 +211,8 @@
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdcard_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
@ -228,10 +230,10 @@
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;

10
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
View File

@ -95,7 +95,8 @@
&sd_emmc_a {
status = "okay";
pinctrl-0 = <&sdio_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdio_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
#address-cells = <1>;
#size-cells = <0>;
@ -116,7 +117,8 @@
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdcard_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
@ -134,10 +136,10 @@
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;

39
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
View File

@ -281,6 +281,17 @@
};
};
emmc_clk_gate_pins: emmc_clk_gate {
mux {
groups = "BOOT_8";
function = "gpio_periphs";
};
cfg-pull-down {
pins = "BOOT_8";
bias-pull-down;
};
};
nor_pins: nor {
mux {
groups = "nor_d",
@ -319,6 +330,17 @@
};
};
sdcard_clk_gate_pins: sdcard_clk_gate {
mux {
groups = "CARD_2";
function = "gpio_periphs";
};
cfg-pull-down {
pins = "CARD_2";
bias-pull-down;
};
};
sdio_pins: sdio {
mux {
groups = "sdio_d0",
@ -331,6 +353,17 @@
};
};
sdio_clk_gate_pins: sdio_clk_gate {
mux {
groups = "GPIOX_4";
function = "gpio_periphs";
};
cfg-pull-down {
pins = "GPIOX_4";
bias-pull-down;
};
};
sdio_irq_pins: sdio_irq {
mux {
groups = "sdio_irq";
@ -603,21 +636,21 @@
&sd_emmc_a {
clocks = <&clkc CLKID_SD_EMMC_A>,
<&xtal>,
<&clkc CLKID_SD_EMMC_A_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
};
&sd_emmc_b {
clocks = <&clkc CLKID_SD_EMMC_B>,
<&xtal>,
<&clkc CLKID_SD_EMMC_B_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
};
&sd_emmc_c {
clocks = <&clkc CLKID_SD_EMMC_C>,
<&xtal>,
<&clkc CLKID_SD_EMMC_C_CLK0>,
<&clkc CLKID_FCLK_DIV2>;
clock-names = "core", "clkin0", "clkin1";
};

7
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
View File

@ -175,7 +175,8 @@
&sd_emmc_b {
status = "okay";
pinctrl-0 = <&sdcard_pins>;
pinctrl-names = "default";
pinctrl-1 = <&sdcard_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <4>;
cap-sd-highspeed;
@ -193,10 +194,10 @@
&sd_emmc_c {
status = "okay";
pinctrl-0 = <&emmc_pins>;
pinctrl-names = "default";
pinctrl-1 = <&emmc_clk_gate_pins>;
pinctrl-names = "default", "clk-gate";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;

1
arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts
View File

@ -220,7 +220,6 @@
pinctrl-names = "default";
bus-width = <8>;
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <200000000>;
non-removable;

4
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View File

@ -254,7 +254,7 @@
ap_syscon: system-controller@6f4000 {
compatible = "syscon", "simple-mfd";
reg = <0x6f4000 0x1000>;
reg = <0x6f4000 0x2000>;
ap_clk: clock {
compatible = "marvell,ap806-clock";
@ -265,7 +265,7 @@
compatible = "marvell,ap806-pinctrl";
};
ap_gpio: gpio {
ap_gpio: gpio@1040 {
compatible = "marvell,armada-8k-gpio";
offset = <0x1040>;
ngpios = <20>;

72
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View File

@ -113,8 +113,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>; /* min followed by max */
};
@ -123,8 +122,6 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
cpu_l2: cpu@2 {
@ -132,8 +129,6 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
cpu_l3: cpu@3 {
@ -141,8 +136,6 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
cpu_b0: cpu@100 {
@ -150,8 +143,7 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>; /* min followed by max */
};
@ -160,8 +152,6 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
};
cpu_b2: cpu@102 {
@ -169,8 +159,6 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
};
cpu_b3: cpu@103 {
@ -178,62 +166,6 @@
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
};
};
cluster0_opp: opp-table0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <950000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000>;
};
opp02 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000>;
};
opp03 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1025000>;
};
opp04 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1125000>;
};
};
cluster1_opp: opp-table1 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <950000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000>;
};
opp02 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000>;
};
opp03 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <975000>;
};
opp04 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1050000>;
};
};

6
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@ -1629,9 +1629,9 @@
compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff960000 0x0 0x8000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
<&cru SCLK_DPHY_TX0_CFG>;
clock-names = "ref", "pclk", "phy_cfg";
clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
<&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
clock-names = "ref", "pclk", "phy_cfg", "grf";
power-domains = <&power RK3399_PD_VIO>;
rockchip,grf = <&grf>;
status = "disabled";

9
arch/arm64/include/asm/memory.h
View File

@ -95,16 +95,19 @@
#define KERNEL_END _end
/*
* The size of the KASAN shadow region. This should be 1/8th of the
* size of the entire kernel virtual address space.
* KASAN requires 1/8th of the kernel virtual address space for the shadow
* region. KASAN can bloat the stack significantly, so double the (minimum)
* stack size when KASAN is in use.
*/
#ifdef CONFIG_KASAN
#define KASAN_SHADOW_SIZE (UL(1) << (VA_BITS - 3))
#define KASAN_THREAD_SHIFT 1
#else
#define KASAN_SHADOW_SIZE (0)
#define KASAN_THREAD_SHIFT 0
#endif
#define MIN_THREAD_SHIFT 14
#define MIN_THREAD_SHIFT (14 + KASAN_THREAD_SHIFT)
/*
* VMAP'd stacks are allocated at page granularity, so we must ensure that such

2
arch/arm64/include/asm/pgtable.h
View File

@ -401,7 +401,7 @@ static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
/* Find an entry in the third-level page table. */
#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset_phys(dir,addr) (pmd_page_paddr(*(dir)) + pte_index(addr) * sizeof(pte_t))
#define pte_offset_phys(dir,addr) (pmd_page_paddr(READ_ONCE(*(dir))) + pte_index(addr) * sizeof(pte_t))
#define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr))))
#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))

2
arch/arm64/kernel/armv8_deprecated.c
View File

@ -649,4 +649,4 @@ static int __init armv8_deprecated_init(void)
return 0;
}
late_initcall(armv8_deprecated_init);
core_initcall(armv8_deprecated_init);

2
arch/arm64/kernel/cpufeature.c
View File

@ -1307,4 +1307,4 @@ static int __init enable_mrs_emulation(void)
return 0;
}
late_initcall(enable_mrs_emulation);
core_initcall(enable_mrs_emulation);

2
arch/arm64/kernel/fpsimd.c
View File

@ -444,4 +444,4 @@ static int __init fpsimd_init(void)
return 0;
}
late_initcall(fpsimd_init);
core_initcall(fpsimd_init);

1
arch/arm64/kernel/head.S
View File

@ -384,6 +384,7 @@ ENTRY(kimage_vaddr)
* booted in EL1 or EL2 respectively.
*/
ENTRY(el2_setup)
msr SPsel, #1 // We want to use SP_EL{1,2}
mrs x0, CurrentEL
cmp x0, #CurrentEL_EL2
b.eq 1f

6
arch/arm64/kernel/signal.c
View File

@ -751,10 +751,10 @@ asmlinkage void do_notify_resume(struct pt_regs *regs,
*/
trace_hardirqs_off();
/* Check valid user FS if needed */
addr_limit_user_check();
do {
/* Check valid user FS if needed */
addr_limit_user_check();
if (thread_flags & _TIF_NEED_RESCHED) {
schedule();
} else {

4
arch/arm64/mm/fault.c
View File

@ -97,7 +97,7 @@ static void data_abort_decode(unsigned int esr)
(esr & ESR_ELx_SF) >> ESR_ELx_SF_SHIFT,
(esr & ESR_ELx_AR) >> ESR_ELx_AR_SHIFT);
} else {
pr_alert(" ISV = 0, ISS = 0x%08lu\n", esr & ESR_ELx_ISS_MASK);
pr_alert(" ISV = 0, ISS = 0x%08lx\n", esr & ESR_ELx_ISS_MASK);
}
pr_alert(" CM = %lu, WnR = %lu\n",
@ -651,7 +651,7 @@ static const struct fault_info fault_info[] = {
{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 0 translation fault" },
{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 1 translation fault" },
{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 2 translation fault" },
{ do_page_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },
{ do_translation_fault, SIGSEGV, SEGV_MAPERR, "level 3 translation fault" },
{ do_bad, SIGBUS, 0, "unknown 8" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 1 access flag fault" },
{ do_page_fault, SIGSEGV, SEGV_ACCERR, "level 2 access flag fault" },

4
arch/m32r/Kconfig
View File

@ -194,6 +194,10 @@ config TIMER_DIVIDE
int "Timer divider (integer)"
default "128"
config CPU_BIG_ENDIAN
bool "Generate big endian code"
default n
config CPU_LITTLE_ENDIAN
bool "Generate little endian code"
default n

9
arch/m32r/kernel/traps.c
View File

@ -114,6 +114,15 @@ static void set_eit_vector_entries(void)
_flush_cache_copyback_all();
}
void abort(void)
{
BUG();
/* if that doesn't kill us, halt */
panic("Oops failed to kill thread");
}
EXPORT_SYMBOL(abort);
void __init trap_init(void)
{
set_eit_vector_entries();

2
arch/microblaze/Kconfig
View File

@ -39,7 +39,7 @@ config MICROBLAZE
# Endianness selection
choice
prompt "Endianness selection"
default CPU_BIG_ENDIAN
default CPU_LITTLE_ENDIAN
help
microblaze architectures can be configured for either little or
big endian formats. Be sure to select the appropriate mode.

1
arch/microblaze/include/uapi/asm/Kbuild
View File

@ -7,6 +7,7 @@ generic-y += fcntl.h
generic-y += ioctl.h
generic-y += ioctls.h
generic-y += ipcbuf.h
generic-y += kvm_para.h
generic-y += mman.h
generic-y += msgbuf.h
generic-y += param.h

2
arch/microblaze/kernel/dma.c
View File

@ -165,7 +165,7 @@ int dma_direct_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
unsigned long attrs)
{
#ifdef CONFIG_MMU
unsigned long user_count = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
unsigned long user_count = vma_pages(vma);
unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
unsigned long off = vma->vm_pgoff;
unsigned long pfn;

2
arch/parisc/kernel/process.c
View File

@ -146,7 +146,7 @@ void machine_power_off(void)
/* prevent soft lockup/stalled CPU messages for endless loop. */
rcu_sysrq_start();
lockup_detector_suspend();
lockup_detector_soft_poweroff();
for (;;);
}

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