x86: Move PCI IO ECS code to x86/pci
"Form follows function". Code is now where it belongs to. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -266,9 +266,6 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
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if (cpu_has_xmm2)
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set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
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if (c->x86 == 0x10)
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amd_enable_pci_ext_cfg(c);
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}
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static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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@ -6,7 +6,6 @@
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#include <asm/cacheflush.h>
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#include <mach_apic.h>
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#include "cpu.h"
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extern int __cpuinit get_model_name(struct cpuinfo_x86 *c);
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extern void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c);
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@ -187,9 +186,6 @@ void __cpuinit init_amd(struct cpuinfo_x86 *c)
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if (c->x86 == 0x10)
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fam10h_check_enable_mmcfg();
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if (c->x86 == 0x10)
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amd_enable_pci_ext_cfg(c);
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if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
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unsigned long long tseg;
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@ -39,5 +39,3 @@ extern int get_model_name(struct cpuinfo_x86 *c);
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extern void display_cacheinfo(struct cpuinfo_x86 *c);
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#endif /* CONFIG_X86_32 */
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extern void __cpuinit amd_enable_pci_ext_cfg(struct cpuinfo_x86 *c);
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@ -137,16 +137,3 @@ void __init setup_per_cpu_areas(void)
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}
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#endif
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#define ENABLE_CF8_EXT_CFG (1ULL << 46)
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void __cpuinit amd_enable_pci_ext_cfg(struct cpuinfo_x86 *c)
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{
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u64 reg;
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rdmsrl(MSR_AMD64_NB_CFG, reg);
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if (!(reg & ENABLE_CF8_EXT_CFG)) {
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reg |= ENABLE_CF8_EXT_CFG;
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wrmsrl(MSR_AMD64_NB_CFG, reg);
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}
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set_cpu_cap(c, X86_FEATURE_PCI_EXT_CFG);
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}
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@ -22,3 +22,4 @@ pci-$(CONFIG_X86_NUMAQ) := numa.o irq.o
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pci-$(CONFIG_NUMA) += mp_bus_to_node.o
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obj-y += $(pci-y) common.o early.o
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obj-y += amd_bus.o
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@ -1,5 +1,9 @@
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#include <linux/init.h>
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#include <linux/pci.h>
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#include "pci.h"
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#ifdef CONFIG_X86_64
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#include <asm/pci-direct.h>
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#include <asm/mpspec.h>
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#include <linux/cpumask.h>
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@ -526,3 +530,31 @@ static int __init early_fill_mp_bus_info(void)
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}
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postcore_initcall(early_fill_mp_bus_info);
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#endif
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/* common 32/64 bit code */
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#define ENABLE_CF8_EXT_CFG (1ULL << 46)
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static void enable_pci_io_ecs_per_cpu(void *unused)
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{
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u64 reg;
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rdmsrl(MSR_AMD64_NB_CFG, reg);
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if (!(reg & ENABLE_CF8_EXT_CFG)) {
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reg |= ENABLE_CF8_EXT_CFG;
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wrmsrl(MSR_AMD64_NB_CFG, reg);
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}
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}
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static int __init enable_pci_io_ecs(void)
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{
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/* assume all cpus from fam10h have IO ECS */
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if (boot_cpu_data.x86 < 0x10)
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return 0;
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on_each_cpu(enable_pci_io_ecs_per_cpu, NULL, 1, 1);
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pci_probe |= PCI_HAS_IO_ECS;
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return 0;
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}
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postcore_initcall(enable_pci_io_ecs);
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@ -265,14 +265,16 @@ void __init pci_direct_init(int type)
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type);
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if (type == 1) {
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raw_pci_ops = &pci_direct_conf1;
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if (!raw_pci_ext_ops && cpu_has_pci_ext_cfg) {
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printk(KERN_INFO "PCI: Using configuration type 1 "
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"for extended access\n");
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raw_pci_ext_ops = &pci_direct_conf1;
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}
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} else {
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raw_pci_ops = &pci_direct_conf2;
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if (raw_pci_ext_ops)
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return;
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if (!(pci_probe & PCI_HAS_IO_ECS))
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return;
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printk(KERN_INFO "PCI: Using configuration type 1 "
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"for extended access\n");
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raw_pci_ext_ops = &pci_direct_conf1;
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return;
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}
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raw_pci_ops = &pci_direct_conf2;
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}
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int __init pci_direct_probe(void)
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@ -27,6 +27,7 @@
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#define PCI_CAN_SKIP_ISA_ALIGN 0x8000
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#define PCI_USE__CRS 0x10000
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#define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
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#define PCI_HAS_IO_ECS 0x40000
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extern unsigned int pci_probe;
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extern unsigned long pirq_table_addr;
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@ -79,7 +79,6 @@
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#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */
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#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
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#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
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#define X86_FEATURE_PCI_EXT_CFG (3*32+19) /* PCI extended cfg access */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
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@ -188,7 +187,6 @@ extern const char * const x86_power_flags[32];
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#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
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#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
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#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
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#define cpu_has_pci_ext_cfg boot_cpu_has(X86_FEATURE_PCI_EXT_CFG)
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#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
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# define cpu_has_invlpg 1
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