MIPS: Netlogic: Platform NAND/NOR flash support
Changes to add support for the boot NOR flash on XLR boards and the boot NAND/NOR flash drivers on the XLS boards. Signed-off-by: Ganesan Ramalingam <ganesanr@netlogicmicro.com> Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3758/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ganesan Ramalingam
Ralf Baechle
parent
f35574a3ab
commit
3a2f9b9905
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/*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the Broadcom
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ASM_NLM_BRIDGE_H_
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#define _ASM_NLM_BRIDGE_H_
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#define BRIDGE_DRAM_0_BAR 0
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#define BRIDGE_DRAM_1_BAR 1
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#define BRIDGE_DRAM_2_BAR 2
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#define BRIDGE_DRAM_3_BAR 3
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#define BRIDGE_DRAM_4_BAR 4
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#define BRIDGE_DRAM_5_BAR 5
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#define BRIDGE_DRAM_6_BAR 6
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#define BRIDGE_DRAM_7_BAR 7
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#define BRIDGE_DRAM_CHN_0_MTR_0_BAR 8
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#define BRIDGE_DRAM_CHN_0_MTR_1_BAR 9
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#define BRIDGE_DRAM_CHN_0_MTR_2_BAR 10
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#define BRIDGE_DRAM_CHN_0_MTR_3_BAR 11
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#define BRIDGE_DRAM_CHN_0_MTR_4_BAR 12
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#define BRIDGE_DRAM_CHN_0_MTR_5_BAR 13
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#define BRIDGE_DRAM_CHN_0_MTR_6_BAR 14
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#define BRIDGE_DRAM_CHN_0_MTR_7_BAR 15
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#define BRIDGE_DRAM_CHN_1_MTR_0_BAR 16
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#define BRIDGE_DRAM_CHN_1_MTR_1_BAR 17
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#define BRIDGE_DRAM_CHN_1_MTR_2_BAR 18
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#define BRIDGE_DRAM_CHN_1_MTR_3_BAR 19
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#define BRIDGE_DRAM_CHN_1_MTR_4_BAR 20
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#define BRIDGE_DRAM_CHN_1_MTR_5_BAR 21
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#define BRIDGE_DRAM_CHN_1_MTR_6_BAR 22
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#define BRIDGE_DRAM_CHN_1_MTR_7_BAR 23
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#define BRIDGE_CFG_BAR 24
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#define BRIDGE_PHNX_IO_BAR 25
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#define BRIDGE_FLASH_BAR 26
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#define BRIDGE_SRAM_BAR 27
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#define BRIDGE_HTMEM_BAR 28
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#define BRIDGE_HTINT_BAR 29
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#define BRIDGE_HTPIC_BAR 30
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#define BRIDGE_HTSM_BAR 31
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#define BRIDGE_HTIO_BAR 32
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#define BRIDGE_HTCFG_BAR 33
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#define BRIDGE_PCIXCFG_BAR 34
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#define BRIDGE_PCIXMEM_BAR 35
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#define BRIDGE_PCIXIO_BAR 36
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#define BRIDGE_DEVICE_MASK 37
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#define BRIDGE_AERR_INTR_LOG1 38
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#define BRIDGE_AERR_INTR_LOG2 39
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#define BRIDGE_AERR_INTR_LOG3 40
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#define BRIDGE_AERR_DEV_STAT 41
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#define BRIDGE_AERR1_LOG1 42
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#define BRIDGE_AERR1_LOG2 43
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#define BRIDGE_AERR1_LOG3 44
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#define BRIDGE_AERR1_DEV_STAT 45
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#define BRIDGE_AERR_INTR_EN 46
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#define BRIDGE_AERR_UPG 47
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#define BRIDGE_AERR_CLEAR 48
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#define BRIDGE_AERR1_CLEAR 49
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#define BRIDGE_SBE_COUNTS 50
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#define BRIDGE_DBE_COUNTS 51
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#define BRIDGE_BITERR_INT_EN 52
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#define BRIDGE_SYS2IO_CREDITS 53
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#define BRIDGE_EVNT_CNT_CTRL1 54
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#define BRIDGE_EVNT_COUNTER1 55
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#define BRIDGE_EVNT_CNT_CTRL2 56
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#define BRIDGE_EVNT_COUNTER2 57
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#define BRIDGE_RESERVED1 58
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#define BRIDGE_DEFEATURE 59
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#define BRIDGE_SCRATCH0 60
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#define BRIDGE_SCRATCH1 61
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#define BRIDGE_SCRATCH2 62
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#define BRIDGE_SCRATCH3 63
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#endif
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@ -0,0 +1,55 @@
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/*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the Broadcom
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ASM_NLM_FLASH_H_
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#define _ASM_NLM_FLASH_H_
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#define FLASH_CSBASE_ADDR(cs) (cs)
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#define FLASH_CSADDR_MASK(cs) (0x10 + (cs))
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#define FLASH_CSDEV_PARM(cs) (0x20 + (cs))
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#define FLASH_CSTIME_PARMA(cs) (0x30 + (cs))
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#define FLASH_CSTIME_PARMB(cs) (0x40 + (cs))
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#define FLASH_INT_MASK 0x50
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#define FLASH_INT_STATUS 0x60
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#define FLASH_ERROR_STATUS 0x70
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#define FLASH_ERROR_ADDR 0x80
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#define FLASH_NAND_CLE(cs) (0x90 + (cs))
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#define FLASH_NAND_ALE(cs) (0xa0 + (cs))
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#define FLASH_NAND_CSDEV_PARAM 0x000041e6
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#define FLASH_NAND_CSTIME_PARAMA 0x4f400e22
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#define FLASH_NAND_CSTIME_PARAMB 0x000083cf
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#endif
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@ -1,2 +1,2 @@
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obj-y += setup.o platform.o
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obj-y += setup.o platform.o platform-flash.o
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obj-$(CONFIG_SMP) += wakeup.o
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/*
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* Copyright 2011, Netlogic Microsystems.
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* Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/ioport.h>
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#include <linux/resource.h>
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#include <linux/spi/flash.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/xlr/iomap.h>
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#include <asm/netlogic/xlr/flash.h>
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#include <asm/netlogic/xlr/bridge.h>
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#include <asm/netlogic/xlr/gpio.h>
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#include <asm/netlogic/xlr/xlr.h>
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/*
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* Default NOR partition layout
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*/
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static struct mtd_partition xlr_nor_parts[] = {
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{
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.name = "User FS",
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.offset = 0x800000,
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.size = MTDPART_SIZ_FULL,
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}
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};
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/*
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* Default NAND partition layout
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*/
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static struct mtd_partition xlr_nand_parts[] = {
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{
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.name = "Root Filesystem",
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.offset = 64 * 64 * 2048,
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.size = 432 * 64 * 2048,
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},
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{
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.name = "Home Filesystem",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL,
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},
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};
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/* Use PHYSMAP flash for NOR */
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struct physmap_flash_data xlr_nor_data = {
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.width = 2,
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.parts = xlr_nor_parts,
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.nr_parts = ARRAY_SIZE(xlr_nor_parts),
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};
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static struct resource xlr_nor_res[] = {
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{
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device xlr_nor_dev = {
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.name = "physmap-flash",
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.dev = {
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.platform_data = &xlr_nor_data,
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},
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.num_resources = ARRAY_SIZE(xlr_nor_res),
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.resource = xlr_nor_res,
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};
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const char *xlr_part_probes[] = { "cmdlinepart", NULL };
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/*
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* Use "gen_nand" driver for NAND flash
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*
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* There seems to be no way to store a private pointer containing
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* platform specific info in gen_nand drivier. We will use a global
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* struct for now, since we currently have only one NAND chip per board.
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*/
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struct xlr_nand_flash_priv {
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int cs;
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uint64_t flash_mmio;
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};
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static struct xlr_nand_flash_priv nand_priv;
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static void xlr_nand_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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if (ctrl & NAND_CLE)
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nlm_write_reg(nand_priv.flash_mmio,
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FLASH_NAND_CLE(nand_priv.cs), cmd);
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else if (ctrl & NAND_ALE)
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nlm_write_reg(nand_priv.flash_mmio,
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FLASH_NAND_ALE(nand_priv.cs), cmd);
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}
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struct platform_nand_data xlr_nand_data = {
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.chip = {
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.nr_chips = 1,
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.nr_partitions = ARRAY_SIZE(xlr_nand_parts),
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.chip_delay = 50,
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.partitions = xlr_nand_parts,
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.part_probe_types = xlr_part_probes,
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},
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.ctrl = {
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.cmd_ctrl = xlr_nand_ctrl,
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},
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};
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static struct resource xlr_nand_res[] = {
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{
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device xlr_nand_dev = {
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.name = "gen_nand",
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.id = -1,
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.num_resources = ARRAY_SIZE(xlr_nand_res),
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.resource = xlr_nand_res,
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.dev = {
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.platform_data = &xlr_nand_data,
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}
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};
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/*
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* XLR/XLS supports upto 8 devices on its FLASH interface. The value in
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* FLASH_BAR (on the MEM/IO bridge) gives the base for mapping all the
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* flash devices.
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* Under this, each flash device has an offset and size given by the
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* CSBASE_ADDR and CSBASE_MASK registers for the device.
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*
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* The CSBASE_ registers are expected to be setup by the bootloader.
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*/
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static void setup_flash_resource(uint64_t flash_mmio,
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uint64_t flash_map_base, int cs, struct resource *res)
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{
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u32 base, mask;
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base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs));
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mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs));
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res->start = flash_map_base + ((unsigned long)base << 16);
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res->end = res->start + (mask + 1) * 64 * 1024;
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}
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static int __init xlr_flash_init(void)
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{
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uint64_t gpio_mmio, flash_mmio, flash_map_base;
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u32 gpio_resetcfg, flash_bar;
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int cs, boot_nand, boot_nor;
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/* Flash address bits 39:24 is in bridge flash BAR */
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flash_bar = nlm_read_reg(nlm_io_base, BRIDGE_FLASH_BAR);
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flash_map_base = (flash_bar & 0xffff0000) << 8;
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gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
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flash_mmio = nlm_mmio_base(NETLOGIC_IO_FLASH_OFFSET);
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/* Get the chip reset config */
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gpio_resetcfg = nlm_read_reg(gpio_mmio, GPIO_PWRON_RESET_CFG_REG);
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/* Check for boot flash type */
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boot_nor = boot_nand = 0;
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if (nlm_chip_is_xls()) {
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/* On XLS, check boot from NAND bit (GPIO reset reg bit 16) */
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if (gpio_resetcfg & (1 << 16))
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boot_nand = 1;
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/* check boot from PCMCIA, (GPIO reset reg bit 15 */
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if ((gpio_resetcfg & (1 << 15)) == 0)
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boot_nor = 1; /* not set, booted from NOR */
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} else { /* XLR */
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/* check boot from PCMCIA (bit 16 in GPIO reset on XLR) */
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if ((gpio_resetcfg & (1 << 16)) == 0)
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boot_nor = 1; /* not set, booted from NOR */
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}
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/* boot flash at chip select 0 */
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cs = 0;
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if (boot_nand) {
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nand_priv.cs = cs;
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nand_priv.flash_mmio = flash_mmio;
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setup_flash_resource(flash_mmio, flash_map_base, cs,
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xlr_nand_res);
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/* Initialize NAND flash at CS 0 */
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nlm_write_reg(flash_mmio, FLASH_CSDEV_PARM(cs),
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FLASH_NAND_CSDEV_PARAM);
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nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMA(cs),
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FLASH_NAND_CSTIME_PARAMA);
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nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMB(cs),
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FLASH_NAND_CSTIME_PARAMB);
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pr_info("ChipSelect %d: NAND Flash %pR\n", cs, xlr_nand_res);
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return platform_device_register(&xlr_nand_dev);
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}
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if (boot_nor) {
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setup_flash_resource(flash_mmio, flash_map_base, cs,
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xlr_nor_res);
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pr_info("ChipSelect %d: NOR Flash %pR\n", cs, xlr_nor_res);
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return platform_device_register(&xlr_nor_dev);
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}
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return 0;
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}
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arch_initcall(xlr_flash_init);
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