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net: ethernet: xilinx_emaclite: set protocol selector bits when writing ANAR 

This patch sets the protocol selector bits (4:0) of the PHY's MII_ADVERTISE
register (ANAR) when writing ADVERTISE_ALL. The protocol selector bits are
indicating IEEE 803.3u support and are fixed / read-only on some PHYs. Not
setting them correctly on others (like TI DP83630) makes the PHY fall back
to 10M HDX mode which should be avoided.

Tested for TI DP83630 PHY on Microblaze platform.

Signed-off-by: Jens Renner <renner@efe-gmbh.de>
Tested-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jens Renner \(EFE\) 2013-06-03 04:32:52 +00:00 committed by David S. Miller
parent 44dbc78ee4
commit 3a5395b3d5
1 changed files with 2 additions and 1 deletions
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3
drivers/net/ethernet/xilinx/xilinx_emaclite.c
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@ -946,7 +946,8 @@ static int xemaclite_open(struct net_device *dev)
phy_write(lp->phy_dev, MII_CTRL1000, 0);
/* Advertise only 10 and 100mbps full/half duplex speeds */
phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL);
phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL |
ADVERTISE_CSMA);
/* Restart auto negotiation */
bmcr = phy_read(lp->phy_dev, MII_BMCR);