Blackfin: punt dead cache locking code
No one uses these functions, and some are duplicate of existing C code. So just punt the whole thing. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
0198b3bcae
commit
3aa670419a
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@ -917,10 +917,6 @@ comment "Cache Support"
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config BFIN_ICACHE
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bool "Enable ICACHE"
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default y
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config BFIN_ICACHE_LOCK
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bool "Enable Instruction Cache Locking"
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depends on BFIN_ICACHE
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default n
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config BFIN_EXTMEM_ICACHEABLE
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bool "Enable ICACHE for external memory"
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depends on BFIN_ICACHE
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@ -99,11 +99,6 @@ extern unsigned long bfin_sic_iwr[];
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extern unsigned vr_wakeup;
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extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
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#ifdef CONFIG_BFIN_ICACHE_LOCK
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extern void cache_grab_lock(int way);
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extern void bfin_cache_lock(int way);
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#endif
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#endif
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#endif /* _BLACKFIN_H_ */
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@ -1238,57 +1238,6 @@ static int show_cpuinfo(struct seq_file *m, void *v)
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#ifdef __ARCH_SYNC_CORE_ICACHE
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seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", cpudata->icache_invld_count);
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#endif
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#ifdef CONFIG_BFIN_ICACHE_LOCK
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switch ((cpudata->imemctl >> 3) & WAYALL_L) {
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case WAY0_L:
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seq_printf(m, "Way0 Locked-Down\n");
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break;
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case WAY1_L:
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seq_printf(m, "Way1 Locked-Down\n");
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break;
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case WAY01_L:
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seq_printf(m, "Way0,Way1 Locked-Down\n");
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break;
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case WAY2_L:
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seq_printf(m, "Way2 Locked-Down\n");
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break;
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case WAY02_L:
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seq_printf(m, "Way0,Way2 Locked-Down\n");
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break;
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case WAY12_L:
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seq_printf(m, "Way1,Way2 Locked-Down\n");
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break;
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case WAY012_L:
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seq_printf(m, "Way0,Way1 & Way2 Locked-Down\n");
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break;
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case WAY3_L:
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seq_printf(m, "Way3 Locked-Down\n");
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break;
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case WAY03_L:
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seq_printf(m, "Way0,Way3 Locked-Down\n");
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break;
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case WAY13_L:
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seq_printf(m, "Way1,Way3 Locked-Down\n");
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break;
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case WAY013_L:
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seq_printf(m, "Way 0,Way1,Way3 Locked-Down\n");
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break;
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case WAY32_L:
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seq_printf(m, "Way3,Way2 Locked-Down\n");
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break;
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case WAY320_L:
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seq_printf(m, "Way3,Way2,Way0 Locked-Down\n");
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break;
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case WAY321_L:
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seq_printf(m, "Way3,Way2,Way1 Locked-Down\n");
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break;
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case WAYALL_L:
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seq_printf(m, "All Ways are locked\n");
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break;
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default:
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seq_printf(m, "No Ways are locked\n");
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}
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#endif
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if (cpu_num != num_possible_cpus() - 1)
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return 0;
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@ -6,7 +6,6 @@ obj-y := \
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cache.o cache-c.o entry.o head.o \
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interrupt.o arch_checks.o ints-priority.o
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obj-$(CONFIG_BFIN_ICACHE_LOCK) += lock.o
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obj-$(CONFIG_PM) += pm.o dpmc_modes.o
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obj-$(CONFIG_CPU_FREQ) += cpufreq.o
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obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
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@ -1,223 +0,0 @@
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/*
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* File: arch/blackfin/mach-common/lock.S
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* Based on:
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* Author: LG Soft India
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*
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* Created: ?
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* Description: kernel locks
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/linkage.h>
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#include <asm/blackfin.h>
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.text
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/* When you come here, it is assumed that
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* R0 - Which way to be locked
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*/
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ENTRY(_cache_grab_lock)
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[--SP]=( R7:0,P5:0 );
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P1.H = HI(IMEM_CONTROL);
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P1.L = LO(IMEM_CONTROL);
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P5.H = HI(ICPLB_ADDR0);
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P5.L = LO(ICPLB_ADDR0);
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P4.H = HI(ICPLB_DATA0);
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P4.L = LO(ICPLB_DATA0);
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R7 = R0;
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/* If the code of interest already resides in the cache
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* invalidate the entire cache itself.
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* invalidate_entire_icache;
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*/
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SP += -12;
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[--SP] = RETS;
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CALL _invalidate_entire_icache;
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RETS = [SP++];
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SP += 12;
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/* Disable the Interrupts*/
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CLI R3;
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.LLOCK_WAY:
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/* Way0 - 0xFFA133E0
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* Way1 - 0xFFA137E0
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* Way2 - 0xFFA13BE0 Total Way Size = 4K
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* Way3 - 0xFFA13FE0
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*/
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/* Procedure Ex. -Set the locks for other ways by setting ILOC[3:1]
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* Only Way0 of the instruction cache can now be
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* replaced by a new code
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*/
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R5 = R7;
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CC = BITTST(R7,0);
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IF CC JUMP .LCLEAR1;
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R7 = 0;
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BITSET(R7,0);
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JUMP .LDONE1;
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.LCLEAR1:
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R7 = 0;
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BITCLR(R7,0);
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.LDONE1: R4 = R7 << 3;
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R7 = [P1];
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R7 = R7 | R4;
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SSYNC; /* SSYNC required writing to IMEM_CONTROL. */
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.align 8;
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[P1] = R7;
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SSYNC;
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R7 = R5;
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CC = BITTST(R7,1);
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IF CC JUMP .LCLEAR2;
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R7 = 0;
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BITSET(R7,1);
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JUMP .LDONE2;
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.LCLEAR2:
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R7 = 0;
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BITCLR(R7,1);
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.LDONE2: R4 = R7 << 3;
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R7 = [P1];
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R7 = R7 | R4;
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SSYNC; /* SSYNC required writing to IMEM_CONTROL. */
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.align 8;
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[P1] = R7;
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SSYNC;
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R7 = R5;
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CC = BITTST(R7,2);
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IF CC JUMP .LCLEAR3;
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R7 = 0;
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BITSET(R7,2);
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JUMP .LDONE3;
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.LCLEAR3:
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R7 = 0;
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BITCLR(R7,2);
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.LDONE3: R4 = R7 << 3;
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R7 = [P1];
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R7 = R7 | R4;
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SSYNC; /* SSYNC required writing to IMEM_CONTROL. */
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.align 8;
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[P1] = R7;
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SSYNC;
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R7 = R5;
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CC = BITTST(R7,3);
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IF CC JUMP .LCLEAR4;
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R7 = 0;
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BITSET(R7,3);
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JUMP .LDONE4;
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.LCLEAR4:
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R7 = 0;
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BITCLR(R7,3);
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.LDONE4: R4 = R7 << 3;
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R7 = [P1];
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R7 = R7 | R4;
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SSYNC; /* SSYNC required writing to IMEM_CONTROL. */
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.align 8;
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[P1] = R7;
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SSYNC;
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STI R3;
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( R7:0,P5:0 ) = [SP++];
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RTS;
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ENDPROC(_cache_grab_lock)
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/* After the execution of critical code, the code is now locked into
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* the cache way. Now we need to set ILOC.
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*
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* R0 - Which way to be locked
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*/
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ENTRY(_bfin_cache_lock)
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[--SP]=( R7:0,P5:0 );
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P1.H = HI(IMEM_CONTROL);
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P1.L = LO(IMEM_CONTROL);
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/* Disable the Interrupts*/
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CLI R3;
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R7 = [P1];
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R2 = ~(0x78) (X); /* mask out ILOC */
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R7 = R7 & R2;
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R0 = R0 << 3;
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R7 = R0 | R7;
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SSYNC; /* SSYNC required writing to IMEM_CONTROL. */
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.align 8;
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[P1] = R7;
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SSYNC;
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/* Renable the Interrupts */
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STI R3;
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( R7:0,P5:0 ) = [SP++];
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RTS;
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ENDPROC(_bfin_cache_lock)
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/* Invalidate the Entire Instruction cache by
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* disabling IMC bit
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*/
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ENTRY(_invalidate_entire_icache)
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[--SP] = ( R7:5);
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P0.L = LO(IMEM_CONTROL);
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P0.H = HI(IMEM_CONTROL);
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R7 = [P0];
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/* Clear the IMC bit , All valid bits in the instruction
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* cache are set to the invalid state
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*/
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BITCLR(R7,IMC_P);
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CLI R6;
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SSYNC; /* SSYNC required before invalidating cache. */
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.align 8;
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[P0] = R7;
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SSYNC;
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STI R6;
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/* Configures the instruction cache agian */
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R6 = (IMC | ENICPLB);
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R7 = R7 | R6;
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CLI R6;
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SSYNC; /* SSYNC required before writing to IMEM_CONTROL. */
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.align 8;
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[P0] = R7;
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SSYNC;
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STI R6;
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( R7:5) = [SP++];
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RTS;
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ENDPROC(_invalidate_entire_icache)
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