cxgb4: fix large delays in PTP synchronization
[ Upstream commitbd019427bf
] Fetching PTP sync information from mailbox is slow and can take up to 10 milliseconds. Reduce this unnecessary delay by directly reading the information from the corresponding registers. Fixes:9c33e4208b
("cxgb4: Add PTP Hardware Clock (PHC) support") Signed-off-by: Manoj Malviya <manojmalviya@chelsio.com> Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -311,32 +311,17 @@ static int cxgb4_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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*/
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static int cxgb4_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
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{
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struct adapter *adapter = (struct adapter *)container_of(ptp,
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struct adapter, ptp_clock_info);
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struct fw_ptp_cmd c;
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struct adapter *adapter = container_of(ptp, struct adapter,
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ptp_clock_info);
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u64 ns;
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int err;
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memset(&c, 0, sizeof(c));
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c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PTP_CMD) |
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FW_CMD_REQUEST_F |
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FW_CMD_READ_F |
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FW_PTP_CMD_PORTID_V(0));
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c.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(sizeof(c) / 16));
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c.u.ts.sc = FW_PTP_SC_GET_TIME;
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err = t4_wr_mbox(adapter, adapter->mbox, &c, sizeof(c), &c);
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if (err < 0) {
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dev_err(adapter->pdev_dev,
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"PTP: %s error %d\n", __func__, -err);
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return err;
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}
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ns = t4_read_reg(adapter, T5_PORT_REG(0, MAC_PORT_PTP_SUM_LO_A));
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ns |= (u64)t4_read_reg(adapter,
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T5_PORT_REG(0, MAC_PORT_PTP_SUM_HI_A)) << 32;
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/* convert to timespec*/
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ns = be64_to_cpu(c.u.ts.tm);
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*ts = ns_to_timespec64(ns);
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return err;
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return 0;
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}
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/**
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@ -1900,6 +1900,9 @@
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#define MAC_PORT_CFG2_A 0x818
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#define MAC_PORT_PTP_SUM_LO_A 0x990
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#define MAC_PORT_PTP_SUM_HI_A 0x994
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#define MPS_CMN_CTL_A 0x9000
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#define COUNTPAUSEMCRX_S 5
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