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cxgb4: fix large delays in PTP synchronization 

[ Upstream commit bd019427bf ]

Fetching PTP sync information from mailbox is slow and can take
up to 10 milliseconds. Reduce this unnecessary delay by directly
reading the information from the corresponding registers.

Fixes: 9c33e4208b ("cxgb4: Add PTP Hardware Clock (PHC) support")
Signed-off-by: Manoj Malviya <manojmalviya@chelsio.com>
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Rahul Lakkireddy 2020-04-20 15:26:54 +05:30 committed by Greg Kroah-Hartman
parent d02f424265
commit 3b759befd7
2 changed files with 9 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c
View File

@ -311,32 +311,17 @@ static int cxgb4_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
*/ */
static int cxgb4_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) static int cxgb4_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
{ {
struct adapter *adapter = (struct adapter *)container_of(ptp, struct adapter *adapter = container_of(ptp, struct adapter,
struct adapter, ptp_clock_info); ptp_clock_info);
struct fw_ptp_cmd c;
u64 ns; u64 ns;
int err;
memset(&c, 0, sizeof(c)); ns = t4_read_reg(adapter, T5_PORT_REG(0, MAC_PORT_PTP_SUM_LO_A));
c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PTP_CMD) | ns |= (u64)t4_read_reg(adapter,
FW_CMD_REQUEST_F | T5_PORT_REG(0, MAC_PORT_PTP_SUM_HI_A)) << 32;
FW_CMD_READ_F |
FW_PTP_CMD_PORTID_V(0));
c.retval_len16 = cpu_to_be32(FW_CMD_LEN16_V(sizeof(c) / 16));
c.u.ts.sc = FW_PTP_SC_GET_TIME;
err = t4_wr_mbox(adapter, adapter->mbox, &c, sizeof(c), &c);
if (err < 0) {
dev_err(adapter->pdev_dev,
"PTP: %s error %d\n", __func__, -err);
return err;
}
/* convert to timespec*/ /* convert to timespec*/
ns = be64_to_cpu(c.u.ts.tm);
*ts = ns_to_timespec64(ns); *ts = ns_to_timespec64(ns);
return 0;
return err;
} }
/** /**

3
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
View File

@ -1900,6 +1900,9 @@
#define MAC_PORT_CFG2_A 0x818 #define MAC_PORT_CFG2_A 0x818
#define MAC_PORT_PTP_SUM_LO_A 0x990
#define MAC_PORT_PTP_SUM_HI_A 0x994
#define MPS_CMN_CTL_A 0x9000 #define MPS_CMN_CTL_A 0x9000
#define COUNTPAUSEMCRX_S 5 #define COUNTPAUSEMCRX_S 5