arm64: dts: Add basic DT to support Spreadtrum's SP9860G
SC9860G is a 8 cores of A53 SoC with 4G LTE support SoC from Spreadtrum. According to regular hierarchy of sprd dts, whale2.dtsi contains SoC peripherals IP nodes, sc9860.dtsi contains stuff related to ARM core stuff and sp9860g dts is for the board level. Signed-off-by: Orson Zhai <orson.zhai@spreadtrum.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Orson Zhai
Arnd Bergmann
parent
052bc8fc8f
commit
3c0e3abd5e
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@ -1,4 +1,5 @@
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dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb
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dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \
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sp9860g-1h10.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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@ -0,0 +1,569 @@
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/*
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* Spreadtrum SC9860 SoC
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*
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* Copyright (C) 2016, Spreadtrum Communications Inc.
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "whale2.dtsi"
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/ {
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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};
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CPU0: cpu@530000 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x530000>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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};
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CPU1: cpu@530001 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x530001>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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};
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CPU2: cpu@530002 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x530002>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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};
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CPU3: cpu@530003 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x530003>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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};
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CPU4: cpu@530100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x530100>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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};
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CPU5: cpu@530101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x530101>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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};
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CPU6: cpu@530102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x530102>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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};
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CPU7: cpu@530103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x530103>;
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enable-method = "psci";
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cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
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};
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};
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idle-states{
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entry-method = "arm,psci";
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CORE_PD: core_pd {
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compatible = "arm,idle-state";
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entry-latency-us = <1000>;
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exit-latency-us = <700>;
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min-residency-us = <2500>;
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local-timer-stop;
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arm,psci-suspend-param = <0x00010002>;
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};
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CLUSTER_PD: cluster_pd {
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compatible = "arm,idle-state";
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entry-latency-us = <1000>;
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exit-latency-us = <1000>;
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min-residency-us = <3000>;
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local-timer-stop;
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arm,psci-suspend-param = <0x01010003>;
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};
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};
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gic: interrupt-controller@12001000 {
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compatible = "arm,gic-400";
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reg = <0 0x12001000 0 0x1000>,
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<0 0x12002000 0 0x2000>,
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<0 0x12004000 0 0x2000>,
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<0 0x12006000 0 0x2000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
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| IRQ_TYPE_LEVEL_HIGH)>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8)
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| IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8)
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| IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8)
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| IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8)
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| IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&CPU0>,
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<&CPU1>,
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<&CPU2>,
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<&CPU3>,
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<&CPU4>,
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<&CPU5>,
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<&CPU6>,
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<&CPU7>;
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};
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soc {
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funnel@10001000 { /* SoC Funnel */
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0 0x10001000 0 0x1000>;
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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soc_funnel_out_port: endpoint {
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remote-endpoint = <&etb_in>;
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};
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};
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port@1 {
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reg = <0>;
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soc_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint =
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<&main_funnel_out_port>;
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};
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};
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port@2 {
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reg = <4>;
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soc_funnel_in_port1: endpoint {
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slave-mode;
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remote-endpioint =
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<&stm_out_port>;
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};
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};
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};
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};
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etb@10003000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0 0x10003000 0 0x1000>;
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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port {
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etb_in: endpoint {
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slave-mode;
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remote-endpoint =
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<&soc_funnel_out_port>;
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};
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};
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};
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stm@10006000 {
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compatible = "arm,coresight-stm", "arm,primecell";
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reg = <0 0x10006000 0 0x1000>,
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<0 0x01000000 0 0x180000>;
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reg-names = "stm-base", "stm-stimulus-base";
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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port {
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stm_out_port: endpoint {
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remote-endpoint =
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<&soc_funnel_in_port1>;
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};
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};
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};
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funnel@11001000 { /* Cluster0 Funnel */
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0 0x11001000 0 0x1000>;
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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cluster0_funnel_out_port: endpoint {
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remote-endpoint =
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<&cluster0_etf_in>;
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};
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};
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port@1 {
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reg = <0>;
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cluster0_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&etm0_out>;
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};
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};
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port@2 {
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reg = <1>;
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cluster0_funnel_in_port1: endpoint {
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slave-mode;
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remote-endpoint = <&etm1_out>;
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};
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};
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port@3 {
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reg = <2>;
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cluster0_funnel_in_port2: endpoint {
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slave-mode;
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remote-endpoint = <&etm2_out>;
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};
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};
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port@4 {
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reg = <4>;
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cluster0_funnel_in_port3: endpoint {
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slave-mode;
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remote-endpoint = <&etm3_out>;
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};
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};
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};
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};
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funnel@11002000 { /* Cluster1 Funnel */
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0 0x11002000 0 0x1000>;
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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cluster1_funnel_out_port: endpoint {
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remote-endpoint =
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<&cluster1_etf_in>;
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};
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};
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port@1 {
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reg = <0>;
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cluster1_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint = <&etm4_out>;
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};
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};
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port@2 {
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reg = <1>;
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cluster1_funnel_in_port1: endpoint {
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slave-mode;
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remote-endpoint = <&etm5_out>;
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};
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};
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port@3 {
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reg = <2>;
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cluster1_funnel_in_port2: endpoint {
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slave-mode;
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remote-endpoint = <&etm6_out>;
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};
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};
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port@4 {
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reg = <3>;
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cluster1_funnel_in_port3: endpoint {
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slave-mode;
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remote-endpoint = <&etm7_out>;
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};
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};
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};
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};
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etf@11003000 { /* ETF on Cluster0 */
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0 0x11003000 0 0x1000>;
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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cluster0_etf_out: endpoint {
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remote-endpoint =
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<&main_funnel_in_port0>;
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};
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};
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port@1 {
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reg = <0>;
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cluster0_etf_in: endpoint {
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slave-mode;
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remote-endpoint =
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<&cluster0_funnel_out_port>;
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};
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};
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};
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};
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etf@11004000 { /* ETF on Cluster1 */
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0 0x11004000 0 0x1000>;
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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cluster1_etf_out: endpoint {
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remote-endpoint =
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<&main_funnel_in_port1>;
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};
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};
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port@1 {
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reg = <0>;
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cluster1_etf_in: endpoint {
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slave-mode;
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remote-endpoint =
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<&cluster1_funnel_out_port>;
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};
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};
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};
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};
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funnel@11005000 { /* Main Funnel */
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0 0x11005000 0 0x1000>;
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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main_funnel_out_port: endpoint {
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remote-endpoint =
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<&soc_funnel_in_port0>;
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};
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};
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port@1 {
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reg = <0>;
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main_funnel_in_port0: endpoint {
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slave-mode;
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remote-endpoint =
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<&cluster0_etf_out>;
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};
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};
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port@2 {
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reg = <1>;
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main_funnel_in_port1: endpoint {
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slave-mode;
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remote-endpoint =
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<&cluster1_etf_out>;
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};
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};
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};
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};
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etm@11440000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x11440000 0 0x1000>;
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cpu = <&CPU0>;
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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port {
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etm0_out: endpoint {
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remote-endpoint =
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<&cluster0_funnel_in_port0>;
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};
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};
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};
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etm@11540000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x11540000 0 0x1000>;
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cpu = <&CPU1>;
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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port {
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etm1_out: endpoint {
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remote-endpoint =
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<&cluster0_funnel_in_port1>;
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};
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};
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};
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etm@11640000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x11640000 0 0x1000>;
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cpu = <&CPU2>;
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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port {
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etm2_out: endpoint {
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remote-endpoint =
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<&cluster0_funnel_in_port2>;
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};
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};
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};
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etm@11740000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0 0x11740000 0 0x1000>;
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cpu = <&CPU3>;
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clocks = <&ext_26m>;
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clock-names = "apb_pclk";
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port {
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etm3_out: endpoint {
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remote-endpoint =
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<&cluster0_funnel_in_port3>;
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};
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};
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};
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|
||||
etm@11840000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x11840000 0 0x1000>;
|
||||
cpu = <&CPU4>;
|
||||
clocks = <&ext_26m>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
port {
|
||||
etm4_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&cluster1_funnel_in_port0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@11940000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x11940000 0 0x1000>;
|
||||
cpu = <&CPU5>;
|
||||
clocks = <&ext_26m>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
port {
|
||||
etm5_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&cluster1_funnel_in_port1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@11a40000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x11a40000 0 0x1000>;
|
||||
cpu = <&CPU6>;
|
||||
clocks = <&ext_26m>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
port {
|
||||
etm6_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&cluster1_funnel_in_port2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
etm@11b40000 {
|
||||
compatible = "arm,coresight-etm4x", "arm,primecell";
|
||||
reg = <0 0x11b40000 0 0x1000>;
|
||||
cpu = <&CPU7>;
|
||||
clocks = <&ext_26m>;
|
||||
clock-names = "apb_pclk";
|
||||
|
||||
port {
|
||||
etm7_out: endpoint {
|
||||
remote-endpoint =
|
||||
<&cluster1_funnel_in_port3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* Spreadtrum SP9860g board
|
||||
*
|
||||
* Copyright (C) 2017, Spreadtrum Communications Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "sc9860.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Spreadtrum SP9860G 3GFHD Board";
|
||||
|
||||
compatible = "sprd,sp9860g-1h10", "sprd,sc9860";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0; /* for Bluetooth */
|
||||
serial1 = &uart1; /* UART console */
|
||||
serial2 = &uart2; /* Reserved */
|
||||
serial3 = &uart3; /* for GPS */
|
||||
};
|
||||
|
||||
memory{
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0 0x60000000>,
|
||||
<0x1 0x80000000 0 0x60000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial1:115200n8";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Spreadtrum Whale2 platform peripherals
|
||||
*
|
||||
* Copyright (C) 2016, Spreadtrum Communications Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
*/
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
ap-apb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x70000000 0x10000000>;
|
||||
|
||||
uart0: serial@0 {
|
||||
compatible = "sprd,sc9860-uart",
|
||||
"sprd,sc9836-uart";
|
||||
reg = <0x0 0x100>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ext_26m>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@100000 {
|
||||
compatible = "sprd,sc9860-uart",
|
||||
"sprd,sc9836-uart";
|
||||
reg = <0x100000 0x100>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ext_26m>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@200000 {
|
||||
compatible = "sprd,sc9860-uart",
|
||||
"sprd,sc9836-uart";
|
||||
reg = <0x200000 0x100>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ext_26m>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@300000 {
|
||||
compatible = "sprd,sc9860-uart",
|
||||
"sprd,sc9836-uart";
|
||||
reg = <0x300000 0x100>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ext_26m>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
ext_26m: ext-26m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
clock-output-names = "ext_26m";
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue