mtd: mtk-nor: new Mediatek serial flash controller driver
Add spi nor flash driver for mediatek controller Signed-off-by: Bayi Cheng <bayi.cheng@mediatek.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
Bayi Cheng
Brian Norris
parent
72eaec21b0
commit
3ce351b535
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@ -7,6 +7,13 @@ menuconfig MTD_SPI_NOR
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if MTD_SPI_NOR
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config MTD_MT81xx_NOR
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tristate "Mediatek MT81xx SPI NOR flash controller"
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help
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This enables access to SPI NOR flash, using MT81xx SPI NOR flash
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controller. This controller does not support generic SPI BUS, it only
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supports SPI NOR Flash.
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config MTD_SPI_NOR_USE_4K_SECTORS
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bool "Use small 4096 B erase sectors"
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default y
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@ -1,3 +1,4 @@
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obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
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obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o
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obj-$(CONFIG_MTD_MT81xx_NOR) += mtk-quadspi.o
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obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
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@ -0,0 +1,486 @@
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/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Bayi Cheng <bayi.cheng@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/spi-nor.h>
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#define MTK_NOR_CMD_REG 0x00
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#define MTK_NOR_CNT_REG 0x04
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#define MTK_NOR_RDSR_REG 0x08
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#define MTK_NOR_RDATA_REG 0x0c
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#define MTK_NOR_RADR0_REG 0x10
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#define MTK_NOR_RADR1_REG 0x14
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#define MTK_NOR_RADR2_REG 0x18
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#define MTK_NOR_WDATA_REG 0x1c
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#define MTK_NOR_PRGDATA0_REG 0x20
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#define MTK_NOR_PRGDATA1_REG 0x24
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#define MTK_NOR_PRGDATA2_REG 0x28
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#define MTK_NOR_PRGDATA3_REG 0x2c
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#define MTK_NOR_PRGDATA4_REG 0x30
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#define MTK_NOR_PRGDATA5_REG 0x34
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#define MTK_NOR_SHREG0_REG 0x38
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#define MTK_NOR_SHREG1_REG 0x3c
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#define MTK_NOR_SHREG2_REG 0x40
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#define MTK_NOR_SHREG3_REG 0x44
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#define MTK_NOR_SHREG4_REG 0x48
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#define MTK_NOR_SHREG5_REG 0x4c
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#define MTK_NOR_SHREG6_REG 0x50
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#define MTK_NOR_SHREG7_REG 0x54
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#define MTK_NOR_SHREG8_REG 0x58
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#define MTK_NOR_SHREG9_REG 0x5c
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#define MTK_NOR_CFG1_REG 0x60
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#define MTK_NOR_CFG2_REG 0x64
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#define MTK_NOR_CFG3_REG 0x68
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#define MTK_NOR_STATUS0_REG 0x70
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#define MTK_NOR_STATUS1_REG 0x74
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#define MTK_NOR_STATUS2_REG 0x78
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#define MTK_NOR_STATUS3_REG 0x7c
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#define MTK_NOR_FLHCFG_REG 0x84
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#define MTK_NOR_TIME_REG 0x94
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#define MTK_NOR_PP_DATA_REG 0x98
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#define MTK_NOR_PREBUF_STUS_REG 0x9c
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#define MTK_NOR_DELSEL0_REG 0xa0
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#define MTK_NOR_DELSEL1_REG 0xa4
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#define MTK_NOR_INTRSTUS_REG 0xa8
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#define MTK_NOR_INTREN_REG 0xac
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#define MTK_NOR_CHKSUM_CTL_REG 0xb8
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#define MTK_NOR_CHKSUM_REG 0xbc
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#define MTK_NOR_CMD2_REG 0xc0
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#define MTK_NOR_WRPROT_REG 0xc4
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#define MTK_NOR_RADR3_REG 0xc8
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#define MTK_NOR_DUAL_REG 0xcc
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#define MTK_NOR_DELSEL2_REG 0xd0
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#define MTK_NOR_DELSEL3_REG 0xd4
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#define MTK_NOR_DELSEL4_REG 0xd8
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/* commands for mtk nor controller */
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#define MTK_NOR_READ_CMD 0x0
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#define MTK_NOR_RDSR_CMD 0x2
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#define MTK_NOR_PRG_CMD 0x4
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#define MTK_NOR_WR_CMD 0x10
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#define MTK_NOR_PIO_WR_CMD 0x90
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#define MTK_NOR_WRSR_CMD 0x20
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#define MTK_NOR_PIO_READ_CMD 0x81
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#define MTK_NOR_WR_BUF_ENABLE 0x1
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#define MTK_NOR_WR_BUF_DISABLE 0x0
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#define MTK_NOR_ENABLE_SF_CMD 0x30
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#define MTK_NOR_DUAD_ADDR_EN 0x8
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#define MTK_NOR_QUAD_READ_EN 0x4
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#define MTK_NOR_DUAL_ADDR_EN 0x2
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#define MTK_NOR_DUAL_READ_EN 0x1
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#define MTK_NOR_DUAL_DISABLE 0x0
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#define MTK_NOR_FAST_READ 0x1
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#define SFLASH_WRBUF_SIZE 128
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/* Can shift up to 48 bits (6 bytes) of TX/RX */
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#define MTK_NOR_MAX_RX_TX_SHIFT 6
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/* can shift up to 56 bits (7 bytes) transfer by MTK_NOR_PRG_CMD */
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#define MTK_NOR_MAX_SHIFT 7
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/* Helpers for accessing the program data / shift data registers */
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#define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n))
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#define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n))
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struct mt8173_nor {
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struct spi_nor nor;
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struct device *dev;
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void __iomem *base; /* nor flash base address */
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struct clk *spi_clk;
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struct clk *nor_clk;
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};
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static void mt8173_nor_set_read_mode(struct mt8173_nor *mt8173_nor)
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{
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struct spi_nor *nor = &mt8173_nor->nor;
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switch (nor->flash_read) {
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case SPI_NOR_FAST:
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writeb(nor->read_opcode, mt8173_nor->base +
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MTK_NOR_PRGDATA3_REG);
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writeb(MTK_NOR_FAST_READ, mt8173_nor->base +
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MTK_NOR_CFG1_REG);
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break;
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case SPI_NOR_DUAL:
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writeb(nor->read_opcode, mt8173_nor->base +
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MTK_NOR_PRGDATA3_REG);
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writeb(MTK_NOR_DUAL_READ_EN, mt8173_nor->base +
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MTK_NOR_DUAL_REG);
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break;
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case SPI_NOR_QUAD:
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writeb(nor->read_opcode, mt8173_nor->base +
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MTK_NOR_PRGDATA4_REG);
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writeb(MTK_NOR_QUAD_READ_EN, mt8173_nor->base +
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MTK_NOR_DUAL_REG);
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break;
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default:
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writeb(MTK_NOR_DUAL_DISABLE, mt8173_nor->base +
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MTK_NOR_DUAL_REG);
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break;
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}
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}
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static int mt8173_nor_execute_cmd(struct mt8173_nor *mt8173_nor, u8 cmdval)
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{
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int reg;
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u8 val = cmdval & 0x1f;
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writeb(cmdval, mt8173_nor->base + MTK_NOR_CMD_REG);
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return readl_poll_timeout(mt8173_nor->base + MTK_NOR_CMD_REG, reg,
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!(reg & val), 100, 10000);
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}
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static int mt8173_nor_do_tx_rx(struct mt8173_nor *mt8173_nor, u8 op,
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u8 *tx, int txlen, u8 *rx, int rxlen)
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{
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int len = 1 + txlen + rxlen;
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int i, ret, idx;
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if (len > MTK_NOR_MAX_SHIFT)
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return -EINVAL;
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writeb(len * 8, mt8173_nor->base + MTK_NOR_CNT_REG);
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/* start at PRGDATA5, go down to PRGDATA0 */
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idx = MTK_NOR_MAX_RX_TX_SHIFT - 1;
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/* opcode */
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writeb(op, mt8173_nor->base + MTK_NOR_PRG_REG(idx));
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idx--;
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/* program TX data */
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for (i = 0; i < txlen; i++, idx--)
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writeb(tx[i], mt8173_nor->base + MTK_NOR_PRG_REG(idx));
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/* clear out rest of TX registers */
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while (idx >= 0) {
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writeb(0, mt8173_nor->base + MTK_NOR_PRG_REG(idx));
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idx--;
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}
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ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PRG_CMD);
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if (ret)
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return ret;
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/* restart at first RX byte */
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idx = rxlen - 1;
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/* read out RX data */
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for (i = 0; i < rxlen; i++, idx--)
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rx[i] = readb(mt8173_nor->base + MTK_NOR_SHREG(idx));
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return 0;
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}
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/* Do a WRSR (Write Status Register) command */
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static int mt8173_nor_wr_sr(struct mt8173_nor *mt8173_nor, u8 sr)
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{
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writeb(sr, mt8173_nor->base + MTK_NOR_PRGDATA5_REG);
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writeb(8, mt8173_nor->base + MTK_NOR_CNT_REG);
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return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WRSR_CMD);
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}
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static int mt8173_nor_write_buffer_enable(struct mt8173_nor *mt8173_nor)
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{
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u8 reg;
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/* the bit0 of MTK_NOR_CFG2_REG is pre-fetch buffer
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* 0: pre-fetch buffer use for read
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* 1: pre-fetch buffer use for page program
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*/
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writel(MTK_NOR_WR_BUF_ENABLE, mt8173_nor->base + MTK_NOR_CFG2_REG);
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return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg,
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0x01 == (reg & 0x01), 100, 10000);
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}
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static int mt8173_nor_write_buffer_disable(struct mt8173_nor *mt8173_nor)
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{
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u8 reg;
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writel(MTK_NOR_WR_BUF_DISABLE, mt8173_nor->base + MTK_NOR_CFG2_REG);
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return readb_poll_timeout(mt8173_nor->base + MTK_NOR_CFG2_REG, reg,
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MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100,
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10000);
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}
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static void mt8173_nor_set_addr(struct mt8173_nor *mt8173_nor, u32 addr)
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{
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int i;
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for (i = 0; i < 3; i++) {
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writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR0_REG + i * 4);
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addr >>= 8;
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}
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/* Last register is non-contiguous */
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writeb(addr & 0xff, mt8173_nor->base + MTK_NOR_RADR3_REG);
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}
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static int mt8173_nor_read(struct spi_nor *nor, loff_t from, size_t length,
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size_t *retlen, u_char *buffer)
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{
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int i, ret;
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int addr = (int)from;
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u8 *buf = (u8 *)buffer;
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struct mt8173_nor *mt8173_nor = nor->priv;
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/* set mode for fast read mode ,dual mode or quad mode */
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mt8173_nor_set_read_mode(mt8173_nor);
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mt8173_nor_set_addr(mt8173_nor, addr);
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for (i = 0; i < length; i++, (*retlen)++) {
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ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_READ_CMD);
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if (ret < 0)
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return ret;
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buf[i] = readb(mt8173_nor->base + MTK_NOR_RDATA_REG);
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}
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return 0;
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}
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static int mt8173_nor_write_single_byte(struct mt8173_nor *mt8173_nor,
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int addr, int length, u8 *data)
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{
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int i, ret;
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mt8173_nor_set_addr(mt8173_nor, addr);
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for (i = 0; i < length; i++) {
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ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_PIO_WR_CMD);
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if (ret < 0)
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return ret;
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writeb(*data++, mt8173_nor->base + MTK_NOR_WDATA_REG);
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}
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return 0;
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}
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static int mt8173_nor_write_buffer(struct mt8173_nor *mt8173_nor, int addr,
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const u8 *buf)
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{
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int i, bufidx, data;
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mt8173_nor_set_addr(mt8173_nor, addr);
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bufidx = 0;
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for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) {
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data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 |
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buf[bufidx + 1]<<8 | buf[bufidx];
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bufidx += 4;
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writel(data, mt8173_nor->base + MTK_NOR_PP_DATA_REG);
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}
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return mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_WR_CMD);
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}
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static void mt8173_nor_write(struct spi_nor *nor, loff_t to, size_t len,
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size_t *retlen, const u_char *buf)
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{
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int ret;
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struct mt8173_nor *mt8173_nor = nor->priv;
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ret = mt8173_nor_write_buffer_enable(mt8173_nor);
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if (ret < 0)
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dev_warn(mt8173_nor->dev, "write buffer enable failed!\n");
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while (len >= SFLASH_WRBUF_SIZE) {
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ret = mt8173_nor_write_buffer(mt8173_nor, to, buf);
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if (ret < 0)
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dev_err(mt8173_nor->dev, "write buffer failed!\n");
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len -= SFLASH_WRBUF_SIZE;
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to += SFLASH_WRBUF_SIZE;
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buf += SFLASH_WRBUF_SIZE;
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(*retlen) += SFLASH_WRBUF_SIZE;
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}
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ret = mt8173_nor_write_buffer_disable(mt8173_nor);
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if (ret < 0)
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dev_warn(mt8173_nor->dev, "write buffer disable failed!\n");
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if (len) {
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ret = mt8173_nor_write_single_byte(mt8173_nor, to, (int)len,
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(u8 *)buf);
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if (ret < 0)
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dev_err(mt8173_nor->dev, "write single byte failed!\n");
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(*retlen) += len;
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}
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}
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static int mt8173_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
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{
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int ret;
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struct mt8173_nor *mt8173_nor = nor->priv;
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switch (opcode) {
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case SPINOR_OP_RDSR:
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ret = mt8173_nor_execute_cmd(mt8173_nor, MTK_NOR_RDSR_CMD);
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if (ret < 0)
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return ret;
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if (len == 1)
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*buf = readb(mt8173_nor->base + MTK_NOR_RDSR_REG);
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else
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dev_err(mt8173_nor->dev, "len should be 1 for read status!\n");
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break;
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default:
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ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, NULL, 0, buf, len);
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break;
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}
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return ret;
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}
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static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
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int len)
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{
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int ret;
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struct mt8173_nor *mt8173_nor = nor->priv;
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switch (opcode) {
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case SPINOR_OP_WRSR:
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/* We only handle 1 byte */
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ret = mt8173_nor_wr_sr(mt8173_nor, *buf);
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break;
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default:
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ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0);
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if (ret)
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dev_warn(mt8173_nor->dev, "write reg failure!\n");
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break;
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}
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return ret;
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}
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static int __init mtk_nor_init(struct mt8173_nor *mt8173_nor,
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struct device_node *flash_node)
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{
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int ret;
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struct spi_nor *nor;
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/* initialize controller to accept commands */
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writel(MTK_NOR_ENABLE_SF_CMD, mt8173_nor->base + MTK_NOR_WRPROT_REG);
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nor = &mt8173_nor->nor;
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nor->dev = mt8173_nor->dev;
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nor->priv = mt8173_nor;
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spi_nor_set_flash_node(nor, flash_node);
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/* fill the hooks to spi nor */
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nor->read = mt8173_nor_read;
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nor->read_reg = mt8173_nor_read_reg;
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nor->write = mt8173_nor_write;
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nor->write_reg = mt8173_nor_write_reg;
|
||||
nor->mtd.owner = THIS_MODULE;
|
||||
nor->mtd.name = "mtk_nor";
|
||||
/* initialized with NULL */
|
||||
ret = spi_nor_scan(nor, NULL, SPI_NOR_DUAL);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return mtd_device_register(&nor->mtd, NULL, 0);
|
||||
}
|
||||
|
||||
static int mtk_nor_drv_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *flash_np;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
struct mt8173_nor *mt8173_nor;
|
||||
|
||||
if (!pdev->dev.of_node) {
|
||||
dev_err(&pdev->dev, "No DT found\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
mt8173_nor = devm_kzalloc(&pdev->dev, sizeof(*mt8173_nor), GFP_KERNEL);
|
||||
if (!mt8173_nor)
|
||||
return -ENOMEM;
|
||||
platform_set_drvdata(pdev, mt8173_nor);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
mt8173_nor->base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(mt8173_nor->base))
|
||||
return PTR_ERR(mt8173_nor->base);
|
||||
|
||||
mt8173_nor->spi_clk = devm_clk_get(&pdev->dev, "spi");
|
||||
if (IS_ERR(mt8173_nor->spi_clk))
|
||||
return PTR_ERR(mt8173_nor->spi_clk);
|
||||
|
||||
mt8173_nor->nor_clk = devm_clk_get(&pdev->dev, "sf");
|
||||
if (IS_ERR(mt8173_nor->nor_clk))
|
||||
return PTR_ERR(mt8173_nor->nor_clk);
|
||||
|
||||
mt8173_nor->dev = &pdev->dev;
|
||||
ret = clk_prepare_enable(mt8173_nor->spi_clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_prepare_enable(mt8173_nor->nor_clk);
|
||||
if (ret) {
|
||||
clk_disable_unprepare(mt8173_nor->spi_clk);
|
||||
return ret;
|
||||
}
|
||||
/* only support one attached flash */
|
||||
flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
|
||||
if (!flash_np) {
|
||||
dev_err(&pdev->dev, "no SPI flash device to configure\n");
|
||||
ret = -ENODEV;
|
||||
goto nor_free;
|
||||
}
|
||||
ret = mtk_nor_init(mt8173_nor, flash_np);
|
||||
|
||||
nor_free:
|
||||
if (ret) {
|
||||
clk_disable_unprepare(mt8173_nor->spi_clk);
|
||||
clk_disable_unprepare(mt8173_nor->nor_clk);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mtk_nor_drv_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mt8173_nor *mt8173_nor = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable_unprepare(mt8173_nor->spi_clk);
|
||||
clk_disable_unprepare(mt8173_nor->nor_clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id mtk_nor_of_ids[] = {
|
||||
{ .compatible = "mediatek,mt8173-nor"},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mtk_nor_of_ids);
|
||||
|
||||
static struct platform_driver mtk_nor_driver = {
|
||||
.probe = mtk_nor_drv_probe,
|
||||
.remove = mtk_nor_drv_remove,
|
||||
.driver = {
|
||||
.name = "mtk-nor",
|
||||
.of_match_table = mtk_nor_of_ids,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(mtk_nor_driver);
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_DESCRIPTION("MediaTek SPI NOR Flash Driver");
|
||||
Loading…
Reference in New Issue