mfd: ab5500 chip register access
The analog baseband chip ab5500 is a multi functional chip containing regulators, charging, gpio, USB and accessory detect. It also contain various multimedia functionalities like digital encoder and audio codec. The core driver added with this patch provides register access via i2c via PRCMU. Event handling implemented as irq_chip will come in future patches since it depends on PRCMU functionality not yet implemented. Signed-off-by: Mattias Wallin <mattias.wallin@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Mattias Wallin
Samuel Ortiz
parent
677df0c901
commit
3d5e2cabf1
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@ -563,6 +563,15 @@ config EZX_PCAP
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This enables the PCAP ASIC present on EZX Phones. This is
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needed for MMC, TouchScreen, Sound, USB, etc..
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config AB5500_CORE
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bool "ST-Ericsson AB5500 Mixed Signal Power Management chip"
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depends on ABX500_CORE && MFD_DB5500_PRCMU
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select MFD_CORE
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help
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Select this option to enable access to AB5500 power management
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chip. This connects to the db5500 chip via the I2C bus via PRCMU.
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This chip embeds various other multimedia funtionalities as well.
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config AB8500_CORE
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bool "ST-Ericsson AB8500 Mixed Signal Power Management chip"
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depends on GENERIC_HARDIRQS && ABX500_CORE
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@ -80,6 +80,7 @@ obj-$(CONFIG_ABX500_CORE) += abx500-core.o
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obj-$(CONFIG_AB3100_CORE) += ab3100-core.o
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obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o
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obj-$(CONFIG_AB3550_CORE) += ab3550-core.o
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obj-$(CONFIG_AB5500_CORE) += ab5500-core.o
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obj-$(CONFIG_AB8500_CORE) += ab8500-core.o ab8500-sysctrl.o
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obj-$(CONFIG_AB8500_DEBUG) += ab8500-debugfs.o
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obj-$(CONFIG_AB8500_GPADC) += ab8500-gpadc.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,140 @@
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/*
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* Copyright (C) ST-Ericsson 2011
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*
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* License Terms: GNU General Public License v2
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*/
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#ifndef MFD_AB5500_H
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#define MFD_AB5500_H
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#include <linux/device.h>
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enum ab5500_devid {
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AB5500_DEVID_ADC,
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AB5500_DEVID_LEDS,
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AB5500_DEVID_POWER,
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AB5500_DEVID_REGULATORS,
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AB5500_DEVID_SIM,
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AB5500_DEVID_RTC,
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AB5500_DEVID_CHARGER,
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AB5500_DEVID_FUELGAUGE,
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AB5500_DEVID_VIBRATOR,
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AB5500_DEVID_CODEC,
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AB5500_DEVID_USB,
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AB5500_DEVID_OTP,
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AB5500_DEVID_VIDEO,
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AB5500_DEVID_DBIECI,
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AB5500_DEVID_ONSWA,
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AB5500_NUM_DEVICES,
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};
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enum ab5500_banks {
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AB5500_BANK_VIT_IO_I2C_CLK_TST_OTP = 0,
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AB5500_BANK_VDDDIG_IO_I2C_CLK_TST = 1,
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AB5500_BANK_VDENC = 2,
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AB5500_BANK_SIM_USBSIM = 3,
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AB5500_BANK_LED = 4,
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AB5500_BANK_ADC = 5,
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AB5500_BANK_RTC = 6,
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AB5500_BANK_STARTUP = 7,
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AB5500_BANK_DBI_ECI = 8,
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AB5500_BANK_CHG = 9,
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AB5500_BANK_FG_BATTCOM_ACC = 10,
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AB5500_BANK_USB = 11,
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AB5500_BANK_IT = 12,
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AB5500_BANK_VIBRA = 13,
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AB5500_BANK_AUDIO_HEADSETUSB = 14,
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AB5500_NUM_BANKS = 15,
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};
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enum ab5500_banks_addr {
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AB5500_ADDR_VIT_IO_I2C_CLK_TST_OTP = 0x4A,
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AB5500_ADDR_VDDDIG_IO_I2C_CLK_TST = 0x4B,
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AB5500_ADDR_VDENC = 0x06,
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AB5500_ADDR_SIM_USBSIM = 0x04,
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AB5500_ADDR_LED = 0x10,
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AB5500_ADDR_ADC = 0x0A,
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AB5500_ADDR_RTC = 0x0F,
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AB5500_ADDR_STARTUP = 0x03,
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AB5500_ADDR_DBI_ECI = 0x07,
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AB5500_ADDR_CHG = 0x0B,
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AB5500_ADDR_FG_BATTCOM_ACC = 0x0C,
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AB5500_ADDR_USB = 0x05,
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AB5500_ADDR_IT = 0x0E,
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AB5500_ADDR_VIBRA = 0x02,
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AB5500_ADDR_AUDIO_HEADSETUSB = 0x0D,
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};
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/*
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* Interrupt register offsets
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* Bank : 0x0E
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*/
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#define AB5500_IT_SOURCE0_REG 0x20
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#define AB5500_IT_SOURCE1_REG 0x21
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#define AB5500_IT_SOURCE2_REG 0x22
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#define AB5500_IT_SOURCE3_REG 0x23
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#define AB5500_IT_SOURCE4_REG 0x24
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#define AB5500_IT_SOURCE5_REG 0x25
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#define AB5500_IT_SOURCE6_REG 0x26
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#define AB5500_IT_SOURCE7_REG 0x27
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#define AB5500_IT_SOURCE8_REG 0x28
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#define AB5500_IT_SOURCE9_REG 0x29
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#define AB5500_IT_SOURCE10_REG 0x2A
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#define AB5500_IT_SOURCE11_REG 0x2B
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#define AB5500_IT_SOURCE12_REG 0x2C
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#define AB5500_IT_SOURCE13_REG 0x2D
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#define AB5500_IT_SOURCE14_REG 0x2E
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#define AB5500_IT_SOURCE15_REG 0x2F
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#define AB5500_IT_SOURCE16_REG 0x30
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#define AB5500_IT_SOURCE17_REG 0x31
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#define AB5500_IT_SOURCE18_REG 0x32
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#define AB5500_IT_SOURCE19_REG 0x33
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#define AB5500_IT_SOURCE20_REG 0x34
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#define AB5500_IT_SOURCE21_REG 0x35
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#define AB5500_IT_SOURCE22_REG 0x36
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#define AB5500_IT_SOURCE23_REG 0x37
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#define AB5500_NUM_IRQ_REGS 23
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/**
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* struct ab5500
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* @access_mutex: lock out concurrent accesses to the AB registers
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* @dev: a pointer to the device struct for this chip driver
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* @ab5500_irq: the analog baseband irq
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* @irq_base: the platform configuration irq base for subdevices
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* @chip_name: name of this chip variant
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* @chip_id: 8 bit chip ID for this chip variant
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* @irq_lock: a lock to protect the mask
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* @abb_events: a local bit mask of the prcmu wakeup events
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* @event_mask: a local copy of the mask event registers
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* @last_event_mask: a copy of the last event_mask written to hardware
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* @startup_events: a copy of the first reading of the event registers
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* @startup_events_read: whether the first events have been read
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*/
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struct ab5500 {
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struct mutex access_mutex;
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struct device *dev;
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unsigned int ab5500_irq;
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unsigned int irq_base;
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char chip_name[32];
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u8 chip_id;
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struct mutex irq_lock;
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u32 abb_events;
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u8 mask[AB5500_NUM_IRQ_REGS];
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u8 oldmask[AB5500_NUM_IRQ_REGS];
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u8 startup_events[AB5500_NUM_IRQ_REGS];
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bool startup_events_read;
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#ifdef CONFIG_DEBUG_FS
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unsigned int debug_bank;
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unsigned int debug_address;
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#endif
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};
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struct ab5500_platform_data {
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struct {unsigned int base; unsigned int count; } irq;
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void *dev_data[AB5500_NUM_DEVICES];
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struct abx500_init_settings *init_settings;
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unsigned int init_settings_sz;
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bool pm_power_off;
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};
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#endif /* MFD_AB5500_H */
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@ -31,8 +31,8 @@
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#define AB3100_R2B 0xc8
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#define AB3550_P1A 0x10
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#define AB5500_1_0 0x20
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#define AB5500_2_0 0x21
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#define AB5500_2_1 0x22
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#define AB5500_1_1 0x21
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#define AB5500_2_0 0x24
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/* AB8500 CIDs*/
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#define AB8500_CUTEARLY 0x00
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