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ARM: dts: imx6q-arm2: move NANDF_CS pins out of 'hog' 

Commit 9e3c0066 (ARM: dts: imx6q-arm2: add pinctrl for uart and enet)
defines NANDF_CS pins as gpio in 'hog', assuming these two pins are
always used by usdhc3 in gpio mode as card-detection and
write-protection on ARM2 board.  But it's not true.  These pins are
shared by usdhc3 and gpmi-nand.  We should have the pins functional
for gpmi-nand when usdhc3 is disabled.

Move the pins out of 'hog', so that pins only work in gpio mode as CD
and WP when usdhc3 is enabled, and otherwise they are available for
gpmi-nand.

Reported-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Shawn Guo 2012-10-15 16:48:04 +08:00 committed by Olof Johansson
parent 5448a279eb
commit 3d76f9f5d3
1 changed files with 9 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm/boot/dts/imx6q-arm2.dts
View File

@ -37,6 +37,13 @@
pinctrl_hog: hoggrp {
fsl,pins = <
176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
>;
};
};
arm2 {
pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
fsl,pins = <
1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
>;
@ -58,7 +65,8 @@
wp-gpios = <&gpio6 14 0>;
vmmc-supply = <&reg_3p3v>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
pinctrl-0 = <&pinctrl_usdhc3_1
&pinctrl_usdhc3_arm2>;
status = "okay";
};