tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state
geni serial needs to express a perforamnce state requirement on CX powerdomain depending on the frequency of the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Akash Asthana <akashast@codeaurora.org> Cc: linux-serial@vger.kernel.org Link: https://lore.kernel.org/r/1588507469-31889-2-git-send-email-rnayak@codeaurora.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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c2880ec6c0
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3d9231e698
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@ -9,6 +9,7 @@
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#include <linux/module.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_device.h>
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#include <linux/pm_opp.h>
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#include <linux/platform_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_runtime.h>
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#include <linux/pm_wakeirq.h>
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#include <linux/pm_wakeirq.h>
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@ -961,7 +962,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
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goto out_restart_rx;
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goto out_restart_rx;
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uport->uartclk = clk_rate;
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uport->uartclk = clk_rate;
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clk_set_rate(port->se.clk, clk_rate);
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dev_pm_opp_set_rate(uport->dev, clk_rate);
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ser_clk_cfg = SER_CLK_EN;
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ser_clk_cfg = SER_CLK_EN;
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ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
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ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
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@ -1198,8 +1199,11 @@ static void qcom_geni_serial_pm(struct uart_port *uport,
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if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
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if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
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geni_se_resources_on(&port->se);
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geni_se_resources_on(&port->se);
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else if (new_state == UART_PM_STATE_OFF &&
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else if (new_state == UART_PM_STATE_OFF &&
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old_state == UART_PM_STATE_ON)
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old_state == UART_PM_STATE_ON) {
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/* Drop the performance state vote */
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dev_pm_opp_set_rate(uport->dev, 0);
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geni_se_resources_off(&port->se);
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geni_se_resources_off(&port->se);
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}
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}
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}
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static const struct uart_ops qcom_geni_console_pops = {
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static const struct uart_ops qcom_geni_console_pops = {
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@ -1318,13 +1322,25 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
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if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
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if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
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port->cts_rts_swap = true;
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port->cts_rts_swap = true;
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port->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se");
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if (IS_ERR(port->se.opp_table))
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return PTR_ERR(port->se.opp_table);
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/* OPP table is optional */
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ret = dev_pm_opp_of_add_table(&pdev->dev);
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if (!ret) {
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port->se.has_opp_table = true;
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} else if (ret != -ENODEV) {
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dev_err(&pdev->dev, "invalid OPP table in device tree\n");
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return ret;
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}
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uport->private_data = drv;
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uport->private_data = drv;
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platform_set_drvdata(pdev, port);
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platform_set_drvdata(pdev, port);
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port->handle_rx = console ? handle_rx_console : handle_rx_uart;
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port->handle_rx = console ? handle_rx_console : handle_rx_uart;
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ret = uart_add_one_port(drv, uport);
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ret = uart_add_one_port(drv, uport);
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if (ret)
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if (ret)
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return ret;
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goto err;
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irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
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irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
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ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
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ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
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@ -1332,7 +1348,7 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
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if (ret) {
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if (ret) {
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dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
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dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
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uart_remove_one_port(drv, uport);
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uart_remove_one_port(drv, uport);
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return ret;
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goto err;
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}
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}
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/*
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/*
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@ -1349,11 +1365,16 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
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if (ret) {
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if (ret) {
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device_init_wakeup(&pdev->dev, false);
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device_init_wakeup(&pdev->dev, false);
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uart_remove_one_port(drv, uport);
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uart_remove_one_port(drv, uport);
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return ret;
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goto err;
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}
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}
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}
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}
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return 0;
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return 0;
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err:
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if (port->se.has_opp_table)
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dev_pm_opp_of_remove_table(&pdev->dev);
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dev_pm_opp_put_clkname(port->se.opp_table);
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return ret;
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}
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}
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static int qcom_geni_serial_remove(struct platform_device *pdev)
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static int qcom_geni_serial_remove(struct platform_device *pdev)
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@ -1361,6 +1382,9 @@ static int qcom_geni_serial_remove(struct platform_device *pdev)
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struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
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struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
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struct uart_driver *drv = port->uport.private_data;
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struct uart_driver *drv = port->uport.private_data;
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if (port->se.has_opp_table)
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dev_pm_opp_of_remove_table(&pdev->dev);
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dev_pm_opp_put_clkname(port->se.opp_table);
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dev_pm_clear_wake_irq(&pdev->dev);
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dev_pm_clear_wake_irq(&pdev->dev);
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device_init_wakeup(&pdev->dev, false);
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device_init_wakeup(&pdev->dev, false);
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uart_remove_one_port(drv, &port->uport);
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uart_remove_one_port(drv, &port->uport);
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@ -33,6 +33,8 @@ struct clk;
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* @clk: Handle to the core serial engine clock
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* @clk: Handle to the core serial engine clock
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* @num_clk_levels: Number of valid clock levels in clk_perf_tbl
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* @num_clk_levels: Number of valid clock levels in clk_perf_tbl
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* @clk_perf_tbl: Table of clock frequency input to serial engine clock
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* @clk_perf_tbl: Table of clock frequency input to serial engine clock
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* @opp_table: Pointer to the OPP table
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* @has_opp_table: Specifies if the SE has an OPP table
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*/
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*/
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struct geni_se {
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struct geni_se {
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void __iomem *base;
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void __iomem *base;
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@ -41,6 +43,8 @@ struct geni_se {
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struct clk *clk;
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struct clk *clk;
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unsigned int num_clk_levels;
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unsigned int num_clk_levels;
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unsigned long *clk_perf_tbl;
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unsigned long *clk_perf_tbl;
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struct opp_table *opp_table;
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bool has_opp_table;
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};
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};
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/* Common SE registers */
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/* Common SE registers */
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