arm64: dts: apq8096-db820c: enable bluetooth node

Add a new serial node for the Qualcomm BT controller QCA6174. This
allows automatic probing and hci registration through the serdev
framework instead of relying on the userspace helpers.

Signed-off-by: Thierry Escande <thierry.escande@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Thierry Escande 2018-03-29 21:15:22 +02:00 committed by Andy Gross
parent 5360394706
commit 3e4cb73080
4 changed files with 76 additions and 0 deletions

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@ -36,4 +36,30 @@
drive-strength = <2>; /* 2 MA */
};
};
blsp1_uart1_default: blsp1_uart1_default {
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "blsp_uart2";
};
config {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
drive-strength = <16>;
bias-disable;
};
};
blsp1_uart1_sleep: blsp1_uart1_sleep {
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "gpio";
};
config {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
drive-strength = <2>;
bias-disable;
};
};
};

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@ -48,6 +48,16 @@
};
};
divclk4_pin_a: divclk4 {
pinconf {
pins = "gpio18";
function = PMIC_GPIO_FUNC_FUNC2;
bias-disable;
power-source = <PM8994_GPIO_S4>;
};
};
usb3_vbus_det_gpio: pm8996_gpio22 {
pinconf {
pins = "gpio22";

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@ -23,6 +23,7 @@
aliases {
serial0 = &blsp2_uart1;
serial1 = &blsp2_uart2;
serial2 = &blsp1_uart1;
i2c0 = &blsp1_i2c2;
i2c1 = &blsp2_i2c1;
i2c2 = &blsp2_i2c0;
@ -34,7 +35,36 @@
stdout-path = "serial0:115200n8";
};
clocks {
divclk4: divclk4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "divclk4";
pinctrl-names = "default";
pinctrl-0 = <&divclk4_pin_a>;
};
};
soc {
serial@7570000 {
label = "BT-UART";
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart1_default>;
pinctrl-1 = <&blsp1_uart1_sleep>;
bluetooth {
compatible = "qcom,qca6174-bt";
/* bt_disable_n gpio */
enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
clocks = <&divclk4>;
};
};
serial@75b0000 {
label = "LS-UART1";
status = "okay";

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@ -419,6 +419,16 @@
#clock-cells = <1>;
};
blsp1_uart1: serial@7570000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x07570000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
blsp1_spi0: spi@7575000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07575000 0x600>;