drm/i915/selftests: Add coverage of mocs registers
Probe the mocs registers for new contexts and across GPU resets. Similar to intel_workarounds, we have tables of what register values we expect to see, so verify that user contexts are affected by them. In the future, we should add tests similar to intel_sseu to cover dynamic reconfigurations. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191112223600.30993-4-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
f8a0c7a996
commit
3fb33cd32f
@ -452,3 +452,7 @@ void intel_mocs_init(struct intel_gt *gt)
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if (HAS_GLOBAL_MOCS_REGISTERS(gt->i915))
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init_global_mocs(gt);
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}
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#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
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#include "selftest_mocs.c"
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#endif
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419
drivers/gpu/drm/i915/gt/selftest_mocs.c
Normal file
419
drivers/gpu/drm/i915/gt/selftest_mocs.c
Normal file
@ -0,0 +1,419 @@
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/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#include "gt/intel_engine_pm.h"
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#include "i915_selftest.h"
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#include "gem/selftests/mock_context.h"
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#include "selftests/igt_reset.h"
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#include "selftests/igt_spinner.h"
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struct live_mocs {
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struct drm_i915_mocs_table table;
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struct i915_vma *scratch;
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void *vaddr;
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};
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static int request_add_sync(struct i915_request *rq, int err)
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{
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i915_request_get(rq);
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i915_request_add(rq);
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if (i915_request_wait(rq, 0, HZ / 5) < 0)
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err = -ETIME;
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i915_request_put(rq);
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return err;
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}
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static int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
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{
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int err = 0;
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i915_request_get(rq);
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i915_request_add(rq);
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if (spin && !igt_wait_for_spinner(spin, rq))
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err = -ETIME;
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i915_request_put(rq);
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return err;
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}
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static struct i915_vma *create_scratch(struct intel_gt *gt)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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int err;
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obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE);
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if (IS_ERR(obj))
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return ERR_CAST(obj);
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i915_gem_object_set_cache_coherency(obj, I915_CACHING_CACHED);
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vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
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if (IS_ERR(vma)) {
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i915_gem_object_put(obj);
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return vma;
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}
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err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
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if (err) {
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i915_gem_object_put(obj);
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return ERR_PTR(err);
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}
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return vma;
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}
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static int live_mocs_init(struct live_mocs *arg, struct intel_gt *gt)
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{
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int err;
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if (!get_mocs_settings(gt->i915, &arg->table))
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return -EINVAL;
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arg->scratch = create_scratch(gt);
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if (IS_ERR(arg->scratch))
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return PTR_ERR(arg->scratch);
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arg->vaddr = i915_gem_object_pin_map(arg->scratch->obj, I915_MAP_WB);
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if (IS_ERR(arg->vaddr)) {
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err = PTR_ERR(arg->vaddr);
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goto err_scratch;
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}
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return 0;
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err_scratch:
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i915_vma_unpin_and_release(&arg->scratch, 0);
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return err;
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}
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static void live_mocs_fini(struct live_mocs *arg)
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{
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i915_vma_unpin_and_release(&arg->scratch, I915_VMA_RELEASE_MAP);
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}
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static int read_regs(struct i915_request *rq,
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u32 addr, unsigned int count,
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uint32_t *offset)
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{
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unsigned int i;
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u32 *cs;
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GEM_BUG_ON(!IS_ALIGNED(*offset, sizeof(u32)));
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cs = intel_ring_begin(rq, 4 * count);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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for (i = 0; i < count; i++) {
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*cs++ = MI_STORE_REGISTER_MEM_GEN8 | MI_USE_GGTT;
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*cs++ = addr;
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*cs++ = *offset;
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*cs++ = 0;
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addr += sizeof(u32);
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*offset += sizeof(u32);
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}
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intel_ring_advance(rq, cs);
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return 0;
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}
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static int read_mocs_table(struct i915_request *rq,
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const struct drm_i915_mocs_table *table,
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uint32_t *offset)
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{
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u32 addr;
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if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
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addr = global_mocs_offset();
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else
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addr = mocs_offset(rq->engine);
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return read_regs(rq, addr, table->n_entries, offset);
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}
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static int read_l3cc_table(struct i915_request *rq,
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const struct drm_i915_mocs_table *table,
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uint32_t *offset)
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{
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u32 addr = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
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return read_regs(rq, addr, (table->n_entries + 1) / 2, offset);
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}
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static int check_mocs_table(struct intel_engine_cs *engine,
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const struct drm_i915_mocs_table *table,
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uint32_t **vaddr)
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{
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unsigned int i;
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u32 expect;
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for_each_mocs(expect, table, i) {
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if (**vaddr != expect) {
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pr_err("%s: Invalid MOCS[%d] entry, found %08x, expected %08x\n",
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engine->name, i, **vaddr, expect);
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return -EINVAL;
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}
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++*vaddr;
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}
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return 0;
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}
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static bool mcr_range(struct drm_i915_private *i915, u32 offset)
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{
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/*
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* Registers in this range are affected by the MCR selector
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* which only controls CPU initiated MMIO. Routing does not
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* work for CS access so we cannot verify them on this path.
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*/
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return INTEL_GEN(i915) >= 8 && offset >= 0xb000 && offset <= 0xb4ff;
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}
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static int check_l3cc_table(struct intel_engine_cs *engine,
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const struct drm_i915_mocs_table *table,
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uint32_t **vaddr)
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{
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/* Can we read the MCR range 0xb00 directly? See intel_workarounds! */
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u32 reg = i915_mmio_reg_offset(GEN9_LNCFCMOCS(0));
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unsigned int i;
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u32 expect;
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for_each_l3cc(expect, table, i) {
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if (!mcr_range(engine->i915, reg) && **vaddr != expect) {
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pr_err("%s: Invalid L3CC[%d] entry, found %08x, expected %08x\n",
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engine->name, i, **vaddr, expect);
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return -EINVAL;
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}
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++*vaddr;
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reg += 4;
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}
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return 0;
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}
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static int check_mocs_engine(struct live_mocs *arg,
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struct intel_context *ce)
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{
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struct i915_vma *vma = arg->scratch;
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struct i915_request *rq;
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u32 offset;
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u32 *vaddr;
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int err;
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memset32(arg->vaddr, STACK_MAGIC, PAGE_SIZE / sizeof(u32));
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rq = intel_context_create_request(ce);
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if (IS_ERR(rq))
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return PTR_ERR(rq);
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i915_vma_lock(vma);
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err = i915_request_await_object(rq, vma->obj, true);
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if (!err)
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err = i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
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i915_vma_unlock(vma);
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/* Read the mocs tables back using SRM */
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offset = i915_ggtt_offset(vma);
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if (!err)
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err = read_mocs_table(rq, &arg->table, &offset);
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if (!err && ce->engine->class == RENDER_CLASS)
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err = read_l3cc_table(rq, &arg->table, &offset);
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offset -= i915_ggtt_offset(vma);
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GEM_BUG_ON(offset > PAGE_SIZE);
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err = request_add_sync(rq, err);
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if (err)
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return err;
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/* Compare the results against the expected tables */
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vaddr = arg->vaddr;
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if (!err)
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err = check_mocs_table(ce->engine, &arg->table, &vaddr);
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if (!err && ce->engine->class == RENDER_CLASS)
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err = check_l3cc_table(ce->engine, &arg->table, &vaddr);
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if (err)
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return err;
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GEM_BUG_ON(arg->vaddr + offset != vaddr);
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return 0;
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}
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static int live_mocs_kernel(void *arg)
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{
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struct intel_gt *gt = arg;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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struct live_mocs mocs;
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int err;
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/* Basic check the system is configured with the expected mocs table */
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err = live_mocs_init(&mocs, gt);
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if (err)
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return err;
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for_each_engine(engine, gt, id) {
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err = check_mocs_engine(&mocs, engine->kernel_context);
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if (err)
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break;
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}
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live_mocs_fini(&mocs);
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return err;
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}
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static int live_mocs_clean(void *arg)
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{
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struct intel_gt *gt = arg;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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struct live_mocs mocs;
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int err;
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/* Every new context should see the same mocs table */
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err = live_mocs_init(&mocs, gt);
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if (err)
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return err;
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for_each_engine(engine, gt, id) {
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struct intel_context *ce;
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ce = intel_context_create(engine->kernel_context->gem_context,
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engine);
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if (IS_ERR(ce)) {
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err = PTR_ERR(ce);
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break;
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}
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err = check_mocs_engine(&mocs, ce);
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intel_context_put(ce);
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if (err)
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break;
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}
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live_mocs_fini(&mocs);
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return err;
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}
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static int active_engine_reset(struct intel_context *ce,
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const char *reason)
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{
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struct igt_spinner spin;
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struct i915_request *rq;
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int err;
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err = igt_spinner_init(&spin, ce->engine->gt);
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if (err)
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return err;
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rq = igt_spinner_create_request(&spin, ce, MI_NOOP);
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if (IS_ERR(rq)) {
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igt_spinner_fini(&spin);
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return PTR_ERR(rq);
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}
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err = request_add_spin(rq, &spin);
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if (err == 0)
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err = intel_engine_reset(ce->engine, reason);
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igt_spinner_end(&spin);
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igt_spinner_fini(&spin);
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return err;
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}
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static int __live_mocs_reset(struct live_mocs *mocs,
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struct intel_context *ce)
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{
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int err;
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err = intel_engine_reset(ce->engine, "mocs");
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if (err)
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return err;
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err = check_mocs_engine(mocs, ce);
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if (err)
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return err;
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err = active_engine_reset(ce, "mocs");
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if (err)
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return err;
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err = check_mocs_engine(mocs, ce);
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if (err)
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return err;
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intel_gt_reset(ce->engine->gt, ce->engine->mask, "mocs");
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err = check_mocs_engine(mocs, ce);
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if (err)
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return err;
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return 0;
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}
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static int live_mocs_reset(void *arg)
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{
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struct intel_gt *gt = arg;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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struct live_mocs mocs;
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int err = 0;
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/* Check the mocs setup is retained over per-engine and global resets */
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if (!intel_has_reset_engine(gt))
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return 0;
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err = live_mocs_init(&mocs, gt);
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if (err)
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return err;
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igt_global_reset_lock(gt);
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for_each_engine(engine, gt, id) {
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struct intel_context *ce;
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ce = intel_context_create(engine->kernel_context->gem_context,
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engine);
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if (IS_ERR(ce)) {
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err = PTR_ERR(ce);
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break;
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}
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intel_engine_pm_get(engine);
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err = __live_mocs_reset(&mocs, ce);
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intel_engine_pm_put(engine);
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intel_context_put(ce);
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if (err)
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break;
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}
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igt_global_reset_unlock(gt);
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live_mocs_fini(&mocs);
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return err;
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}
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int intel_mocs_live_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(live_mocs_kernel),
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SUBTEST(live_mocs_clean),
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SUBTEST(live_mocs_reset),
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};
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struct drm_i915_mocs_table table;
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if (!get_mocs_settings(i915, &table))
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return 0;
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return intel_gt_live_subtests(tests, &i915->gt);
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}
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@ -16,6 +16,7 @@ selftest(gt_engines, intel_engine_live_selftests)
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selftest(gt_timelines, intel_timeline_live_selftests)
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selftest(gt_contexts, intel_context_live_selftests)
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selftest(gt_lrc, intel_lrc_live_selftests)
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selftest(gt_mocs, intel_mocs_live_selftests)
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selftest(gt_pm, intel_gt_pm_live_selftests)
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selftest(gt_heartbeat, intel_heartbeat_live_selftests)
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selftest(requests, i915_request_live_selftests)
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