ARM: SoC fixes for 3.15-rc3:
Since we didn't get around to collect fixes in time for -rc2 over the easter vacation, this one is unfortunately a bit larger than we'd like for an -rc3 merge. A large set of the changes is in the device tree sources, so I'm splitting out the description between code changes and DT changes. Aside from omap and versatile express, the actual code bugs are sporadic and trivial. Here is an overview: imx: - fix video clock settings - fix one clock refcounting bug omap: - update defconfig for renamed USB PHY driver - fix error handling in gpmc - fix N900 video initialization regression - fix reression in hwmod code from missing braces - fix am43xx and omap3 clocks - remove bogus write to voltage control register pxa: - fix build regression from 3.13 header cleanup rockchip: - fix a misleading printk string shmobile: - fix incorrect sound setting on multiple machines spear: - remove incorrect __init section annotation tegra: - remove a stale Kconfig entry u300: - update defconfig ux500: - enable common wireless and sensor drivers in defconfig - more defconfig updates vexpress: - fix voltage calculation for opp - fix reboot hang and warning - fix out-of-bounds array access - improve error handling in clock driver overall: - always select CLKSRC_OF in multiplatform builds And these are the devicetree related changes: imx: - add missing #clock-cell properties - fix pinctrl setting in imx6sl-evk - fix video endpoint on imx53 - remove obsolete lvds-channel nodes (multiple patches) - add missing second stmpe node - fix usb host mode on dmo-edmqmx6 (multiple patches) - fix gic node #address-cells to match usage - add missing legacy IRQ map for PCIe - fix microsom pincontrol setting for rgmii - fix fatal typo in touchscreen DT usage for mx5 - list all RAM present on m53evk and mx53qsb omap: - fix bug in DT handling of gpmc external bus - add DT for older revision of beagleboard - fix regression after DT node name fixes - remove obsolete properties for gpmc - fix pinmux comment to match DT it refers to - fix newly added dra7xx clock node data - add missing clock for USB PHY mvebu: - add missing clock for mdio node - fix nonstandard vendor prefixes on i2c nodes rockchip: - fix pin control setting for uart shmobile: - fix typo in DT data for pin control (multiple patches) - fix gic node #address-cells to match usage tegra: - fix clock and uart DT representation to match hardware zynq: - add DT nodes for newly added driver - add DT properties required for cpufreq-ondemand overall: - restore alphabetic order in Makefile - grammar fixes in bindings -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAU1pK92CrR//JCVInAQLerA/9GwLHJIBU6osKnZtIWDYPhYj81uRxgF5Q qtaUdsSoDQmIiW8tzJL0VUBJQfSpPtf4hsIPh5dMKclalx+0kca3zpPepo58rvEP zG39OIK/fBsmD/eVkz0y3lG5BUu9/1gkpnM8jSEmkDWqcNX8wQoOeHSrWXWzEk1G 2eZlXsYr9OVuIGRx14wnINvPuD2Z75zEXA7KDbDuYqauQvVojj5wH6s8R7Ujy7e1 +NGCThkLJUF2wid+6QmVk9D6tQXyVxmf+cr080n58LmOmoVnoFkCjs5gaUUIP8Zb nM97PQly0s1JIRn+9jF7+U0KNyp9eec7Ogc00tpvvBmQI2kVfHfSRROLq+tDGu1t nEEy52X/QVgWWY+1qUl+gqIWWmMTpniDF1pd/5jP3jKXUc/sM7OfLGQaTP4O7sR6 5MlfvqvSO/EaMeWEvX4e8+Z+2dY1qFZUYk7VtamqmOegzkcDjAiJ3aQNozuqq9JH TTHbA2Em9VGC1LlAMAg7h46rM//npCeJ0Q5yjuFk093UBEbAF4HWO2PFNrdohKzC Yz/R+vkvGeQ98K/4jj4UIyjcB4PUX+DRrozC10i2XCQh+UIYdgC4dFQz1nH/4iQS CrdSRmDvpZDjSFV5m4+QVkaEsTJnXX6vV62VBVRcSLkqyfPABWj1y9c2L3K8kfBJ 6nbficflFqE= =PPo/ -----END PGP SIGNATURE----- Merge tag 'fixes-3.15-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Arnd Bergmann: "Since we didn't get around to collect fixes in time for -rc2 over the easter vacation, this one is unfortunately a bit larger than we'd like for an -rc3 merge. A large set of the changes is in the device tree sources, so I'm splitting out the description between code changes and DT changes. Aside from omap and versatile express, the actual code bugs are and trivial. Here is an overview: imx: - fix video clock settings - fix one clock refcounting bug omap: - update defconfig for renamed USB PHY driver - fix error handling in gpmc - fix N900 video initialization regression - fix reression in hwmod code from missing braces - fix am43xx and omap3 clocks - remove bogus write to voltage control register pxa: - fix build regression from 3.13 header cleanup rockchip: - fix a misleading printk string shmobile: - fix incorrect sound setting on multiple machines spear: - remove incorrect __init section annotation tegra: - remove a stale Kconfig entry u300: - update defconfig ux500: - enable common wireless and sensor drivers in defconfig - more defconfig updates vexpress: - fix voltage calculation for opp - fix reboot hang and warning - fix out-of-bounds array access - improve error handling in clock driver overall: - always select CLKSRC_OF in multiplatform builds And these are the devicetree related changes: imx: - add missing #clock-cell properties - fix pinctrl setting in imx6sl-evk - fix video endpoint on imx53 - remove obsolete lvds-channel nodes (multiple patches) - add missing second stmpe node - fix usb host mode on dmo-edmqmx6 (multiple patches) - fix gic node #address-cells to match usage - add missing legacy IRQ map for PCIe - fix microsom pincontrol setting for rgmii - fix fatal typo in touchscreen DT usage for mx5 - list all RAM present on m53evk and mx53qsb omap: - fix bug in DT handling of gpmc external bus - add DT for older revision of beagleboard - fix regression after DT node name fixes - remove obsolete properties for gpmc - fix pinmux comment to match DT it refers to - fix newly added dra7xx clock node data - add missing clock for USB PHY mvebu: - add missing clock for mdio node - fix nonstandard vendor prefixes on i2c nodes rockchip: - fix pin control setting for uart shmobile: - fix typo in DT data for pin control (multiple patches) - fix gic node #address-cells to match usage tegra: - fix clock and uart DT representation to match hardware zynq: - add DT nodes for newly added driver - add DT properties required for cpufreq-ondemand overall: - restore alphabetic order in Makefile - grammar fixes in bindings" * tag 'fixes-3.15-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (66 commits) ARM: vexpress/TC2: Convert OPP voltage to uV before storing power/reset: vexpress: Fix restart/power off operation dt: tegra: remove non-existent clock IDs clk: tegra: remove non-existent clocks ARM: tegra: remove UART5/UARTE from tegra124.dtsi ARM: tegra: remove TEGRA_EMC_SCALING_ENABLE ARM: Tidy up DTB Makefile entries ARM: fix missing CLKSRC_OF on multi-platform ARM: spear: add __init to spear_clocksource_init() ARM: pxa: hx4700.h: include "irqs.h" for PXA_NR_BUILTIN_GPIO arm/mach-vexpress: array accessed out of bounds clk: vexpress: NULL dereference on error path ARM: OMAP2+: Fix GPMC remap for devices using an offset ARM: zynq: dt: Add I2C nodes to Zynq device tree ARM: zynq: DT: Add 'clock-latency' property ARM: OMAP2+: Fix oops for GPMC free ARM: dts: Add support for the BeagleBoard xM A/B ARM: dts: Grammar /that will/it will/ ARM: dts: Grammar /is uses/ is used/ ARM: OMAP2+: Fix config name for USB3 PHY ...
This commit is contained in:
commit
3fe89d2e76
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@ -311,6 +311,7 @@ config ARCH_MULTIPLATFORM
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select ARM_HAS_SG_CHAIN
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select ARM_HAS_SG_CHAIN
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select ARM_PATCH_PHYS_VIRT
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select ARM_PATCH_PHYS_VIRT
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select AUTO_ZRELADDR
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select AUTO_ZRELADDR
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select CLKSRC_OF
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select COMMON_CLK
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select COMMON_CLK
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select GENERIC_CLOCKEVENTS
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select GENERIC_CLOCKEVENTS
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select MULTI_IRQ_HANDLER
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select MULTI_IRQ_HANDLER
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@ -51,10 +51,9 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
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dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
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dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
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dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
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dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
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dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
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dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
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dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
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bcm21664-garnet.dtb
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bcm21664-garnet.dtb
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dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
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dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
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dtb-$(CONFIG_ARCH_BERLIN) += \
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dtb-$(CONFIG_ARCH_BERLIN) += \
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berlin2-sony-nsz-gs7.dtb \
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berlin2-sony-nsz-gs7.dtb \
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berlin2cd-google-chromecast.dtb
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berlin2cd-google-chromecast.dtb
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@ -246,6 +245,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
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omap3-sbc-t3730.dtb \
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omap3-sbc-t3730.dtb \
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omap3-devkit8000.dtb \
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omap3-devkit8000.dtb \
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omap3-beagle-xm.dtb \
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omap3-beagle-xm.dtb \
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omap3-beagle-xm-ab.dtb \
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omap3-evm.dtb \
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omap3-evm.dtb \
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omap3-evm-37xx.dtb \
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omap3-evm-37xx.dtb \
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omap3-ldp.dtb \
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omap3-ldp.dtb \
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@ -294,13 +294,6 @@ dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
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dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
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qcom-msm8960-cdp.dtb \
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qcom-msm8960-cdp.dtb \
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qcom-apq8074-dragonboard.dtb
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qcom-apq8074-dragonboard.dtb
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dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
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ste-hrefprev60-stuib.dtb \
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ste-hrefprev60-tvk.dtb \
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ste-hrefv60plus-stuib.dtb \
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ste-hrefv60plus-tvk.dtb \
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ste-ccu8540.dtb \
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ste-ccu9540.dtb
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dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
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dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
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dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
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dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
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s3c6410-smdk6410.dtb
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s3c6410-smdk6410.dtb
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@ -369,9 +362,16 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
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tegra30-cardhu-a04.dtb \
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tegra30-cardhu-a04.dtb \
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tegra114-dalmore.dtb \
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tegra114-dalmore.dtb \
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tegra124-venice2.dtb
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tegra124-venice2.dtb
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dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
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dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
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|
ste-hrefprev60-stuib.dtb \
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ste-hrefprev60-tvk.dtb \
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|
ste-hrefv60plus-stuib.dtb \
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ste-hrefv60plus-tvk.dtb \
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|
ste-ccu8540.dtb \
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||||||
|
ste-ccu9540.dtb
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dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
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dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
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versatile-pb.dtb
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versatile-pb.dtb
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dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
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dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
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dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
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||||||
vexpress-v2p-ca9.dtb \
|
vexpress-v2p-ca9.dtb \
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||||||
vexpress-v2p-ca15-tc1.dtb \
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vexpress-v2p-ca15-tc1.dtb \
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||||||
|
|
|
@ -183,7 +183,7 @@
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&usb {
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&usb {
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||||||
status = "okay";
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status = "okay";
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||||||
|
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||||||
control@44e10000 {
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control@44e10620 {
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status = "okay";
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status = "okay";
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||||||
};
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};
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||||||
|
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||||||
|
@ -204,7 +204,7 @@
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dr_mode = "host";
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dr_mode = "host";
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};
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};
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||||||
|
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||||||
dma-controller@07402000 {
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dma-controller@47402000 {
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status = "okay";
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status = "okay";
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||||||
};
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};
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||||||
};
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};
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|
|
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@ -301,8 +301,8 @@
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||||||
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||||||
am335x_evm_audio_pins: am335x_evm_audio_pins {
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am335x_evm_audio_pins: am335x_evm_audio_pins {
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pinctrl-single,pins = <
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pinctrl-single,pins = <
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||||||
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rx_dv.mcasp1_aclkx */
|
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
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||||||
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_txd3.mcasp1_fsx */
|
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
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||||||
0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
|
0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
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||||||
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
|
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
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>;
|
>;
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||||||
|
@ -331,7 +331,7 @@
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||||||
&usb {
|
&usb {
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||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
control@44e10000 {
|
control@44e10620 {
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||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -352,7 +352,7 @@
|
||||||
dr_mode = "host";
|
dr_mode = "host";
|
||||||
};
|
};
|
||||||
|
|
||||||
dma-controller@07402000 {
|
dma-controller@47402000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -364,7 +364,7 @@
|
||||||
&usb {
|
&usb {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
control@44e10000 {
|
control@44e10620 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -385,7 +385,7 @@
|
||||||
dr_mode = "host";
|
dr_mode = "host";
|
||||||
};
|
};
|
||||||
|
|
||||||
dma-controller@07402000 {
|
dma-controller@47402000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -118,7 +118,6 @@
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||||||
reg = <0 0 0>; /* CS0, offset 0 */
|
reg = <0 0 0>; /* CS0, offset 0 */
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nand-bus-width = <8>;
|
nand-bus-width = <8>;
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||||||
ti,nand-ecc-opt = "bch8";
|
ti,nand-ecc-opt = "bch8";
|
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gpmc,device-nand = "true";
|
|
||||||
gpmc,device-width = <1>;
|
gpmc,device-width = <1>;
|
||||||
gpmc,sync-clk-ps = <0>;
|
gpmc,sync-clk-ps = <0>;
|
||||||
gpmc,cs-on-ns = <0>;
|
gpmc,cs-on-ns = <0>;
|
||||||
|
@ -202,7 +201,7 @@
|
||||||
&usb {
|
&usb {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
control@44e10000 {
|
control@44e10620 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -223,7 +222,7 @@
|
||||||
dr_mode = "host";
|
dr_mode = "host";
|
||||||
};
|
};
|
||||||
|
|
||||||
dma-controller@07402000 {
|
dma-controller@47402000 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -72,7 +72,7 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The soc node represents the soc top level view. It is uses for IPs
|
* The soc node represents the soc top level view. It is used for IPs
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||||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||||
*/
|
*/
|
||||||
soc {
|
soc {
|
||||||
|
@ -94,8 +94,8 @@
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* XXX: Use a flat representation of the AM33XX interconnect.
|
* XXX: Use a flat representation of the AM33XX interconnect.
|
||||||
* The real AM33XX interconnect network is quite complex.Since
|
* The real AM33XX interconnect network is quite complex. Since
|
||||||
* that will not bring real advantage to represent that in DT
|
* it will not bring real advantage to represent that in DT
|
||||||
* for the moment, just use a fake OCP bus entry to represent
|
* for the moment, just use a fake OCP bus entry to represent
|
||||||
* the whole bus hierarchy.
|
* the whole bus hierarchy.
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -230,6 +230,7 @@
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
compatible = "marvell,orion-mdio";
|
compatible = "marvell,orion-mdio";
|
||||||
reg = <0x72004 0x4>;
|
reg = <0x72004 0x4>;
|
||||||
|
clocks = <&gateclk 4>;
|
||||||
};
|
};
|
||||||
|
|
||||||
eth1: ethernet@74000 {
|
eth1: ethernet@74000 {
|
||||||
|
|
|
@ -336,6 +336,7 @@
|
||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
compatible = "marvell,orion-mdio";
|
compatible = "marvell,orion-mdio";
|
||||||
reg = <0x72004 0x4>;
|
reg = <0x72004 0x4>;
|
||||||
|
clocks = <&gateclk 4>;
|
||||||
};
|
};
|
||||||
|
|
||||||
coredivclk: clock@e4250 {
|
coredivclk: clock@e4250 {
|
||||||
|
|
|
@ -80,7 +80,7 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The soc node represents the soc top level view. It is uses for IPs
|
* The soc node represents the soc top level view. It is used for IPs
|
||||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||||
*/
|
*/
|
||||||
soc {
|
soc {
|
||||||
|
@ -94,7 +94,7 @@
|
||||||
/*
|
/*
|
||||||
* XXX: Use a flat representation of the SOC interconnect.
|
* XXX: Use a flat representation of the SOC interconnect.
|
||||||
* The real OMAP interconnect network is quite complex.
|
* The real OMAP interconnect network is quite complex.
|
||||||
* Since that will not bring real advantage to represent that in DT for
|
* Since it will not bring real advantage to represent that in DT for
|
||||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||||
* hierarchy.
|
* hierarchy.
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -1640,7 +1640,7 @@
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
compatible = "ti,mux-clock";
|
compatible = "ti,mux-clock";
|
||||||
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
|
clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
|
||||||
ti,bit-shift = <28>;
|
ti,bit-shift = <24>;
|
||||||
reg = <0x1860>;
|
reg = <0x1860>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -56,6 +56,7 @@
|
||||||
|
|
||||||
osc {
|
osc {
|
||||||
compatible = "fsl,imx-osc", "fixed-clock";
|
compatible = "fsl,imx-osc", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <24000000>;
|
clock-frequency = <24000000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -29,6 +29,7 @@
|
||||||
|
|
||||||
osc26m {
|
osc26m {
|
||||||
compatible = "fsl,imx-osc26m", "fixed-clock";
|
compatible = "fsl,imx-osc26m", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <0>;
|
clock-frequency = <0>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -48,6 +48,7 @@
|
||||||
|
|
||||||
osc26m {
|
osc26m {
|
||||||
compatible = "fsl,imx-osc26m", "fixed-clock";
|
compatible = "fsl,imx-osc26m", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <26000000>;
|
clock-frequency = <26000000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -53,21 +53,25 @@
|
||||||
|
|
||||||
ckil {
|
ckil {
|
||||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <32768>;
|
clock-frequency = <32768>;
|
||||||
};
|
};
|
||||||
|
|
||||||
ckih1 {
|
ckih1 {
|
||||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <22579200>;
|
clock-frequency = <22579200>;
|
||||||
};
|
};
|
||||||
|
|
||||||
ckih2 {
|
ckih2 {
|
||||||
compatible = "fsl,imx-ckih2", "fixed-clock";
|
compatible = "fsl,imx-ckih2", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <0>;
|
clock-frequency = <0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
osc {
|
osc {
|
||||||
compatible = "fsl,imx-osc", "fixed-clock";
|
compatible = "fsl,imx-osc", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <24000000>;
|
clock-frequency = <24000000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -50,21 +50,25 @@
|
||||||
|
|
||||||
ckil {
|
ckil {
|
||||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <32768>;
|
clock-frequency = <32768>;
|
||||||
};
|
};
|
||||||
|
|
||||||
ckih1 {
|
ckih1 {
|
||||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <0>;
|
clock-frequency = <0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
ckih2 {
|
ckih2 {
|
||||||
compatible = "fsl,imx-ckih2", "fixed-clock";
|
compatible = "fsl,imx-ckih2", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <0>;
|
clock-frequency = <0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
osc {
|
osc {
|
||||||
compatible = "fsl,imx-osc", "fixed-clock";
|
compatible = "fsl,imx-osc", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <24000000>;
|
clock-frequency = <24000000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -17,7 +17,8 @@
|
||||||
compatible = "denx,imx53-m53evk", "fsl,imx53";
|
compatible = "denx,imx53-m53evk", "fsl,imx53";
|
||||||
|
|
||||||
memory {
|
memory {
|
||||||
reg = <0x70000000 0x20000000>;
|
reg = <0x70000000 0x20000000>,
|
||||||
|
<0xb0000000 0x20000000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
soc {
|
soc {
|
||||||
|
@ -193,17 +194,17 @@
|
||||||
irq-trigger = <0x1>;
|
irq-trigger = <0x1>;
|
||||||
|
|
||||||
stmpe_touchscreen {
|
stmpe_touchscreen {
|
||||||
compatible = "stmpe,ts";
|
compatible = "st,stmpe-ts";
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
ts,sample-time = <4>;
|
st,sample-time = <4>;
|
||||||
ts,mod-12b = <1>;
|
st,mod-12b = <1>;
|
||||||
ts,ref-sel = <0>;
|
st,ref-sel = <0>;
|
||||||
ts,adc-freq = <1>;
|
st,adc-freq = <1>;
|
||||||
ts,ave-ctrl = <3>;
|
st,ave-ctrl = <3>;
|
||||||
ts,touch-det-delay = <3>;
|
st,touch-det-delay = <3>;
|
||||||
ts,settling = <4>;
|
st,settling = <4>;
|
||||||
ts,fraction-z = <7>;
|
st,fraction-z = <7>;
|
||||||
ts,i-drive = <1>;
|
st,i-drive = <1>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -14,7 +14,8 @@
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
memory {
|
memory {
|
||||||
reg = <0x70000000 0x40000000>;
|
reg = <0x70000000 0x20000000>,
|
||||||
|
<0xb0000000 0x20000000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
display0: display@di0 {
|
display0: display@di0 {
|
||||||
|
|
|
@ -25,12 +25,17 @@
|
||||||
soc {
|
soc {
|
||||||
display: display@di0 {
|
display: display@di0 {
|
||||||
compatible = "fsl,imx-parallel-display";
|
compatible = "fsl,imx-parallel-display";
|
||||||
crtcs = <&ipu 0>;
|
|
||||||
interface-pix-fmt = "rgb24";
|
interface-pix-fmt = "rgb24";
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&pinctrl_rgb24_vga1>;
|
pinctrl-0 = <&pinctrl_rgb24_vga1>;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
|
port {
|
||||||
|
display0_in: endpoint {
|
||||||
|
remote-endpoint = <&ipu_di0_disp0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
display-timings {
|
display-timings {
|
||||||
VGA {
|
VGA {
|
||||||
clock-frequency = <25200000>;
|
clock-frequency = <25200000>;
|
||||||
|
@ -293,6 +298,10 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&ipu_di0_disp0 {
|
||||||
|
remote-endpoint = <&display0_in>;
|
||||||
|
};
|
||||||
|
|
||||||
&kpp {
|
&kpp {
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&pinctrl_kpp>;
|
pinctrl-0 = <&pinctrl_kpp>;
|
||||||
|
|
|
@ -70,21 +70,25 @@
|
||||||
|
|
||||||
ckil {
|
ckil {
|
||||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <32768>;
|
clock-frequency = <32768>;
|
||||||
};
|
};
|
||||||
|
|
||||||
ckih1 {
|
ckih1 {
|
||||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <22579200>;
|
clock-frequency = <22579200>;
|
||||||
};
|
};
|
||||||
|
|
||||||
ckih2 {
|
ckih2 {
|
||||||
compatible = "fsl,imx-ckih2", "fixed-clock";
|
compatible = "fsl,imx-ckih2", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <0>;
|
clock-frequency = <0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
osc {
|
osc {
|
||||||
compatible = "fsl,imx-osc", "fixed-clock";
|
compatible = "fsl,imx-osc", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <24000000>;
|
clock-frequency = <24000000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
@ -430,7 +434,7 @@
|
||||||
|
|
||||||
port {
|
port {
|
||||||
lvds1_in: endpoint {
|
lvds1_in: endpoint {
|
||||||
remote-endpoint = <&ipu_di0_lvds0>;
|
remote-endpoint = <&ipu_di1_lvds1>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -19,7 +19,10 @@
|
||||||
compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
|
compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
|
||||||
|
|
||||||
aliases {
|
aliases {
|
||||||
gpio7 = &stmpe_gpio;
|
gpio7 = &stmpe_gpio1;
|
||||||
|
gpio8 = &stmpe_gpio2;
|
||||||
|
stmpe-i2c0 = &stmpe1;
|
||||||
|
stmpe-i2c1 = &stmpe2;
|
||||||
};
|
};
|
||||||
|
|
||||||
memory {
|
memory {
|
||||||
|
@ -40,13 +43,15 @@
|
||||||
regulator-always-on;
|
regulator-always-on;
|
||||||
};
|
};
|
||||||
|
|
||||||
reg_usb_otg_vbus: regulator@1 {
|
reg_usb_otg_switch: regulator@1 {
|
||||||
compatible = "regulator-fixed";
|
compatible = "regulator-fixed";
|
||||||
reg = <1>;
|
reg = <1>;
|
||||||
regulator-name = "usb_otg_vbus";
|
regulator-name = "usb_otg_switch";
|
||||||
regulator-min-microvolt = <5000000>;
|
regulator-min-microvolt = <5000000>;
|
||||||
regulator-max-microvolt = <5000000>;
|
regulator-max-microvolt = <5000000>;
|
||||||
gpio = <&gpio7 12 0>;
|
gpio = <&gpio7 12 0>;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-always-on;
|
||||||
};
|
};
|
||||||
|
|
||||||
reg_usb_host1: regulator@2 {
|
reg_usb_host1: regulator@2 {
|
||||||
|
@ -65,23 +70,23 @@
|
||||||
|
|
||||||
led-blue {
|
led-blue {
|
||||||
label = "blue";
|
label = "blue";
|
||||||
gpios = <&stmpe_gpio 8 GPIO_ACTIVE_HIGH>;
|
gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>;
|
||||||
linux,default-trigger = "heartbeat";
|
linux,default-trigger = "heartbeat";
|
||||||
};
|
};
|
||||||
|
|
||||||
led-green {
|
led-green {
|
||||||
label = "green";
|
label = "green";
|
||||||
gpios = <&stmpe_gpio 9 GPIO_ACTIVE_HIGH>;
|
gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>;
|
||||||
};
|
};
|
||||||
|
|
||||||
led-pink {
|
led-pink {
|
||||||
label = "pink";
|
label = "pink";
|
||||||
gpios = <&stmpe_gpio 10 GPIO_ACTIVE_HIGH>;
|
gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>;
|
||||||
};
|
};
|
||||||
|
|
||||||
led-red {
|
led-red {
|
||||||
label = "red";
|
label = "red";
|
||||||
gpios = <&stmpe_gpio 11 GPIO_ACTIVE_HIGH>;
|
gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
@ -99,7 +104,8 @@
|
||||||
clock-frequency = <100000>;
|
clock-frequency = <100000>;
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&pinctrl_i2c2
|
pinctrl-0 = <&pinctrl_i2c2
|
||||||
&pinctrl_stmpe>;
|
&pinctrl_stmpe1
|
||||||
|
&pinctrl_stmpe2>;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
pmic: pfuze100@08 {
|
pmic: pfuze100@08 {
|
||||||
|
@ -205,13 +211,25 @@
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
stmpe: stmpe1601@40 {
|
stmpe1: stmpe1601@40 {
|
||||||
compatible = "st,stmpe1601";
|
compatible = "st,stmpe1601";
|
||||||
reg = <0x40>;
|
reg = <0x40>;
|
||||||
interrupts = <30 0>;
|
interrupts = <30 0>;
|
||||||
interrupt-parent = <&gpio3>;
|
interrupt-parent = <&gpio3>;
|
||||||
|
|
||||||
stmpe_gpio: stmpe_gpio {
|
stmpe_gpio1: stmpe_gpio {
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
compatible = "st,stmpe-gpio";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
stmpe2: stmpe1601@44 {
|
||||||
|
compatible = "st,stmpe1601";
|
||||||
|
reg = <0x44>;
|
||||||
|
interrupts = <2 0>;
|
||||||
|
interrupt-parent = <&gpio5>;
|
||||||
|
|
||||||
|
stmpe_gpio2: stmpe_gpio {
|
||||||
#gpio-cells = <2>;
|
#gpio-cells = <2>;
|
||||||
compatible = "st,stmpe-gpio";
|
compatible = "st,stmpe-gpio";
|
||||||
};
|
};
|
||||||
|
@ -273,10 +291,14 @@
|
||||||
>;
|
>;
|
||||||
};
|
};
|
||||||
|
|
||||||
pinctrl_stmpe: stmpegrp {
|
pinctrl_stmpe1: stmpe1grp {
|
||||||
fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
|
fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
pinctrl_stmpe2: stmpe2grp {
|
||||||
|
fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>;
|
||||||
|
};
|
||||||
|
|
||||||
pinctrl_uart1: uart1grp {
|
pinctrl_uart1: uart1grp {
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
|
||||||
|
@ -293,7 +315,7 @@
|
||||||
|
|
||||||
pinctrl_usbotg: usbotggrp {
|
pinctrl_usbotg: usbotggrp {
|
||||||
fsl,pins = <
|
fsl,pins = <
|
||||||
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
|
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
||||||
>;
|
>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -344,11 +366,11 @@
|
||||||
&usbh1 {
|
&usbh1 {
|
||||||
vbus-supply = <®_usb_host1>;
|
vbus-supply = <®_usb_host1>;
|
||||||
disable-over-current;
|
disable-over-current;
|
||||||
|
dr_mode = "host";
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
&usbotg {
|
&usbotg {
|
||||||
vbus-supply = <®_usb_otg_vbus>;
|
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
pinctrl-0 = <&pinctrl_usbotg>;
|
pinctrl-0 = <&pinctrl_usbotg>;
|
||||||
disable-over-current;
|
disable-over-current;
|
||||||
|
|
|
@ -487,9 +487,6 @@
|
||||||
|
|
||||||
&ldb {
|
&ldb {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
lvds-channel@0 {
|
|
||||||
crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
|
|
||||||
};
|
|
||||||
};
|
};
|
||||||
|
|
||||||
&pcie {
|
&pcie {
|
||||||
|
|
|
@ -436,9 +436,6 @@
|
||||||
|
|
||||||
&ldb {
|
&ldb {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
lvds-channel@0 {
|
|
||||||
crtcs = <&ipu1 0>, <&ipu1 1>;
|
|
||||||
};
|
|
||||||
};
|
};
|
||||||
|
|
||||||
&pcie {
|
&pcie {
|
||||||
|
|
|
@ -26,25 +26,25 @@
|
||||||
/* GPIO16 -> AR8035 25MHz */
|
/* GPIO16 -> AR8035 25MHz */
|
||||||
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000
|
||||||
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000
|
||||||
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
||||||
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
||||||
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
|
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
|
||||||
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
|
||||||
/* AR8035 pin strapping: IO voltage: pull up */
|
/* AR8035 pin strapping: IO voltage: pull up */
|
||||||
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
||||||
/* AR8035 pin strapping: PHYADDR#0: pull down */
|
/* AR8035 pin strapping: PHYADDR#0: pull down */
|
||||||
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
|
||||||
/* AR8035 pin strapping: PHYADDR#1: pull down */
|
/* AR8035 pin strapping: PHYADDR#1: pull down */
|
||||||
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
|
||||||
/* AR8035 pin strapping: MODE#1: pull up */
|
/* AR8035 pin strapping: MODE#1: pull up */
|
||||||
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
||||||
/* AR8035 pin strapping: MODE#3: pull up */
|
/* AR8035 pin strapping: MODE#3: pull up */
|
||||||
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
||||||
/* AR8035 pin strapping: MODE#0: pull down */
|
/* AR8035 pin strapping: MODE#0: pull down */
|
||||||
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* As the RMII pins are also connected to RGMII
|
* As the RMII pins are also connected to RGMII
|
||||||
|
|
|
@ -10,6 +10,8 @@
|
||||||
* http://www.gnu.org/copyleft/gpl.html
|
* http://www.gnu.org/copyleft/gpl.html
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
|
||||||
#include "skeleton.dtsi"
|
#include "skeleton.dtsi"
|
||||||
|
|
||||||
/ {
|
/ {
|
||||||
|
@ -46,8 +48,6 @@
|
||||||
intc: interrupt-controller@00a01000 {
|
intc: interrupt-controller@00a01000 {
|
||||||
compatible = "arm,cortex-a9-gic";
|
compatible = "arm,cortex-a9-gic";
|
||||||
#interrupt-cells = <3>;
|
#interrupt-cells = <3>;
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
reg = <0x00a01000 0x1000>,
|
reg = <0x00a01000 0x1000>,
|
||||||
<0x00a00100 0x100>;
|
<0x00a00100 0x100>;
|
||||||
|
@ -59,16 +59,19 @@
|
||||||
|
|
||||||
ckil {
|
ckil {
|
||||||
compatible = "fsl,imx-ckil", "fixed-clock";
|
compatible = "fsl,imx-ckil", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <32768>;
|
clock-frequency = <32768>;
|
||||||
};
|
};
|
||||||
|
|
||||||
ckih1 {
|
ckih1 {
|
||||||
compatible = "fsl,imx-ckih1", "fixed-clock";
|
compatible = "fsl,imx-ckih1", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <0>;
|
clock-frequency = <0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
osc {
|
osc {
|
||||||
compatible = "fsl,imx-osc", "fixed-clock";
|
compatible = "fsl,imx-osc", "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <24000000>;
|
clock-frequency = <24000000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
@ -138,6 +141,12 @@
|
||||||
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
|
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
|
||||||
num-lanes = <1>;
|
num-lanes = <1>;
|
||||||
interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
interrupt-map-mask = <0 0 0 0x7>;
|
||||||
|
interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
|
clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
|
||||||
clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
|
clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
|
|
|
@ -282,6 +282,7 @@
|
||||||
MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
|
MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
|
||||||
MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
|
MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
|
||||||
MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
|
MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
|
||||||
|
MX6SL_PAD_ECSPI1_SS0__GPIO4_IO11 0x80000000
|
||||||
>;
|
>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -68,8 +68,6 @@
|
||||||
intc: interrupt-controller@00a01000 {
|
intc: interrupt-controller@00a01000 {
|
||||||
compatible = "arm,cortex-a9-gic";
|
compatible = "arm,cortex-a9-gic";
|
||||||
#interrupt-cells = <3>;
|
#interrupt-cells = <3>;
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
reg = <0x00a01000 0x1000>,
|
reg = <0x00a01000 0x1000>,
|
||||||
<0x00a00100 0x100>;
|
<0x00a00100 0x100>;
|
||||||
|
@ -81,11 +79,13 @@
|
||||||
|
|
||||||
ckil {
|
ckil {
|
||||||
compatible = "fixed-clock";
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <32768>;
|
clock-frequency = <32768>;
|
||||||
};
|
};
|
||||||
|
|
||||||
osc {
|
osc {
|
||||||
compatible = "fixed-clock";
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <24000000>;
|
clock-frequency = <24000000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -75,7 +75,7 @@
|
||||||
m25p16@0 {
|
m25p16@0 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
compatible = "m25p16";
|
compatible = "st,m25p16";
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
spi-max-frequency = <40000000>;
|
spi-max-frequency = <40000000>;
|
||||||
mode = <0>;
|
mode = <0>;
|
||||||
|
|
|
@ -46,7 +46,7 @@
|
||||||
flash@0 {
|
flash@0 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
compatible = "mx25l4005a";
|
compatible = "mxicy,mx25l4005a";
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
spi-max-frequency = <20000000>;
|
spi-max-frequency = <20000000>;
|
||||||
mode = <0>;
|
mode = <0>;
|
||||||
|
|
|
@ -43,7 +43,7 @@
|
||||||
m25p40@0 {
|
m25p40@0 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
compatible = "mx25l1606e";
|
compatible = "mxicy,mx25l1606e";
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
spi-max-frequency = <50000000>;
|
spi-max-frequency = <50000000>;
|
||||||
mode = <0>;
|
mode = <0>;
|
||||||
|
|
|
@ -48,7 +48,7 @@
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
eeprom@50 {
|
eeprom@50 {
|
||||||
compatible = "at,24c04";
|
compatible = "atmel,24c04";
|
||||||
pagesize = <16>;
|
pagesize = <16>;
|
||||||
reg = <0x50>;
|
reg = <0x50>;
|
||||||
};
|
};
|
||||||
|
|
|
@ -56,7 +56,7 @@
|
||||||
flash@0 {
|
flash@0 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
compatible = "mx25l12805d";
|
compatible = "mxicy,mx25l12805d";
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
spi-max-frequency = <50000000>;
|
spi-max-frequency = <50000000>;
|
||||||
mode = <0>;
|
mode = <0>;
|
||||||
|
|
|
@ -32,7 +32,7 @@
|
||||||
flash@0 {
|
flash@0 {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
#size-cells = <1>;
|
#size-cells = <1>;
|
||||||
compatible = "mx25l4005a";
|
compatible = "mxicy,mx25l4005a";
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
spi-max-frequency = <20000000>;
|
spi-max-frequency = <20000000>;
|
||||||
mode = <0>;
|
mode = <0>;
|
||||||
|
@ -50,7 +50,7 @@
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
eeprom@50 {
|
eeprom@50 {
|
||||||
compatible = "at,24c04";
|
compatible = "atmel,24c04";
|
||||||
pagesize = <16>;
|
pagesize = <16>;
|
||||||
reg = <0x50>;
|
reg = <0x50>;
|
||||||
};
|
};
|
||||||
|
|
|
@ -104,7 +104,7 @@
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
adt7476: adt7476a@2e {
|
adt7476: adt7476a@2e {
|
||||||
compatible = "adt7476";
|
compatible = "adi,adt7476";
|
||||||
reg = <0x2e>;
|
reg = <0x2e>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -94,7 +94,7 @@
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
lm85: lm85@2e {
|
lm85: lm85@2e {
|
||||||
compatible = "lm85";
|
compatible = "national,lm85";
|
||||||
reg = <0x2e>;
|
reg = <0x2e>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -40,7 +40,7 @@
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
|
|
||||||
s35390a: s35390a@30 {
|
s35390a: s35390a@30 {
|
||||||
compatible = "s35390a";
|
compatible = "sii,s35390a";
|
||||||
reg = <0x30>;
|
reg = <0x30>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -52,7 +52,7 @@
|
||||||
pinctrl-names = "default";
|
pinctrl-names = "default";
|
||||||
|
|
||||||
s24c02: s24c02@50 {
|
s24c02: s24c02@50 {
|
||||||
compatible = "24c02";
|
compatible = "atmel,24c02";
|
||||||
reg = <0x50>;
|
reg = <0x50>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -0,0 +1,16 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "omap3-beagle-xm.dts"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
/* HS USB Port 2 Power enable was inverted with the xM C */
|
||||||
|
hsusb2_power: hsusb2_power_reg {
|
||||||
|
enable-active-high;
|
||||||
|
};
|
||||||
|
};
|
|
@ -112,7 +112,6 @@
|
||||||
reg = <0 0 0>; /* CS0, offset 0 */
|
reg = <0 0 0>; /* CS0, offset 0 */
|
||||||
nand-bus-width = <16>;
|
nand-bus-width = <16>;
|
||||||
|
|
||||||
gpmc,device-nand;
|
|
||||||
gpmc,sync-clk-ps = <0>;
|
gpmc,sync-clk-ps = <0>;
|
||||||
gpmc,cs-on-ns = <0>;
|
gpmc,cs-on-ns = <0>;
|
||||||
gpmc,cs-rd-off-ns = <44>;
|
gpmc,cs-rd-off-ns = <44>;
|
||||||
|
|
|
@ -368,7 +368,6 @@
|
||||||
/* no elm on omap3 */
|
/* no elm on omap3 */
|
||||||
|
|
||||||
gpmc,mux-add-data = <0>;
|
gpmc,mux-add-data = <0>;
|
||||||
gpmc,device-nand;
|
|
||||||
gpmc,device-width = <2>;
|
gpmc,device-width = <2>;
|
||||||
gpmc,wait-pin = <0>;
|
gpmc,wait-pin = <0>;
|
||||||
gpmc,wait-monitoring-ns = <0>;
|
gpmc,wait-monitoring-ns = <0>;
|
||||||
|
|
|
@ -74,7 +74,7 @@
|
||||||
/*
|
/*
|
||||||
* XXX: Use a flat representation of the OMAP3 interconnect.
|
* XXX: Use a flat representation of the OMAP3 interconnect.
|
||||||
* The real OMAP interconnect network is quite complex.
|
* The real OMAP interconnect network is quite complex.
|
||||||
* Since that will not bring real advantage to represent that in DT for
|
* Since it will not bring real advantage to represent that in DT for
|
||||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||||
* hierarchy.
|
* hierarchy.
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -72,7 +72,7 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The soc node represents the soc top level view. It is uses for IPs
|
* The soc node represents the soc top level view. It is used for IPs
|
||||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||||
*/
|
*/
|
||||||
soc {
|
soc {
|
||||||
|
@ -96,7 +96,7 @@
|
||||||
/*
|
/*
|
||||||
* XXX: Use a flat representation of the OMAP4 interconnect.
|
* XXX: Use a flat representation of the OMAP4 interconnect.
|
||||||
* The real OMAP interconnect network is quite complex.
|
* The real OMAP interconnect network is quite complex.
|
||||||
* Since that will not bring real advantage to represent that in DT for
|
* Since it will not bring real advantage to represent that in DT for
|
||||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||||
* hierarchy.
|
* hierarchy.
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -93,7 +93,7 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The soc node represents the soc top level view. It is uses for IPs
|
* The soc node represents the soc top level view. It is used for IPs
|
||||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||||
*/
|
*/
|
||||||
soc {
|
soc {
|
||||||
|
@ -107,7 +107,7 @@
|
||||||
/*
|
/*
|
||||||
* XXX: Use a flat representation of the OMAP3 interconnect.
|
* XXX: Use a flat representation of the OMAP3 interconnect.
|
||||||
* The real OMAP interconnect network is quite complex.
|
* The real OMAP interconnect network is quite complex.
|
||||||
* Since that will not bring real advantage to represent that in DT for
|
* Since it will not bring real advantage to represent that in DT for
|
||||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||||
* hierarchy.
|
* hierarchy.
|
||||||
*/
|
*/
|
||||||
|
@ -813,6 +813,12 @@
|
||||||
<0x4a084c00 0x40>;
|
<0x4a084c00 0x40>;
|
||||||
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
||||||
ctrl-module = <&omap_control_usb3phy>;
|
ctrl-module = <&omap_control_usb3phy>;
|
||||||
|
clocks = <&usb_phy_cm_clk32k>,
|
||||||
|
<&sys_clkin>,
|
||||||
|
<&usb_otg_ss_refclk960m>;
|
||||||
|
clock-names = "wkupclk",
|
||||||
|
"sysclk",
|
||||||
|
"refclk";
|
||||||
#phy-cells = <0>;
|
#phy-cells = <0>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -28,7 +28,6 @@
|
||||||
gic: interrupt-controller@c2800000 {
|
gic: interrupt-controller@c2800000 {
|
||||||
compatible = "arm,cortex-a9-gic";
|
compatible = "arm,cortex-a9-gic";
|
||||||
#interrupt-cells = <3>;
|
#interrupt-cells = <3>;
|
||||||
#address-cells = <1>;
|
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
reg = <0xc2800000 0x1000>,
|
reg = <0xc2800000 0x1000>,
|
||||||
<0xc2000000 0x1000>;
|
<0xc2000000 0x1000>;
|
||||||
|
|
|
@ -141,12 +141,12 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
sdhi0_pins: sd0 {
|
sdhi0_pins: sd0 {
|
||||||
renesas,gpios = "sdhi0_data4", "sdhi0_ctrl";
|
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||||
renesas,function = "sdhi0";
|
renesas,function = "sdhi0";
|
||||||
};
|
};
|
||||||
|
|
||||||
sdhi2_pins: sd2 {
|
sdhi2_pins: sd2 {
|
||||||
renesas,gpios = "sdhi2_data4", "sdhi2_ctrl";
|
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||||
renesas,function = "sdhi2";
|
renesas,function = "sdhi2";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -230,17 +230,17 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
sdhi0_pins: sd0 {
|
sdhi0_pins: sd0 {
|
||||||
renesas,gpios = "sdhi0_data4", "sdhi0_ctrl";
|
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
|
||||||
renesas,function = "sdhi0";
|
renesas,function = "sdhi0";
|
||||||
};
|
};
|
||||||
|
|
||||||
sdhi1_pins: sd1 {
|
sdhi1_pins: sd1 {
|
||||||
renesas,gpios = "sdhi1_data4", "sdhi1_ctrl";
|
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
|
||||||
renesas,function = "sdhi1";
|
renesas,function = "sdhi1";
|
||||||
};
|
};
|
||||||
|
|
||||||
sdhi2_pins: sd2 {
|
sdhi2_pins: sd2 {
|
||||||
renesas,gpios = "sdhi2_data4", "sdhi2_ctrl";
|
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||||
renesas,function = "sdhi2";
|
renesas,function = "sdhi2";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -149,7 +149,7 @@
|
||||||
|
|
||||||
uart0 {
|
uart0 {
|
||||||
uart0_xfer: uart0-xfer {
|
uart0_xfer: uart0-xfer {
|
||||||
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>,
|
rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
|
||||||
<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
|
<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -164,7 +164,7 @@
|
||||||
|
|
||||||
uart1 {
|
uart1 {
|
||||||
uart1_xfer: uart1-xfer {
|
uart1_xfer: uart1-xfer {
|
||||||
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_none>,
|
rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
|
||||||
<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
|
<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -179,7 +179,7 @@
|
||||||
|
|
||||||
uart2 {
|
uart2 {
|
||||||
uart2_xfer: uart2-xfer {
|
uart2_xfer: uart2-xfer {
|
||||||
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_none>,
|
rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
|
||||||
<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
|
<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
|
||||||
};
|
};
|
||||||
/* no rts / cts for uart2 */
|
/* no rts / cts for uart2 */
|
||||||
|
@ -187,7 +187,7 @@
|
||||||
|
|
||||||
uart3 {
|
uart3 {
|
||||||
uart3_xfer: uart3-xfer {
|
uart3_xfer: uart3-xfer {
|
||||||
rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_none>,
|
rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
|
||||||
<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
|
<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -34,7 +34,6 @@
|
||||||
gic: interrupt-controller@f0001000 {
|
gic: interrupt-controller@f0001000 {
|
||||||
compatible = "arm,cortex-a9-gic";
|
compatible = "arm,cortex-a9-gic";
|
||||||
#interrupt-cells = <3>;
|
#interrupt-cells = <3>;
|
||||||
#address-cells = <1>;
|
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
reg = <0xf0001000 0x1000>,
|
reg = <0xf0001000 0x1000>,
|
||||||
<0xf0000100 0x100>;
|
<0xf0000100 0x100>;
|
||||||
|
|
|
@ -233,19 +233,6 @@
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
serial@0,70006400 {
|
|
||||||
compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
|
|
||||||
reg = <0x0 0x70006400 0x0 0x40>;
|
|
||||||
reg-shift = <2>;
|
|
||||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
||||||
clocks = <&tegra_car TEGRA124_CLK_UARTE>;
|
|
||||||
resets = <&tegra_car 66>;
|
|
||||||
reset-names = "serial";
|
|
||||||
dmas = <&apbdma 20>, <&apbdma 20>;
|
|
||||||
dma-names = "rx", "tx";
|
|
||||||
status = "disabled";
|
|
||||||
};
|
|
||||||
|
|
||||||
pwm@0,7000a000 {
|
pwm@0,7000a000 {
|
||||||
compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
|
compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
|
||||||
reg = <0x0 0x7000a000 0x0 0x100>;
|
reg = <0x0 0x7000a000 0x0 0x100>;
|
||||||
|
|
|
@ -25,11 +25,13 @@
|
||||||
clocks {
|
clocks {
|
||||||
audio_ext {
|
audio_ext {
|
||||||
compatible = "fixed-clock";
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <24576000>;
|
clock-frequency = <24576000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
enet_ext {
|
enet_ext {
|
||||||
compatible = "fixed-clock";
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <50000000>;
|
clock-frequency = <50000000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
@ -45,11 +45,13 @@
|
||||||
|
|
||||||
sxosc {
|
sxosc {
|
||||||
compatible = "fixed-clock";
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <32768>;
|
clock-frequency = <32768>;
|
||||||
};
|
};
|
||||||
|
|
||||||
fxosc {
|
fxosc {
|
||||||
compatible = "fixed-clock";
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
clock-frequency = <24000000>;
|
clock-frequency = <24000000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
@ -72,8 +74,6 @@
|
||||||
intc: interrupt-controller@40002000 {
|
intc: interrupt-controller@40002000 {
|
||||||
compatible = "arm,cortex-a9-gic";
|
compatible = "arm,cortex-a9-gic";
|
||||||
#interrupt-cells = <3>;
|
#interrupt-cells = <3>;
|
||||||
#address-cells = <1>;
|
|
||||||
#size-cells = <1>;
|
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
reg = <0x40003000 0x1000>,
|
reg = <0x40003000 0x1000>,
|
||||||
<0x40002100 0x100>;
|
<0x40002100 0x100>;
|
||||||
|
|
|
@ -24,6 +24,7 @@
|
||||||
device_type = "cpu";
|
device_type = "cpu";
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
clocks = <&clkc 3>;
|
clocks = <&clkc 3>;
|
||||||
|
clock-latency = <1000>;
|
||||||
operating-points = <
|
operating-points = <
|
||||||
/* kHz uV */
|
/* kHz uV */
|
||||||
666667 1000000
|
666667 1000000
|
||||||
|
@ -54,6 +55,28 @@
|
||||||
interrupt-parent = <&intc>;
|
interrupt-parent = <&intc>;
|
||||||
ranges;
|
ranges;
|
||||||
|
|
||||||
|
i2c0: zynq-i2c@e0004000 {
|
||||||
|
compatible = "cdns,i2c-r1p10";
|
||||||
|
status = "disabled";
|
||||||
|
clocks = <&clkc 38>;
|
||||||
|
interrupt-parent = <&intc>;
|
||||||
|
interrupts = <0 25 4>;
|
||||||
|
reg = <0xe0004000 0x1000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c1: zynq-i2c@e0005000 {
|
||||||
|
compatible = "cdns,i2c-r1p10";
|
||||||
|
status = "disabled";
|
||||||
|
clocks = <&clkc 39>;
|
||||||
|
interrupt-parent = <&intc>;
|
||||||
|
interrupts = <0 48 4>;
|
||||||
|
reg = <0xe0005000 0x1000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
intc: interrupt-controller@f8f01000 {
|
intc: interrupt-controller@f8f01000 {
|
||||||
compatible = "arm,cortex-a9-gic";
|
compatible = "arm,cortex-a9-gic";
|
||||||
#interrupt-cells = <3>;
|
#interrupt-cells = <3>;
|
||||||
|
|
|
@ -34,6 +34,82 @@
|
||||||
phy-mode = "rgmii";
|
phy-mode = "rgmii";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&i2c0 {
|
||||||
|
status = "okay";
|
||||||
|
clock-frequency = <400000>;
|
||||||
|
|
||||||
|
i2cswitch@74 {
|
||||||
|
compatible = "nxp,pca9548";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <0x74>;
|
||||||
|
|
||||||
|
i2c@0 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <0>;
|
||||||
|
si570: clock-generator@5d {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "silabs,si570";
|
||||||
|
temperature-stability = <50>;
|
||||||
|
reg = <0x5d>;
|
||||||
|
factory-fout = <156250000>;
|
||||||
|
clock-frequency = <148500000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@2 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <2>;
|
||||||
|
eeprom@54 {
|
||||||
|
compatible = "at,24c08";
|
||||||
|
reg = <0x54>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@3 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <3>;
|
||||||
|
gpio@21 {
|
||||||
|
compatible = "ti,tca6416";
|
||||||
|
reg = <0x21>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@4 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <4>;
|
||||||
|
rtc@51 {
|
||||||
|
compatible = "nxp,pcf8563";
|
||||||
|
reg = <0x51>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@7 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <7>;
|
||||||
|
hwmon@52 {
|
||||||
|
compatible = "ti,ucd9248";
|
||||||
|
reg = <52>;
|
||||||
|
};
|
||||||
|
hwmon@53 {
|
||||||
|
compatible = "ti,ucd9248";
|
||||||
|
reg = <53>;
|
||||||
|
};
|
||||||
|
hwmon@54 {
|
||||||
|
compatible = "ti,ucd9248";
|
||||||
|
reg = <54>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
&sdhci0 {
|
&sdhci0 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
|
@ -35,6 +35,74 @@
|
||||||
phy-mode = "rgmii";
|
phy-mode = "rgmii";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&i2c0 {
|
||||||
|
status = "okay";
|
||||||
|
clock-frequency = <400000>;
|
||||||
|
|
||||||
|
i2cswitch@74 {
|
||||||
|
compatible = "nxp,pca9548";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <0x74>;
|
||||||
|
|
||||||
|
i2c@0 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <0>;
|
||||||
|
si570: clock-generator@5d {
|
||||||
|
#clock-cells = <0>;
|
||||||
|
compatible = "silabs,si570";
|
||||||
|
temperature-stability = <50>;
|
||||||
|
reg = <0x5d>;
|
||||||
|
factory-fout = <156250000>;
|
||||||
|
clock-frequency = <148500000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@2 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <2>;
|
||||||
|
eeprom@54 {
|
||||||
|
compatible = "at,24c08";
|
||||||
|
reg = <0x54>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@3 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <3>;
|
||||||
|
gpio@21 {
|
||||||
|
compatible = "ti,tca6416";
|
||||||
|
reg = <0x21>;
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@4 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <4>;
|
||||||
|
rtc@51 {
|
||||||
|
compatible = "nxp,pcf8563";
|
||||||
|
reg = <0x51>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c@7 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <7>;
|
||||||
|
ucd90120@65 {
|
||||||
|
compatible = "ti,ucd90120";
|
||||||
|
reg = <0x65>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
&sdhci0 {
|
&sdhci0 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
|
@ -226,7 +226,7 @@ CONFIG_USB_DWC3=m
|
||||||
CONFIG_USB_TEST=y
|
CONFIG_USB_TEST=y
|
||||||
CONFIG_NOP_USB_XCEIV=y
|
CONFIG_NOP_USB_XCEIV=y
|
||||||
CONFIG_OMAP_USB2=y
|
CONFIG_OMAP_USB2=y
|
||||||
CONFIG_OMAP_USB3=y
|
CONFIG_TI_PIPE3=y
|
||||||
CONFIG_AM335X_PHY_USB=y
|
CONFIG_AM335X_PHY_USB=y
|
||||||
CONFIG_USB_GADGET=y
|
CONFIG_USB_GADGET=y
|
||||||
CONFIG_USB_GADGET_DEBUG=y
|
CONFIG_USB_GADGET_DEBUG=y
|
||||||
|
|
|
@ -11,6 +11,7 @@ CONFIG_MODULES=y
|
||||||
CONFIG_MODULE_UNLOAD=y
|
CONFIG_MODULE_UNLOAD=y
|
||||||
# CONFIG_LBDAF is not set
|
# CONFIG_LBDAF is not set
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
# CONFIG_BLK_DEV_BSG is not set
|
||||||
|
CONFIG_PARTITION_ADVANCED=y
|
||||||
# CONFIG_IOSCHED_CFQ is not set
|
# CONFIG_IOSCHED_CFQ is not set
|
||||||
# CONFIG_ARCH_MULTI_V7 is not set
|
# CONFIG_ARCH_MULTI_V7 is not set
|
||||||
CONFIG_ARCH_U300=y
|
CONFIG_ARCH_U300=y
|
||||||
|
@ -21,7 +22,6 @@ CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||||
CONFIG_ZBOOT_ROM_BSS=0x0
|
CONFIG_ZBOOT_ROM_BSS=0x0
|
||||||
CONFIG_CMDLINE="root=/dev/ram0 rw rootfstype=rootfs console=ttyAMA0,115200n8 lpj=515072"
|
CONFIG_CMDLINE="root=/dev/ram0 rw rootfstype=rootfs console=ttyAMA0,115200n8 lpj=515072"
|
||||||
CONFIG_CPU_IDLE=y
|
CONFIG_CPU_IDLE=y
|
||||||
CONFIG_FPE_NWFPE=y
|
|
||||||
# CONFIG_SUSPEND is not set
|
# CONFIG_SUSPEND is not set
|
||||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||||
|
@ -64,8 +64,8 @@ CONFIG_TMPFS=y
|
||||||
CONFIG_NLS_CODEPAGE_437=y
|
CONFIG_NLS_CODEPAGE_437=y
|
||||||
CONFIG_NLS_ISO8859_1=y
|
CONFIG_NLS_ISO8859_1=y
|
||||||
CONFIG_PRINTK_TIME=y
|
CONFIG_PRINTK_TIME=y
|
||||||
|
CONFIG_DEBUG_INFO=y
|
||||||
CONFIG_DEBUG_FS=y
|
CONFIG_DEBUG_FS=y
|
||||||
# CONFIG_SCHED_DEBUG is not set
|
# CONFIG_SCHED_DEBUG is not set
|
||||||
CONFIG_TIMER_STATS=y
|
CONFIG_TIMER_STATS=y
|
||||||
# CONFIG_DEBUG_PREEMPT is not set
|
# CONFIG_DEBUG_PREEMPT is not set
|
||||||
CONFIG_DEBUG_INFO=y
|
|
||||||
|
|
|
@ -1,16 +1,16 @@
|
||||||
# CONFIG_SWAP is not set
|
# CONFIG_SWAP is not set
|
||||||
CONFIG_SYSVIPC=y
|
CONFIG_SYSVIPC=y
|
||||||
CONFIG_NO_HZ=y
|
CONFIG_NO_HZ_IDLE=y
|
||||||
CONFIG_HIGH_RES_TIMERS=y
|
CONFIG_HIGH_RES_TIMERS=y
|
||||||
CONFIG_BLK_DEV_INITRD=y
|
CONFIG_BLK_DEV_INITRD=y
|
||||||
CONFIG_KALLSYMS_ALL=y
|
CONFIG_KALLSYMS_ALL=y
|
||||||
CONFIG_MODULES=y
|
CONFIG_MODULES=y
|
||||||
CONFIG_MODULE_UNLOAD=y
|
CONFIG_MODULE_UNLOAD=y
|
||||||
# CONFIG_BLK_DEV_BSG is not set
|
# CONFIG_BLK_DEV_BSG is not set
|
||||||
|
CONFIG_PARTITION_ADVANCED=y
|
||||||
CONFIG_ARCH_U8500=y
|
CONFIG_ARCH_U8500=y
|
||||||
CONFIG_MACH_HREFV60=y
|
CONFIG_MACH_HREFV60=y
|
||||||
CONFIG_MACH_SNOWBALL=y
|
CONFIG_MACH_SNOWBALL=y
|
||||||
CONFIG_MACH_UX500_DT=y
|
|
||||||
CONFIG_SMP=y
|
CONFIG_SMP=y
|
||||||
CONFIG_NR_CPUS=2
|
CONFIG_NR_CPUS=2
|
||||||
CONFIG_PREEMPT=y
|
CONFIG_PREEMPT=y
|
||||||
|
@ -34,16 +34,22 @@ CONFIG_IP_PNP=y
|
||||||
CONFIG_IP_PNP_DHCP=y
|
CONFIG_IP_PNP_DHCP=y
|
||||||
CONFIG_NETFILTER=y
|
CONFIG_NETFILTER=y
|
||||||
CONFIG_PHONET=y
|
CONFIG_PHONET=y
|
||||||
# CONFIG_WIRELESS is not set
|
CONFIG_CFG80211=y
|
||||||
|
CONFIG_CFG80211_DEBUGFS=y
|
||||||
|
CONFIG_MAC80211=y
|
||||||
|
CONFIG_MAC80211_LEDS=y
|
||||||
CONFIG_CAIF=y
|
CONFIG_CAIF=y
|
||||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||||
|
CONFIG_DEVTMPFS=y
|
||||||
|
CONFIG_DEVTMPFS_MOUNT=y
|
||||||
CONFIG_BLK_DEV_RAM=y
|
CONFIG_BLK_DEV_RAM=y
|
||||||
CONFIG_BLK_DEV_RAM_SIZE=65536
|
CONFIG_BLK_DEV_RAM_SIZE=65536
|
||||||
CONFIG_SENSORS_BH1780=y
|
CONFIG_SENSORS_BH1780=y
|
||||||
CONFIG_NETDEVICES=y
|
CONFIG_NETDEVICES=y
|
||||||
CONFIG_SMSC911X=y
|
CONFIG_SMSC911X=y
|
||||||
CONFIG_SMSC_PHY=y
|
CONFIG_SMSC_PHY=y
|
||||||
# CONFIG_WLAN is not set
|
CONFIG_CW1200=y
|
||||||
|
CONFIG_CW1200_WLAN_SDIO=y
|
||||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
||||||
CONFIG_INPUT_EVDEV=y
|
CONFIG_INPUT_EVDEV=y
|
||||||
# CONFIG_KEYBOARD_ATKBD is not set
|
# CONFIG_KEYBOARD_ATKBD is not set
|
||||||
|
@ -85,15 +91,12 @@ CONFIG_AB8500_USB=y
|
||||||
CONFIG_USB_GADGET=y
|
CONFIG_USB_GADGET=y
|
||||||
CONFIG_USB_ETH=m
|
CONFIG_USB_ETH=m
|
||||||
CONFIG_MMC=y
|
CONFIG_MMC=y
|
||||||
CONFIG_MMC_UNSAFE_RESUME=y
|
|
||||||
# CONFIG_MMC_BLOCK_BOUNCE is not set
|
|
||||||
CONFIG_MMC_ARMMMCI=y
|
CONFIG_MMC_ARMMMCI=y
|
||||||
CONFIG_NEW_LEDS=y
|
CONFIG_NEW_LEDS=y
|
||||||
CONFIG_LEDS_CLASS=y
|
CONFIG_LEDS_CLASS=y
|
||||||
CONFIG_LEDS_LM3530=y
|
CONFIG_LEDS_LM3530=y
|
||||||
CONFIG_LEDS_GPIO=y
|
CONFIG_LEDS_GPIO=y
|
||||||
CONFIG_LEDS_LP5521=y
|
CONFIG_LEDS_LP5521=y
|
||||||
CONFIG_LEDS_TRIGGERS=y
|
|
||||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||||
CONFIG_RTC_CLASS=y
|
CONFIG_RTC_CLASS=y
|
||||||
CONFIG_RTC_DRV_AB8500=y
|
CONFIG_RTC_DRV_AB8500=y
|
||||||
|
@ -103,6 +106,11 @@ CONFIG_STE_DMA40=y
|
||||||
CONFIG_STAGING=y
|
CONFIG_STAGING=y
|
||||||
CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y
|
CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y
|
||||||
CONFIG_HSEM_U8500=y
|
CONFIG_HSEM_U8500=y
|
||||||
|
CONFIG_IIO=y
|
||||||
|
CONFIG_IIO_ST_ACCEL_3AXIS=y
|
||||||
|
CONFIG_IIO_ST_GYRO_3AXIS=y
|
||||||
|
CONFIG_IIO_ST_MAGN_3AXIS=y
|
||||||
|
CONFIG_IIO_ST_PRESS=y
|
||||||
CONFIG_EXT2_FS=y
|
CONFIG_EXT2_FS=y
|
||||||
CONFIG_EXT2_FS_XATTR=y
|
CONFIG_EXT2_FS_XATTR=y
|
||||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||||
|
@ -110,8 +118,6 @@ CONFIG_EXT2_FS_SECURITY=y
|
||||||
CONFIG_EXT3_FS=y
|
CONFIG_EXT3_FS=y
|
||||||
CONFIG_EXT4_FS=y
|
CONFIG_EXT4_FS=y
|
||||||
CONFIG_VFAT_FS=y
|
CONFIG_VFAT_FS=y
|
||||||
CONFIG_DEVTMPFS=y
|
|
||||||
CONFIG_DEVTMPFS_MOUNT=y
|
|
||||||
CONFIG_TMPFS=y
|
CONFIG_TMPFS=y
|
||||||
CONFIG_TMPFS_POSIX_ACL=y
|
CONFIG_TMPFS_POSIX_ACL=y
|
||||||
# CONFIG_MISC_FILESYSTEMS is not set
|
# CONFIG_MISC_FILESYSTEMS is not set
|
||||||
|
|
|
@ -208,8 +208,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
||||||
* the "output_enable" bit as a gate, even though it's really just
|
* the "output_enable" bit as a gate, even though it's really just
|
||||||
* enabling clock output.
|
* enabling clock output.
|
||||||
*/
|
*/
|
||||||
clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10);
|
clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "lvds1_sel", base + 0x160, 10);
|
||||||
clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11);
|
clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "lvds2_sel", base + 0x160, 11);
|
||||||
|
|
||||||
/* name parent_name reg idx */
|
/* name parent_name reg idx */
|
||||||
clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
|
clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
|
||||||
|
@ -258,14 +258,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
||||||
clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
|
clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
|
||||||
clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
clk[ldb_di0_sel] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||||
clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
clk[ldb_di1_sel] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
|
||||||
clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
|
clk[ipu1_di0_pre_sel] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||||
clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
|
clk[ipu1_di1_pre_sel] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||||
clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
|
clk[ipu2_di0_pre_sel] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||||
clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
|
clk[ipu2_di1_pre_sel] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
|
||||||
clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels));
|
clk[ipu1_di0_sel] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
|
||||||
clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels));
|
clk[ipu1_di1_sel] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
|
||||||
clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels));
|
clk[ipu2_di0_sel] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
|
||||||
clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
|
clk[ipu2_di1_sel] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
|
||||||
clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
|
clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
|
||||||
clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
|
clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
|
||||||
clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
|
||||||
|
@ -445,6 +445,15 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
|
||||||
clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
|
clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
|
||||||
|
clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
|
||||||
|
clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
|
||||||
|
clk_set_parent(clk[ipu2_di1_pre_sel], clk[pll5_video_div]);
|
||||||
|
clk_set_parent(clk[ipu1_di0_sel], clk[ipu1_di0_pre]);
|
||||||
|
clk_set_parent(clk[ipu1_di1_sel], clk[ipu1_di1_pre]);
|
||||||
|
clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
|
||||||
|
clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
|
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
|
||||||
* We can not get the 100MHz from the pll2_pfd0_352m.
|
* We can not get the 100MHz from the pll2_pfd0_352m.
|
||||||
|
|
|
@ -48,7 +48,7 @@ static struct omap_dss_board_info rx51_dss_board_info = {
|
||||||
|
|
||||||
static int __init rx51_video_init(void)
|
static int __init rx51_video_init(void)
|
||||||
{
|
{
|
||||||
if (!machine_is_nokia_rx51() && !of_machine_is_compatible("nokia,omap3-n900"))
|
if (!machine_is_nokia_rx51())
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
if (omap_mux_init_gpio(RX51_LCD_RESET_GPIO, OMAP_PIN_OUTPUT)) {
|
if (omap_mux_init_gpio(RX51_LCD_RESET_GPIO, OMAP_PIN_OUTPUT)) {
|
||||||
|
|
|
@ -209,7 +209,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
|
||||||
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
|
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
|
||||||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
|
v == OMAP3XXX_EN_DPLL_FRBYPASS)
|
||||||
return 1;
|
return 1;
|
||||||
} else if (soc_is_am33xx() || cpu_is_omap44xx()) {
|
} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
|
||||||
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
|
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
|
||||||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
|
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
|
||||||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
|
v == OMAP4XXX_EN_DPLL_MNBYPASS)
|
||||||
|
@ -255,7 +255,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
|
||||||
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
|
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
|
||||||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
|
v == OMAP3XXX_EN_DPLL_FRBYPASS)
|
||||||
return __clk_get_rate(dd->clk_bypass);
|
return __clk_get_rate(dd->clk_bypass);
|
||||||
} else if (soc_is_am33xx() || cpu_is_omap44xx()) {
|
} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {
|
||||||
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
|
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
|
||||||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
|
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
|
||||||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
|
v == OMAP4XXX_EN_DPLL_MNBYPASS)
|
||||||
|
|
|
@ -501,7 +501,7 @@ static int gpmc_cs_delete_mem(int cs)
|
||||||
int r;
|
int r;
|
||||||
|
|
||||||
spin_lock(&gpmc_mem_lock);
|
spin_lock(&gpmc_mem_lock);
|
||||||
r = release_resource(&gpmc_cs_mem[cs]);
|
r = release_resource(res);
|
||||||
res->start = 0;
|
res->start = 0;
|
||||||
res->end = 0;
|
res->end = 0;
|
||||||
spin_unlock(&gpmc_mem_lock);
|
spin_unlock(&gpmc_mem_lock);
|
||||||
|
@ -527,6 +527,14 @@ static int gpmc_cs_remap(int cs, u32 base)
|
||||||
pr_err("%s: requested chip-select is disabled\n", __func__);
|
pr_err("%s: requested chip-select is disabled\n", __func__);
|
||||||
return -ENODEV;
|
return -ENODEV;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Make sure we ignore any device offsets from the GPMC partition
|
||||||
|
* allocated for the chip select and that the new base confirms
|
||||||
|
* to the GPMC 16MB minimum granularity.
|
||||||
|
*/
|
||||||
|
base &= ~(SZ_16M - 1);
|
||||||
|
|
||||||
gpmc_cs_get_memconf(cs, &old_base, &size);
|
gpmc_cs_get_memconf(cs, &old_base, &size);
|
||||||
if (base == old_base)
|
if (base == old_base)
|
||||||
return 0;
|
return 0;
|
||||||
|
@ -586,6 +594,8 @@ EXPORT_SYMBOL(gpmc_cs_request);
|
||||||
|
|
||||||
void gpmc_cs_free(int cs)
|
void gpmc_cs_free(int cs)
|
||||||
{
|
{
|
||||||
|
struct resource *res = &gpmc_cs_mem[cs];
|
||||||
|
|
||||||
spin_lock(&gpmc_mem_lock);
|
spin_lock(&gpmc_mem_lock);
|
||||||
if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
|
if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
|
||||||
printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
|
printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
|
||||||
|
@ -594,7 +604,8 @@ void gpmc_cs_free(int cs)
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
gpmc_cs_disable_mem(cs);
|
gpmc_cs_disable_mem(cs);
|
||||||
release_resource(&gpmc_cs_mem[cs]);
|
if (res->flags)
|
||||||
|
release_resource(res);
|
||||||
gpmc_cs_set_reserved(cs, 0);
|
gpmc_cs_set_reserved(cs, 0);
|
||||||
spin_unlock(&gpmc_mem_lock);
|
spin_unlock(&gpmc_mem_lock);
|
||||||
}
|
}
|
||||||
|
|
|
@ -2546,11 +2546,12 @@ static int __init _init(struct omap_hwmod *oh, void *data)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
if (np)
|
if (np) {
|
||||||
if (of_find_property(np, "ti,no-reset-on-init", NULL))
|
if (of_find_property(np, "ti,no-reset-on-init", NULL))
|
||||||
oh->flags |= HWMOD_INIT_NO_RESET;
|
oh->flags |= HWMOD_INIT_NO_RESET;
|
||||||
if (of_find_property(np, "ti,no-idle-on-init", NULL))
|
if (of_find_property(np, "ti,no-idle-on-init", NULL))
|
||||||
oh->flags |= HWMOD_INIT_NO_IDLE;
|
oh->flags |= HWMOD_INIT_NO_IDLE;
|
||||||
|
}
|
||||||
|
|
||||||
oh->_state = _HWMOD_STATE_INITIALIZED;
|
oh->_state = _HWMOD_STATE_INITIALIZED;
|
||||||
|
|
||||||
|
|
|
@ -1964,7 +1964,7 @@ static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
|
||||||
static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
|
static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
|
||||||
.name = "usb_host_hs",
|
.name = "usb_host_hs",
|
||||||
.class = &omap3xxx_usb_host_hs_hwmod_class,
|
.class = &omap3xxx_usb_host_hs_hwmod_class,
|
||||||
.clkdm_name = "l3_init_clkdm",
|
.clkdm_name = "usbhost_clkdm",
|
||||||
.mpu_irqs = omap3xxx_usb_host_hs_irqs,
|
.mpu_irqs = omap3xxx_usb_host_hs_irqs,
|
||||||
.main_clk = "usbhost_48m_fck",
|
.main_clk = "usbhost_48m_fck",
|
||||||
.prcm = {
|
.prcm = {
|
||||||
|
@ -2047,7 +2047,7 @@ static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
|
||||||
static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
|
static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
|
||||||
.name = "usb_tll_hs",
|
.name = "usb_tll_hs",
|
||||||
.class = &omap3xxx_usb_tll_hs_hwmod_class,
|
.class = &omap3xxx_usb_tll_hs_hwmod_class,
|
||||||
.clkdm_name = "l3_init_clkdm",
|
.clkdm_name = "core_l4_clkdm",
|
||||||
.mpu_irqs = omap3xxx_usb_tll_hs_irqs,
|
.mpu_irqs = omap3xxx_usb_tll_hs_irqs,
|
||||||
.main_clk = "usbtll_fck",
|
.main_clk = "usbtll_fck",
|
||||||
.prcm = {
|
.prcm = {
|
||||||
|
|
|
@ -330,10 +330,6 @@ void omap_sram_idle(void)
|
||||||
omap3_sram_restore_context();
|
omap3_sram_restore_context();
|
||||||
omap2_sms_restore_context();
|
omap2_sms_restore_context();
|
||||||
}
|
}
|
||||||
if (core_next_state == PWRDM_POWER_OFF)
|
|
||||||
omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
|
|
||||||
OMAP3430_GR_MOD,
|
|
||||||
OMAP3_PRM_VOLTCTRL_OFFSET);
|
|
||||||
}
|
}
|
||||||
omap3_intc_resume_idle();
|
omap3_intc_resume_idle();
|
||||||
|
|
||||||
|
|
|
@ -14,6 +14,7 @@
|
||||||
|
|
||||||
#include <linux/gpio.h>
|
#include <linux/gpio.h>
|
||||||
#include <linux/mfd/asic3.h>
|
#include <linux/mfd/asic3.h>
|
||||||
|
#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */
|
||||||
|
|
||||||
#define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO
|
#define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO
|
||||||
#define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS)
|
#define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS)
|
||||||
|
|
|
@ -152,7 +152,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
|
||||||
|
|
||||||
node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
|
node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
|
||||||
if (!node) {
|
if (!node) {
|
||||||
pr_err("%s: could not find sram dt node\n", __func__);
|
pr_err("%s: could not find pmu dt node\n", __func__);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -992,6 +992,7 @@ static struct asoc_simple_card_info fsi_wm8978_info = {
|
||||||
.platform = "sh_fsi2",
|
.platform = "sh_fsi2",
|
||||||
.daifmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
|
.daifmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM,
|
||||||
.cpu_dai = {
|
.cpu_dai = {
|
||||||
|
.fmt = SND_SOC_DAIFMT_IB_NF,
|
||||||
.name = "fsia-dai",
|
.name = "fsia-dai",
|
||||||
},
|
},
|
||||||
.codec_dai = {
|
.codec_dai = {
|
||||||
|
|
|
@ -588,14 +588,12 @@ static struct asoc_simple_card_info rsnd_card_info = {
|
||||||
.card = "SSI01-AK4643",
|
.card = "SSI01-AK4643",
|
||||||
.codec = "ak4642-codec.2-0012",
|
.codec = "ak4642-codec.2-0012",
|
||||||
.platform = "rcar_sound",
|
.platform = "rcar_sound",
|
||||||
.daifmt = SND_SOC_DAIFMT_LEFT_J,
|
.daifmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM,
|
||||||
.cpu_dai = {
|
.cpu_dai = {
|
||||||
.name = "rcar_sound",
|
.name = "rcar_sound",
|
||||||
.fmt = SND_SOC_DAIFMT_CBS_CFS,
|
|
||||||
},
|
},
|
||||||
.codec_dai = {
|
.codec_dai = {
|
||||||
.name = "ak4642-hifi",
|
.name = "ak4642-hifi",
|
||||||
.fmt = SND_SOC_DAIFMT_CBM_CFM,
|
|
||||||
.sysclk = 11289600,
|
.sysclk = 11289600,
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
|
@ -71,7 +71,7 @@ static void clockevent_set_mode(enum clock_event_mode mode,
|
||||||
static int clockevent_next_event(unsigned long evt,
|
static int clockevent_next_event(unsigned long evt,
|
||||||
struct clock_event_device *clk_event_dev);
|
struct clock_event_device *clk_event_dev);
|
||||||
|
|
||||||
static void spear_clocksource_init(void)
|
static void __init spear_clocksource_init(void)
|
||||||
{
|
{
|
||||||
u32 tick_rate;
|
u32 tick_rate;
|
||||||
u16 val;
|
u16 val;
|
||||||
|
|
|
@ -70,7 +70,4 @@ config TEGRA_AHB
|
||||||
which controls AHB bus master arbitration and some
|
which controls AHB bus master arbitration and some
|
||||||
performance parameters(priority, prefech size).
|
performance parameters(priority, prefech size).
|
||||||
|
|
||||||
config TEGRA_EMC_SCALING_ENABLE
|
|
||||||
bool "Enable scaling the memory frequency"
|
|
||||||
|
|
||||||
endmenu
|
endmenu
|
||||||
|
|
|
@ -51,12 +51,14 @@ static int dcscb_allcpus_mask[2];
|
||||||
static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
|
static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
|
||||||
{
|
{
|
||||||
unsigned int rst_hold, cpumask = (1 << cpu);
|
unsigned int rst_hold, cpumask = (1 << cpu);
|
||||||
unsigned int all_mask = dcscb_allcpus_mask[cluster];
|
unsigned int all_mask;
|
||||||
|
|
||||||
pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
|
pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
|
||||||
if (cpu >= 4 || cluster >= 2)
|
if (cpu >= 4 || cluster >= 2)
|
||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
|
|
||||||
|
all_mask = dcscb_allcpus_mask[cluster];
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Since this is called with IRQs enabled, and no arch_spin_lock_irq
|
* Since this is called with IRQs enabled, and no arch_spin_lock_irq
|
||||||
* variant exists, we need to disable IRQs manually here.
|
* variant exists, we need to disable IRQs manually here.
|
||||||
|
@ -101,11 +103,12 @@ static void dcscb_power_down(void)
|
||||||
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
|
||||||
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
|
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
|
||||||
cpumask = (1 << cpu);
|
cpumask = (1 << cpu);
|
||||||
all_mask = dcscb_allcpus_mask[cluster];
|
|
||||||
|
|
||||||
pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
|
pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
|
||||||
BUG_ON(cpu >= 4 || cluster >= 2);
|
BUG_ON(cpu >= 4 || cluster >= 2);
|
||||||
|
|
||||||
|
all_mask = dcscb_allcpus_mask[cluster];
|
||||||
|
|
||||||
__mcpm_cpu_going_down(cpu, cluster);
|
__mcpm_cpu_going_down(cpu, cluster);
|
||||||
|
|
||||||
arch_spin_lock(&dcscb_lock);
|
arch_spin_lock(&dcscb_lock);
|
||||||
|
|
|
@ -392,7 +392,7 @@ static irqreturn_t ve_spc_irq_handler(int irq, void *data)
|
||||||
* +--------------------------+
|
* +--------------------------+
|
||||||
* | 31 20 | 19 0 |
|
* | 31 20 | 19 0 |
|
||||||
* +--------------------------+
|
* +--------------------------+
|
||||||
* | u_volt | freq(kHz) |
|
* | m_volt | freq(kHz) |
|
||||||
* +--------------------------+
|
* +--------------------------+
|
||||||
*/
|
*/
|
||||||
#define MULT_FACTOR 20
|
#define MULT_FACTOR 20
|
||||||
|
@ -414,7 +414,7 @@ static int ve_spc_populate_opps(uint32_t cluster)
|
||||||
ret = ve_spc_read_sys_cfg(SYSCFG_SCC, off, &data);
|
ret = ve_spc_read_sys_cfg(SYSCFG_SCC, off, &data);
|
||||||
if (!ret) {
|
if (!ret) {
|
||||||
opps->freq = (data & FREQ_MASK) * MULT_FACTOR;
|
opps->freq = (data & FREQ_MASK) * MULT_FACTOR;
|
||||||
opps->u_volt = data >> VOLT_SHIFT;
|
opps->u_volt = (data >> VOLT_SHIFT) * 1000;
|
||||||
} else {
|
} else {
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
|
@ -764,7 +764,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
|
||||||
[tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
|
[tegra_clk_sdmmc2_8] = { .dt_id = TEGRA124_CLK_SDMMC2, .present = true },
|
||||||
[tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
|
[tegra_clk_i2s1] = { .dt_id = TEGRA124_CLK_I2S1, .present = true },
|
||||||
[tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
|
[tegra_clk_i2c1] = { .dt_id = TEGRA124_CLK_I2C1, .present = true },
|
||||||
[tegra_clk_ndflash] = { .dt_id = TEGRA124_CLK_NDFLASH, .present = true },
|
|
||||||
[tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
|
[tegra_clk_sdmmc1_8] = { .dt_id = TEGRA124_CLK_SDMMC1, .present = true },
|
||||||
[tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
|
[tegra_clk_sdmmc4_8] = { .dt_id = TEGRA124_CLK_SDMMC4, .present = true },
|
||||||
[tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
|
[tegra_clk_pwm] = { .dt_id = TEGRA124_CLK_PWM, .present = true },
|
||||||
|
@ -809,7 +808,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
|
||||||
[tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
|
[tegra_clk_trace] = { .dt_id = TEGRA124_CLK_TRACE, .present = true },
|
||||||
[tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
|
[tegra_clk_soc_therm] = { .dt_id = TEGRA124_CLK_SOC_THERM, .present = true },
|
||||||
[tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
|
[tegra_clk_dtv] = { .dt_id = TEGRA124_CLK_DTV, .present = true },
|
||||||
[tegra_clk_ndspeed] = { .dt_id = TEGRA124_CLK_NDSPEED, .present = true },
|
|
||||||
[tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
|
[tegra_clk_i2cslow] = { .dt_id = TEGRA124_CLK_I2CSLOW, .present = true },
|
||||||
[tegra_clk_dsib] = { .dt_id = TEGRA124_CLK_DSIB, .present = true },
|
[tegra_clk_dsib] = { .dt_id = TEGRA124_CLK_DSIB, .present = true },
|
||||||
[tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
|
[tegra_clk_tsec] = { .dt_id = TEGRA124_CLK_TSEC, .present = true },
|
||||||
|
@ -952,7 +950,6 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
|
||||||
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
|
[tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
|
||||||
[tegra_clk_dsia_mux] = { .dt_id = TEGRA124_CLK_DSIA_MUX, .present = true },
|
[tegra_clk_dsia_mux] = { .dt_id = TEGRA124_CLK_DSIA_MUX, .present = true },
|
||||||
[tegra_clk_dsib_mux] = { .dt_id = TEGRA124_CLK_DSIB_MUX, .present = true },
|
[tegra_clk_dsib_mux] = { .dt_id = TEGRA124_CLK_DSIB_MUX, .present = true },
|
||||||
[tegra_clk_uarte] = { .dt_id = TEGRA124_CLK_UARTE, .present = true },
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct tegra_devclk devclks[] __initdata = {
|
static struct tegra_devclk devclks[] __initdata = {
|
||||||
|
|
|
@ -102,7 +102,7 @@ void __init vexpress_osc_of_setup(struct device_node *node)
|
||||||
|
|
||||||
osc = kzalloc(sizeof(*osc), GFP_KERNEL);
|
osc = kzalloc(sizeof(*osc), GFP_KERNEL);
|
||||||
if (!osc)
|
if (!osc)
|
||||||
goto error;
|
return;
|
||||||
|
|
||||||
osc->func = vexpress_config_func_get_by_node(node);
|
osc->func = vexpress_config_func_get_by_node(node);
|
||||||
if (!osc->func) {
|
if (!osc->func) {
|
||||||
|
|
|
@ -11,7 +11,7 @@
|
||||||
* Copyright (C) 2012 ARM Limited
|
* Copyright (C) 2012 ARM Limited
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <linux/jiffies.h>
|
#include <linux/delay.h>
|
||||||
#include <linux/of.h>
|
#include <linux/of.h>
|
||||||
#include <linux/of_device.h>
|
#include <linux/of_device.h>
|
||||||
#include <linux/platform_device.h>
|
#include <linux/platform_device.h>
|
||||||
|
@ -23,17 +23,12 @@
|
||||||
static void vexpress_reset_do(struct device *dev, const char *what)
|
static void vexpress_reset_do(struct device *dev, const char *what)
|
||||||
{
|
{
|
||||||
int err = -ENOENT;
|
int err = -ENOENT;
|
||||||
struct vexpress_config_func *func =
|
struct vexpress_config_func *func = dev_get_drvdata(dev);
|
||||||
vexpress_config_func_get_by_dev(dev);
|
|
||||||
|
|
||||||
if (func) {
|
if (func) {
|
||||||
unsigned long timeout;
|
|
||||||
|
|
||||||
err = vexpress_config_write(func, 0, 0);
|
err = vexpress_config_write(func, 0, 0);
|
||||||
|
if (!err)
|
||||||
timeout = jiffies + HZ;
|
mdelay(1000);
|
||||||
while (time_before(jiffies, timeout))
|
|
||||||
cpu_relax();
|
|
||||||
}
|
}
|
||||||
|
|
||||||
dev_emerg(dev, "Unable to %s (%d)\n", what, err);
|
dev_emerg(dev, "Unable to %s (%d)\n", what, err);
|
||||||
|
@ -96,12 +91,18 @@ static int vexpress_reset_probe(struct platform_device *pdev)
|
||||||
enum vexpress_reset_func func;
|
enum vexpress_reset_func func;
|
||||||
const struct of_device_id *match =
|
const struct of_device_id *match =
|
||||||
of_match_device(vexpress_reset_of_match, &pdev->dev);
|
of_match_device(vexpress_reset_of_match, &pdev->dev);
|
||||||
|
struct vexpress_config_func *config_func;
|
||||||
|
|
||||||
if (match)
|
if (match)
|
||||||
func = (enum vexpress_reset_func)match->data;
|
func = (enum vexpress_reset_func)match->data;
|
||||||
else
|
else
|
||||||
func = pdev->id_entry->driver_data;
|
func = pdev->id_entry->driver_data;
|
||||||
|
|
||||||
|
config_func = vexpress_config_func_get_by_dev(&pdev->dev);
|
||||||
|
if (!config_func)
|
||||||
|
return -EINVAL;
|
||||||
|
dev_set_drvdata(&pdev->dev, config_func);
|
||||||
|
|
||||||
switch (func) {
|
switch (func) {
|
||||||
case FUNC_SHUTDOWN:
|
case FUNC_SHUTDOWN:
|
||||||
vexpress_power_off_device = &pdev->dev;
|
vexpress_power_off_device = &pdev->dev;
|
||||||
|
|
|
@ -29,7 +29,7 @@
|
||||||
/* 10 (register bit affects spdif_in and spdif_out) */
|
/* 10 (register bit affects spdif_in and spdif_out) */
|
||||||
#define TEGRA124_CLK_I2S1 11
|
#define TEGRA124_CLK_I2S1 11
|
||||||
#define TEGRA124_CLK_I2C1 12
|
#define TEGRA124_CLK_I2C1 12
|
||||||
#define TEGRA124_CLK_NDFLASH 13
|
/* 13 */
|
||||||
#define TEGRA124_CLK_SDMMC1 14
|
#define TEGRA124_CLK_SDMMC1 14
|
||||||
#define TEGRA124_CLK_SDMMC4 15
|
#define TEGRA124_CLK_SDMMC4 15
|
||||||
/* 16 */
|
/* 16 */
|
||||||
|
@ -83,7 +83,7 @@
|
||||||
|
|
||||||
/* 64 */
|
/* 64 */
|
||||||
#define TEGRA124_CLK_UARTD 65
|
#define TEGRA124_CLK_UARTD 65
|
||||||
#define TEGRA124_CLK_UARTE 66
|
/* 66 */
|
||||||
#define TEGRA124_CLK_I2C3 67
|
#define TEGRA124_CLK_I2C3 67
|
||||||
#define TEGRA124_CLK_SBC4 68
|
#define TEGRA124_CLK_SBC4 68
|
||||||
#define TEGRA124_CLK_SDMMC3 69
|
#define TEGRA124_CLK_SDMMC3 69
|
||||||
|
@ -97,7 +97,7 @@
|
||||||
#define TEGRA124_CLK_TRACE 77
|
#define TEGRA124_CLK_TRACE 77
|
||||||
#define TEGRA124_CLK_SOC_THERM 78
|
#define TEGRA124_CLK_SOC_THERM 78
|
||||||
#define TEGRA124_CLK_DTV 79
|
#define TEGRA124_CLK_DTV 79
|
||||||
#define TEGRA124_CLK_NDSPEED 80
|
/* 80 */
|
||||||
#define TEGRA124_CLK_I2CSLOW 81
|
#define TEGRA124_CLK_I2CSLOW 81
|
||||||
#define TEGRA124_CLK_DSIB 82
|
#define TEGRA124_CLK_DSIB 82
|
||||||
#define TEGRA124_CLK_TSEC 83
|
#define TEGRA124_CLK_TSEC 83
|
||||||
|
|
Loading…
Reference in New Issue