MIPS, Perf-events: Work with the new PMU interface
This is the MIPS part of the following commits by Peter Zijlstra: -a4eaf7f146
perf: Rework the PMU methods Replace pmu::{enable,disable,start,stop,unthrottle} with pmu::{add,del,start,stop}, all of which take a flags argument. The new interface extends the capability to stop a counter while keeping it scheduled on the PMU. We replace the throttled state with the generic stopped state. This also allows us to efficiently stop/start counters over certain code paths (like IRQ handlers). It also allows scheduling a counter without it starting, allowing for a generic frozen state (useful for rotating stopped counters). The stopped state is implemented in two different ways, depending on how the architecture implemented the throttled state: 1) We disable the counter: a) the pmu has per-counter enable bits, we flip that b) we program a NOP event, preserving the counter state 2) We store the counter state and ignore all read/overflow events For MIPSXX, the stopped state is implemented in the way of 1.b as above. -33696fc0d1
perf: Per PMU disable Changes perf_disable() into perf_pmu_disable(). -24cd7f54a0
perf: Reduce perf_disable() usage Since the current perf_disable() usage is only an optimization, remove it for now. This eases the removal of the __weak hw_perf_enable() interface. -b0a873ebbf
perf: Register PMU implementations Simple registration interface for struct pmu, this provides the infrastructure for removing all the weak functions. -51b0fe3954
perf: Deconstify struct pmu sed -ie 's/const struct pmu\>/struct pmu/g' `git grep -l "const struct pmu\>"` Reported-by: Wu Zhangjin <wuzhangjin@gmail.com> Acked-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: a.p.zijlstra@chello.nl To: fweisbec@gmail.com To: will.deacon@arm.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: wuzhangjin@gmail.com Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: dengcheng.zhu@gmail.com Cc: matt@console-pimps.org Cc: sshtylyov@mvista.com Cc: ddaney@caviumnetworks.com Patchwork: http://patchwork.linux-mips.org/patch/2012/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
parent
91f017372a
commit
404ff63840
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@ -161,41 +161,6 @@ mipspmu_event_set_period(struct perf_event *event,
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return ret;
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}
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static int mipspmu_enable(struct perf_event *event)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx;
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int err = 0;
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/* To look for a free counter for this event. */
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idx = mipspmu->alloc_counter(cpuc, hwc);
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if (idx < 0) {
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err = idx;
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goto out;
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}
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/*
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* If there is an event in the counter we are going to use then
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* make sure it is disabled.
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*/
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event->hw.idx = idx;
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mipspmu->disable_event(idx);
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cpuc->events[idx] = event;
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/* Set the period for the event. */
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mipspmu_event_set_period(event, hwc, idx);
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/* Enable the event. */
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mipspmu->enable_event(hwc, idx);
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/* Propagate our changes to the userspace mapping. */
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perf_event_update_userpage(event);
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out:
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return err;
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}
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static void mipspmu_event_update(struct perf_event *event,
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struct hw_perf_event *hwc,
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int idx)
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@ -231,34 +196,92 @@ again:
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return;
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}
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static void mipspmu_disable(struct perf_event *event)
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static void mipspmu_start(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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if (!mipspmu)
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return;
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if (flags & PERF_EF_RELOAD)
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WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
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hwc->state = 0;
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/* Set the period for the event. */
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mipspmu_event_set_period(event, hwc, hwc->idx);
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/* Enable the event. */
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mipspmu->enable_event(hwc, hwc->idx);
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}
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static void mipspmu_stop(struct perf_event *event, int flags)
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{
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struct hw_perf_event *hwc = &event->hw;
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if (!mipspmu)
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return;
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if (!(hwc->state & PERF_HES_STOPPED)) {
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/* We are working on a local event. */
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mipspmu->disable_event(hwc->idx);
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barrier();
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mipspmu_event_update(event, hwc, hwc->idx);
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hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
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}
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}
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static int mipspmu_add(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx;
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int err = 0;
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perf_pmu_disable(event->pmu);
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/* To look for a free counter for this event. */
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idx = mipspmu->alloc_counter(cpuc, hwc);
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if (idx < 0) {
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err = idx;
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goto out;
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}
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/*
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* If there is an event in the counter we are going to use then
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* make sure it is disabled.
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*/
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event->hw.idx = idx;
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mipspmu->disable_event(idx);
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cpuc->events[idx] = event;
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hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
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if (flags & PERF_EF_START)
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mipspmu_start(event, PERF_EF_RELOAD);
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/* Propagate our changes to the userspace mapping. */
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perf_event_update_userpage(event);
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out:
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perf_pmu_enable(event->pmu);
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return err;
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}
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static void mipspmu_del(struct perf_event *event, int flags)
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{
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struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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WARN_ON(idx < 0 || idx >= mipspmu->num_counters);
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/* We are working on a local event. */
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mipspmu->disable_event(idx);
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barrier();
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mipspmu_event_update(event, hwc, idx);
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mipspmu_stop(event, PERF_EF_UPDATE);
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cpuc->events[idx] = NULL;
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clear_bit(idx, cpuc->used_mask);
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perf_event_update_userpage(event);
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}
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static void mipspmu_unthrottle(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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mipspmu->enable_event(hwc, hwc->idx);
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}
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static void mipspmu_read(struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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@ -270,12 +293,17 @@ static void mipspmu_read(struct perf_event *event)
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mipspmu_event_update(event, hwc, hwc->idx);
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}
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static struct pmu pmu = {
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.enable = mipspmu_enable,
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.disable = mipspmu_disable,
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.unthrottle = mipspmu_unthrottle,
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.read = mipspmu_read,
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};
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static void mipspmu_enable(struct pmu *pmu)
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{
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if (mipspmu)
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mipspmu->start();
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}
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static void mipspmu_disable(struct pmu *pmu)
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{
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if (mipspmu)
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mipspmu->stop();
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}
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static atomic_t active_events = ATOMIC_INIT(0);
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static DEFINE_MUTEX(pmu_reserve_mutex);
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@ -318,6 +346,82 @@ static void mipspmu_free_irq(void)
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perf_irq = save_perf_irq;
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}
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/*
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* mipsxx/rm9000/loongson2 have different performance counters, they have
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* specific low-level init routines.
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*/
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static void reset_counters(void *arg);
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static int __hw_perf_event_init(struct perf_event *event);
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static void hw_perf_event_destroy(struct perf_event *event)
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{
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if (atomic_dec_and_mutex_lock(&active_events,
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&pmu_reserve_mutex)) {
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/*
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* We must not call the destroy function with interrupts
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* disabled.
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*/
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on_each_cpu(reset_counters,
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(void *)(long)mipspmu->num_counters, 1);
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mipspmu_free_irq();
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mutex_unlock(&pmu_reserve_mutex);
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}
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}
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static int mipspmu_event_init(struct perf_event *event)
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{
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int err = 0;
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switch (event->attr.type) {
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case PERF_TYPE_RAW:
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case PERF_TYPE_HARDWARE:
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case PERF_TYPE_HW_CACHE:
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break;
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default:
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return -ENOENT;
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}
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if (!mipspmu || event->cpu >= nr_cpumask_bits ||
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(event->cpu >= 0 && !cpu_online(event->cpu)))
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return -ENODEV;
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if (!atomic_inc_not_zero(&active_events)) {
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if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) {
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atomic_dec(&active_events);
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return -ENOSPC;
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}
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mutex_lock(&pmu_reserve_mutex);
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if (atomic_read(&active_events) == 0)
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err = mipspmu_get_irq();
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if (!err)
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atomic_inc(&active_events);
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mutex_unlock(&pmu_reserve_mutex);
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}
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if (err)
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return err;
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err = __hw_perf_event_init(event);
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if (err)
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hw_perf_event_destroy(event);
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return err;
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}
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static struct pmu pmu = {
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.pmu_enable = mipspmu_enable,
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.pmu_disable = mipspmu_disable,
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.event_init = mipspmu_event_init,
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.add = mipspmu_add,
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.del = mipspmu_del,
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.start = mipspmu_start,
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.stop = mipspmu_stop,
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.read = mipspmu_read,
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};
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static inline unsigned int
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mipspmu_perf_event_encode(const struct mips_perf_event *pev)
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{
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@ -409,73 +513,6 @@ static int validate_group(struct perf_event *event)
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return 0;
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}
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/*
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* mipsxx/rm9000/loongson2 have different performance counters, they have
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* specific low-level init routines.
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*/
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static void reset_counters(void *arg);
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static int __hw_perf_event_init(struct perf_event *event);
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static void hw_perf_event_destroy(struct perf_event *event)
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{
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if (atomic_dec_and_mutex_lock(&active_events,
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&pmu_reserve_mutex)) {
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/*
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* We must not call the destroy function with interrupts
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* disabled.
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*/
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on_each_cpu(reset_counters,
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(void *)(long)mipspmu->num_counters, 1);
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mipspmu_free_irq();
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mutex_unlock(&pmu_reserve_mutex);
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}
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}
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const struct pmu *hw_perf_event_init(struct perf_event *event)
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{
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int err = 0;
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if (!mipspmu || event->cpu >= nr_cpumask_bits ||
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(event->cpu >= 0 && !cpu_online(event->cpu)))
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return ERR_PTR(-ENODEV);
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if (!atomic_inc_not_zero(&active_events)) {
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if (atomic_read(&active_events) > MIPS_MAX_HWEVENTS) {
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atomic_dec(&active_events);
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return ERR_PTR(-ENOSPC);
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}
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mutex_lock(&pmu_reserve_mutex);
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if (atomic_read(&active_events) == 0)
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err = mipspmu_get_irq();
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if (!err)
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atomic_inc(&active_events);
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mutex_unlock(&pmu_reserve_mutex);
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}
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if (err)
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return ERR_PTR(err);
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err = __hw_perf_event_init(event);
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if (err)
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hw_perf_event_destroy(event);
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return err ? ERR_PTR(err) : &pmu;
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}
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void hw_perf_enable(void)
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{
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if (mipspmu)
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mipspmu->start();
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}
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void hw_perf_disable(void)
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{
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if (mipspmu)
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mipspmu->stop();
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}
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/* This is needed by specific irq handlers in perf_event_*.c */
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static void
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handle_associated_event(struct cpu_hw_events *cpuc,
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@ -1045,6 +1045,8 @@ init_hw_perf_events(void)
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"CPU, irq %d%s\n", mipspmu->name, counters, irq,
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irq < 0 ? " (share with timer interrupt)" : "");
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perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
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return 0;
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}
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early_initcall(init_hw_perf_events);
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