[PATCH] x86-64: x86_64 make NMI use PERFCTR1 for architectural perfmon (take 2)
Hello, This patch against 2.6.20-git14 makes the NMI watchdog use PERFSEL1/PERFCTR1 instead of PERFSEL0/PERFCTR0 on processors supporting Intel architectural perfmon, such as Intel Core 2. Although all PMU events can work on both counters, the Precise Event-Based Sampling (PEBS) requires that the event be in PERFCTR0 to work correctly (see section 18.14.4.1 in the IA32 SDM Vol 3b). This versions has 3 chunks compared to previous where we had missed on check. Changelog: - make the x86-64 NMI watchdog use PERFSEL1/PERFCTR1 instead of PERFSEL0/PERFCTR0 on processors supporting the Intel architectural perfmon (e.g. Core 2 Duo). This allows PEBS to work when the NMI watchdog is active. signed-off-by: stephane eranian <eranian@hpl.hp.com> Signed-off-by: Andi Kleen <ak@suse.de>
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@ -348,7 +348,7 @@ int __init check_nmi_watchdog (void)
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struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
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nmi_hz = 1;
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if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0)
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if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR1)
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nmi_hz = adjust_for_32bit_ctr(nmi_hz);
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}
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@ -713,8 +713,8 @@ static int setup_intel_arch_watchdog(void)
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(ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
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goto fail;
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perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
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evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0;
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perfctr_msr = MSR_ARCH_PERFMON_PERFCTR1;
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evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL1;
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if (!__reserve_perfctr_nmi(-1, perfctr_msr))
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goto fail;
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@ -958,7 +958,7 @@ int __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
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/* start the cycle over again */
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wrmsrl(wd->perfctr_msr,
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-((u64)cpu_khz * 1000 / nmi_hz));
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} else if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
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} else if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR1) {
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/*
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* ArchPerfom/Core Duo needs to re-unmask
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* the apic vector
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