net: fec: move fec_enet_private to header file
A new file fec_ptp.c will use fec_enet_private to support 1588 PTP move such structure to common header file fec.h Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Frank Li
David S. Miller
parent
23ea5a9637
commit
405f257f46
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@ -140,21 +140,6 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
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#endif
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#endif /* CONFIG_M5272 */
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/* The number of Tx and Rx buffers. These are allocated from the page
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* pool. The code may assume these are power of two, so it it best
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* to keep them that size.
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* We don't need to allocate pages for the transmitter. We just use
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* the skbuffer directly.
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*/
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#define FEC_ENET_RX_PAGES 8
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#define FEC_ENET_RX_FRSIZE 2048
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#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
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#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
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#define FEC_ENET_TX_FRSIZE 2048
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#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
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#define TX_RING_SIZE 16 /* Must be power of two */
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#define TX_RING_MOD_MASK 15 /* for this to work */
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#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
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#error "FEC: descriptor ring size constants too large"
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#endif
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@ -179,9 +164,6 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
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#define PKT_MINBUF_SIZE 64
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#define PKT_MAXBLR_SIZE 1520
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/* This device has up to three irqs on some platforms */
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#define FEC_IRQ_NUM 3
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/*
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* The 5270/5271/5280/5282/532x RX control register also contains maximum frame
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* size bits. Other FEC hardware does not, so we need to take that into
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@ -194,61 +176,6 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
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#define OPT_FRAME_SIZE 0
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#endif
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/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
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* tx_bd_base always point to the base of the buffer descriptors. The
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* cur_rx and cur_tx point to the currently available buffer.
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* The dirty_tx tracks the current buffer that is being sent by the
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* controller. The cur_tx and dirty_tx are equal under both completely
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* empty and completely full conditions. The empty/ready indicator in
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* the buffer descriptor determines the actual condition.
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*/
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struct fec_enet_private {
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/* Hardware registers of the FEC device */
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void __iomem *hwp;
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struct net_device *netdev;
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struct clk *clk_ipg;
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struct clk *clk_ahb;
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/* The saved address of a sent-in-place packet/buffer, for skfree(). */
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unsigned char *tx_bounce[TX_RING_SIZE];
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struct sk_buff* tx_skbuff[TX_RING_SIZE];
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struct sk_buff* rx_skbuff[RX_RING_SIZE];
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ushort skb_cur;
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ushort skb_dirty;
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/* CPM dual port RAM relative addresses */
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dma_addr_t bd_dma;
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/* Address of Rx and Tx buffers */
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struct bufdesc *rx_bd_base;
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struct bufdesc *tx_bd_base;
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/* The next free ring entry */
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struct bufdesc *cur_rx, *cur_tx;
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/* The ring entries to be free()ed */
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struct bufdesc *dirty_tx;
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uint tx_full;
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/* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
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spinlock_t hw_lock;
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struct platform_device *pdev;
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int opened;
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int dev_id;
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/* Phylib and MDIO interface */
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struct mii_bus *mii_bus;
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struct phy_device *phy_dev;
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int mii_timeout;
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uint phy_speed;
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phy_interface_t phy_interface;
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int link;
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int full_duplex;
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struct completion mdio_done;
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int irq[FEC_IRQ_NUM];
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};
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/* FEC MII MMFR bits definition */
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#define FEC_MMFR_ST (1 << 30)
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#define FEC_MMFR_OP_READ (2 << 28)
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@ -147,6 +147,87 @@ struct bufdesc {
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#define BD_ENET_TX_CSL ((ushort)0x0001)
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#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
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/*enhanced buffer desciptor control/status used by Ethernet transmit*/
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#define BD_ENET_TX_INT 0x40000000
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#define BD_ENET_TX_TS 0x20000000
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/* This device has up to three irqs on some platforms */
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#define FEC_IRQ_NUM 3
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/* The number of Tx and Rx buffers. These are allocated from the page
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* pool. The code may assume these are power of two, so it it best
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* to keep them that size.
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* We don't need to allocate pages for the transmitter. We just use
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* the skbuffer directly.
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*/
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#define FEC_ENET_RX_PAGES 8
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#define FEC_ENET_RX_FRSIZE 2048
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#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
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#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
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#define FEC_ENET_TX_FRSIZE 2048
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#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
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#define TX_RING_SIZE 16 /* Must be power of two */
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#define TX_RING_MOD_MASK 15 /* for this to work */
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#define BD_ENET_RX_INT 0x00800000
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#define BD_ENET_RX_PTP ((ushort)0x0400)
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/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
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* tx_bd_base always point to the base of the buffer descriptors. The
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* cur_rx and cur_tx point to the currently available buffer.
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* The dirty_tx tracks the current buffer that is being sent by the
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* controller. The cur_tx and dirty_tx are equal under both completely
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* empty and completely full conditions. The empty/ready indicator in
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* the buffer descriptor determines the actual condition.
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*/
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struct fec_enet_private {
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/* Hardware registers of the FEC device */
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void __iomem *hwp;
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struct net_device *netdev;
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struct clk *clk_ipg;
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struct clk *clk_ahb;
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/* The saved address of a sent-in-place packet/buffer, for skfree(). */
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unsigned char *tx_bounce[TX_RING_SIZE];
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struct sk_buff *tx_skbuff[TX_RING_SIZE];
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struct sk_buff *rx_skbuff[RX_RING_SIZE];
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ushort skb_cur;
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ushort skb_dirty;
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/* CPM dual port RAM relative addresses */
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dma_addr_t bd_dma;
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/* Address of Rx and Tx buffers */
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struct bufdesc *rx_bd_base;
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struct bufdesc *tx_bd_base;
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/* The next free ring entry */
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struct bufdesc *cur_rx, *cur_tx;
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/* The ring entries to be free()ed */
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struct bufdesc *dirty_tx;
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uint tx_full;
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/* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
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spinlock_t hw_lock;
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struct platform_device *pdev;
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int opened;
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int dev_id;
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/* Phylib and MDIO interface */
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struct mii_bus *mii_bus;
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struct phy_device *phy_dev;
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int mii_timeout;
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uint phy_speed;
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phy_interface_t phy_interface;
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int link;
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int full_duplex;
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struct completion mdio_done;
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int irq[FEC_IRQ_NUM];
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};
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/****************************************************************************/
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#endif /* FEC_H */
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