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ARM: SoC fixes for 4.18-rc 

- A fix for OMAP5 and DRA7 to make the branch predictor hardening
    settings take proper effect on secondary cores
  - Disable USB OTG on am3517 since current driver isn't working
  - Fix thermal sensor register settings on Armada 38x
  - Fix suspend/resume IRQs on pxa3xx
 -----BEGIN PGP SIGNATURE-----
 
 iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAltK4qkPHG9sb2ZAbGl4
 b20ubmV0AAoJEIwa5zzehBx3pS0P/i4cTb8pESaYltSiVXePn8Ii6LJa0zxKZ4SK
 Yb2jBAFliG319HX2uFNsu42DfhgfdjBlhjkK/5pyOmMyo/t6YLDmC+qmeMhSCwbi
 913eZav3UxdegJWFauU8P/khyxPD2nCeDqETzhANuzEB6+ayhi+cgIjpnx+8JLyK
 0q5cifBEdRbZO9UGG+IFqt3TLpeAuCIbWLzTCOmdEQ706Zw2TPzzR6RTBt+kfupA
 j7Z0pg1yzK40TWyv1ZOyYC7yw2S+9cuT4gdXE/DUgyT4dGlE/deE9iT9D/s8fgAL
 Fser9jLbC5rbNQ1MnLRuGtbidvpiq2iCyf7G/FTJD3eoe1AGeaVooa+Jsz9LgEN6
 JFJ/sxD8c6PSAJ8t9Dmv9eFOhia0V8XzjtEinWJ2E8F0cgMLxG1y4Ek0cnvaRgZG
 2VMfNLIN0iQvYj1FHLJEYkOFEJ+3szJYC8Ejr5RdMUAShUHzqTw1XB4D9IPljJm9
 fvrk20LmHRosvcrtqgUNRtMdfEvnTaUMB427ywYyH6Mz75L30CyE7FWohtoL+Qm3
 mjB/qQ+c4dWj0YHKLSRhG40hP4Bzo/ljeuzgLs3/crRh12qBHxhE73rUvCpctCyA
 VBrU4F+I/a8cJPDqLYtwK8RuMFcYQTWogF3OVWIa+xlWRINYFO8hTgHETSHUtkQY
 TGpglcH0
 =lmky
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:

 - A fix for OMAP5 and DRA7 to make the branch predictor hardening
   settings take proper effect on secondary cores

 - Disable USB OTG on am3517 since current driver isn't working

 - Fix thermal sensor register settings on Armada 38x

 - Fix suspend/resume IRQs on pxa3xx

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: dts: am3517.dtsi:  Disable reference to OMAP3 OTG controller
  ARM: DRA7/OMAP5: Enable ACTLR[0] (Enable invalidates of BTB) for secondary cores
  ARM: pxa: irq: fix handling of ICMR registers in suspend/resume
  ARM: dts: armada-38x: use the new thermal binding
This commit is contained in:
Linus Torvalds 2018-07-15 09:49:21 -07:00
parent 37b5dca289 13e66ceea1
commit 41b55d23ee
4 changed files with 49 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/boot/dts/am3517.dtsi
View File

@ -91,6 +91,11 @@
};
};
/* Table Table 5-79 of the TRM shows 480ab000 is reserved */
&usb_otg_hs {
status = "disabled";
};
&iva {
status = "disabled";
};

2
arch/arm/boot/dts/armada-38x.dtsi
View File

@ -547,7 +547,7 @@
thermal: thermal@e8078 {
compatible = "marvell,armada380-thermal";
reg = <0xe4078 0x4>, <0xe4074 0x4>;
reg = <0xe4078 0x4>, <0xe4070 0x8>;
status = "okay";
};

41
arch/arm/mach-omap2/omap-smp.c
View File

@ -109,6 +109,45 @@ void omap5_erratum_workaround_801819(void)
static inline void omap5_erratum_workaround_801819(void) { }
#endif
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
/*
* Configure ACR and enable ACTLR[0] (Enable invalidates of BTB with
* ICIALLU) to activate the workaround for secondary Core.
* NOTE: it is assumed that the primary core's configuration is done
* by the boot loader (kernel will detect a misconfiguration and complain
* if this is not done).
*
* In General Purpose(GP) devices, ACR bit settings can only be done
* by ROM code in "secure world" using the smc call and there is no
* option to update the "firmware" on such devices. This also works for
* High security(HS) devices, as a backup option in case the
* "update" is not done in the "security firmware".
*/
static void omap5_secondary_harden_predictor(void)
{
u32 acr, acr_mask;
asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
/*
* ACTLR[0] (Enable invalidates of BTB with ICIALLU)
*/
acr_mask = BIT(0);
/* Do we already have it done.. if yes, skip expensive smc */
if ((acr & acr_mask) == acr_mask)
return;
acr |= acr_mask;
omap_smc1(OMAP5_DRA7_MON_SET_ACR_INDEX, acr);
pr_debug("%s: ARM ACR setup for CVE_2017_5715 applied on CPU%d\n",
__func__, smp_processor_id());
}
#else
static inline void omap5_secondary_harden_predictor(void) { }
#endif
static void omap4_secondary_init(unsigned int cpu)
{
/*
@ -131,6 +170,8 @@ static void omap4_secondary_init(unsigned int cpu)
set_cntfreq();
/* Configure ACR to disable streaming WA for 801819 */
omap5_erratum_workaround_801819();
/* Enable ACR to allow for ICUALLU workaround */
omap5_secondary_harden_predictor();
}
/*

4
arch/arm/mach-pxa/irq.c
View File

@ -185,7 +185,7 @@ static int pxa_irq_suspend(void)
{
int i;
for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) {
void __iomem *base = irq_base(i);
saved_icmr[i] = __raw_readl(base + ICMR);
@ -204,7 +204,7 @@ static void pxa_irq_resume(void)
{
int i;
for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
for (i = 0; i < DIV_ROUND_UP(pxa_internal_irq_nr, 32); i++) {
void __iomem *base = irq_base(i);
__raw_writel(saved_icmr[i], base + ICMR);