clocksource: sh_mtu2: Split channel fields from sh_mtu2_priv
Create a new sh_mtu2_channel structure to hold the channel-specific fields in preparation for multiple channels per device support. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Wolfram Sang <wsa@sang-engineering.com>
This commit is contained in:
Laurent Pinchart
parent
f92d62f539
commit
42752cc619
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@ -34,12 +34,21 @@
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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struct sh_mtu2_priv;
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struct sh_mtu2_channel {
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struct sh_mtu2_priv *mtu;
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int irq;
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struct clock_event_device ced;
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};
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struct sh_mtu2_priv {
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struct platform_device *pdev;
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void __iomem *mapbase;
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struct clk *clk;
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int irq;
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struct platform_device *pdev;
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struct clock_event_device ced;
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struct sh_mtu2_channel channel;
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};
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static DEFINE_RAW_SPINLOCK(sh_mtu2_lock);
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@ -63,10 +72,10 @@ static unsigned long mtu2_reg_offs[] = {
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[TGR] = 8,
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};
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static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
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static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr)
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{
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struct sh_timer_config *cfg = p->pdev->dev.platform_data;
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void __iomem *base = p->mapbase;
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struct sh_timer_config *cfg = ch->mtu->pdev->dev.platform_data;
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void __iomem *base = ch->mtu->mapbase;
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unsigned long offs;
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if (reg_nr == TSTR)
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@ -80,11 +89,11 @@ static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
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return ioread8(base + offs);
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}
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static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
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static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr,
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unsigned long value)
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{
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struct sh_timer_config *cfg = p->pdev->dev.platform_data;
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void __iomem *base = p->mapbase;
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struct sh_timer_config *cfg = ch->mtu->pdev->dev.platform_data;
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void __iomem *base = ch->mtu->mapbase;
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unsigned long offs;
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if (reg_nr == TSTR) {
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@ -100,100 +109,100 @@ static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
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iowrite8(value, base + offs);
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}
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static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
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static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)
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{
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struct sh_timer_config *cfg = p->pdev->dev.platform_data;
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struct sh_timer_config *cfg = ch->mtu->pdev->dev.platform_data;
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unsigned long flags, value;
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/* start stop register shared by multiple timer channels */
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raw_spin_lock_irqsave(&sh_mtu2_lock, flags);
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value = sh_mtu2_read(p, TSTR);
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value = sh_mtu2_read(ch, TSTR);
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if (start)
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value |= 1 << cfg->timer_bit;
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else
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value &= ~(1 << cfg->timer_bit);
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sh_mtu2_write(p, TSTR, value);
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sh_mtu2_write(ch, TSTR, value);
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raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags);
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}
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static int sh_mtu2_enable(struct sh_mtu2_priv *p)
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static int sh_mtu2_enable(struct sh_mtu2_channel *ch)
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{
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unsigned long periodic;
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unsigned long rate;
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int ret;
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pm_runtime_get_sync(&p->pdev->dev);
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dev_pm_syscore_device(&p->pdev->dev, true);
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pm_runtime_get_sync(&ch->mtu->pdev->dev);
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dev_pm_syscore_device(&ch->mtu->pdev->dev, true);
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/* enable clock */
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ret = clk_enable(p->clk);
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ret = clk_enable(ch->mtu->clk);
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if (ret) {
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dev_err(&p->pdev->dev, "cannot enable clock\n");
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dev_err(&ch->mtu->pdev->dev, "cannot enable clock\n");
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return ret;
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}
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/* make sure channel is disabled */
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sh_mtu2_start_stop_ch(p, 0);
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sh_mtu2_start_stop_ch(ch, 0);
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rate = clk_get_rate(p->clk) / 64;
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rate = clk_get_rate(ch->mtu->clk) / 64;
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periodic = (rate + HZ/2) / HZ;
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/* "Periodic Counter Operation" */
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sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
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sh_mtu2_write(p, TIOR, 0);
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sh_mtu2_write(p, TGR, periodic);
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sh_mtu2_write(p, TCNT, 0);
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sh_mtu2_write(p, TMDR, 0);
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sh_mtu2_write(p, TIER, 0x01);
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sh_mtu2_write(ch, TCR, 0x23); /* TGRA clear, divide clock by 64 */
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sh_mtu2_write(ch, TIOR, 0);
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sh_mtu2_write(ch, TGR, periodic);
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sh_mtu2_write(ch, TCNT, 0);
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sh_mtu2_write(ch, TMDR, 0);
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sh_mtu2_write(ch, TIER, 0x01);
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/* enable channel */
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sh_mtu2_start_stop_ch(p, 1);
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sh_mtu2_start_stop_ch(ch, 1);
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return 0;
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}
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static void sh_mtu2_disable(struct sh_mtu2_priv *p)
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static void sh_mtu2_disable(struct sh_mtu2_channel *ch)
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{
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/* disable channel */
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sh_mtu2_start_stop_ch(p, 0);
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sh_mtu2_start_stop_ch(ch, 0);
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/* stop clock */
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clk_disable(p->clk);
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clk_disable(ch->mtu->clk);
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dev_pm_syscore_device(&p->pdev->dev, false);
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pm_runtime_put(&p->pdev->dev);
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dev_pm_syscore_device(&ch->mtu->pdev->dev, false);
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pm_runtime_put(&ch->mtu->pdev->dev);
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}
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static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
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{
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struct sh_mtu2_priv *p = dev_id;
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struct sh_mtu2_channel *ch = dev_id;
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/* acknowledge interrupt */
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sh_mtu2_read(p, TSR);
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sh_mtu2_write(p, TSR, 0xfe);
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sh_mtu2_read(ch, TSR);
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sh_mtu2_write(ch, TSR, 0xfe);
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/* notify clockevent layer */
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p->ced.event_handler(&p->ced);
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ch->ced.event_handler(&ch->ced);
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return IRQ_HANDLED;
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}
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static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced)
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static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced)
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{
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return container_of(ced, struct sh_mtu2_priv, ced);
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return container_of(ced, struct sh_mtu2_channel, ced);
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}
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static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
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struct clock_event_device *ced)
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{
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struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced);
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struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);
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int disabled = 0;
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/* deal with old setting first */
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switch (ced->mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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sh_mtu2_disable(p);
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sh_mtu2_disable(ch);
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disabled = 1;
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break;
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default:
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@ -202,12 +211,13 @@ static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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dev_info(&p->pdev->dev, "used for periodic clock events\n");
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sh_mtu2_enable(p);
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dev_info(&ch->mtu->pdev->dev,
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"used for periodic clock events\n");
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sh_mtu2_enable(ch);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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if (!disabled)
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sh_mtu2_disable(p);
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sh_mtu2_disable(ch);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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default:
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@ -217,18 +227,18 @@ static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
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static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced)
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{
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pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->pdev->dev);
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pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
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}
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static void sh_mtu2_clock_event_resume(struct clock_event_device *ced)
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{
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pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->pdev->dev);
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pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
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}
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static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
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static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch,
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char *name, unsigned long rating)
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{
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struct clock_event_device *ced = &p->ced;
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struct clock_event_device *ced = &ch->ced;
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int ret;
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memset(ced, 0, sizeof(*ced));
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@ -241,23 +251,24 @@ static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
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ced->suspend = sh_mtu2_clock_event_suspend;
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ced->resume = sh_mtu2_clock_event_resume;
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dev_info(&p->pdev->dev, "used for clock events\n");
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dev_info(&ch->mtu->pdev->dev, "used for clock events\n");
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clockevents_register_device(ced);
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ret = request_irq(p->irq, sh_mtu2_interrupt,
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ret = request_irq(ch->irq, sh_mtu2_interrupt,
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IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
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dev_name(&p->pdev->dev), p);
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dev_name(&ch->mtu->pdev->dev), ch);
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if (ret) {
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dev_err(&p->pdev->dev, "failed to request irq %d\n", p->irq);
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dev_err(&ch->mtu->pdev->dev, "failed to request irq %d\n",
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ch->irq);
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return;
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}
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}
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static int sh_mtu2_register(struct sh_mtu2_priv *p, char *name,
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static int sh_mtu2_register(struct sh_mtu2_channel *ch, char *name,
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unsigned long clockevent_rating)
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{
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if (clockevent_rating)
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sh_mtu2_register_clockevent(p, name, clockevent_rating);
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sh_mtu2_register_clockevent(ch, name, clockevent_rating);
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return 0;
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}
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@ -285,8 +296,8 @@ static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
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goto err0;
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}
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p->irq = platform_get_irq(p->pdev, 0);
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if (p->irq < 0) {
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p->channel.irq = platform_get_irq(p->pdev, 0);
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if (p->channel.irq < 0) {
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dev_err(&p->pdev->dev, "failed to get irq\n");
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goto err0;
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}
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@ -310,7 +321,9 @@ static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
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if (ret < 0)
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goto err2;
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ret = sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev),
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p->channel.mtu = p;
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ret = sh_mtu2_register(&p->channel, (char *)dev_name(&p->pdev->dev),
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cfg->clockevent_rating);
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if (ret < 0)
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goto err3;
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