sis5513: factor out UDMA programming code
* Factor out UDMA programming code from sis_set_dma_mode() to per chipset family helpers: sis_{ata33,ata133}_program_udma_timings(). * Add sis_program_udma_timings() helper. * Remove unneeded casts to 'unsigned long'. * Minor cleanups. There should be no functionality changes caused by this patch. Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
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@ -305,11 +305,52 @@ static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
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sis_program_timings(drive, XFER_PIO_0 + pio);
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}
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static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode)
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{
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struct pci_dev *dev = drive->hwif->pci_dev;
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u32 regdw = 0;
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u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
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pci_read_config_dword(dev, drive_pci, ®dw);
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regdw |= 0x04;
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regdw &= 0xfffff00f;
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/* check if ATA133 enable */
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clk = (regdw & 0x08) ? ATA_133 : ATA_100;
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idx = mode - XFER_UDMA_0;
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regdw |= cycle_time_value[clk][idx] << 4;
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regdw |= cvs_time_value[clk][idx] << 8;
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pci_write_config_dword(dev, drive_pci, regdw);
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}
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static void sis_ata33_program_udma_timings(ide_drive_t *drive, const u8 mode)
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{
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struct pci_dev *dev = drive->hwif->pci_dev;
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u8 drive_pci = 0x40 + drive->dn * 2, reg = 0, i = chipset_family;
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pci_read_config_byte(dev, drive_pci + 1, ®);
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/* force the UDMA bit on if we want to use UDMA */
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reg |= 0x80;
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/* clean reg cycle time bits */
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reg &= ~((0xff >> (8 - cycle_time_range[i])) << cycle_time_offset[i]);
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/* set reg cycle time bits */
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reg |= cycle_time_value[i][mode - XFER_UDMA_0] << cycle_time_offset[i];
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pci_write_config_byte(dev, drive_pci + 1, reg);
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}
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static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode)
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{
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if (chipset_family >= ATA_133) /* ATA_133 */
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sis_ata133_program_udma_timings(drive, mode);
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else /* ATA_33/66/100a/100/133a */
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sis_ata33_program_udma_timings(drive, mode);
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}
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static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = hwif->pci_dev;
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/* Config chip for mode */
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switch(speed) {
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case XFER_UDMA_6:
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@ -319,36 +360,7 @@ static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
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case XFER_UDMA_2:
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case XFER_UDMA_1:
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case XFER_UDMA_0:
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if (chipset_family >= ATA_133) {
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u32 regdw = 0;
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u8 drive_pci = sis_ata133_get_base(drive);
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pci_read_config_dword(dev, drive_pci, ®dw);
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regdw |= 0x04;
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regdw &= 0xfffff00f;
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/* check if ATA133 enable */
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if (regdw & 0x08) {
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regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4;
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regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8;
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} else {
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regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4;
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regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8;
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}
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pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
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} else {
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u8 drive_pci = 0x40 + drive->dn * 2, reg = 0;
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pci_read_config_byte(dev, drive_pci+1, ®);
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/* Force the UDMA bit on if we want to use UDMA */
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reg |= 0x80;
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/* clean reg cycle time bits */
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reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family]))
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<< cycle_time_offset[chipset_family]);
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/* set reg cycle time bits */
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reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0]
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<< cycle_time_offset[chipset_family];
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pci_write_config_byte(dev, drive_pci+1, reg);
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}
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sis_program_udma_timings(drive, speed);
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break;
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case XFER_MW_DMA_2:
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case XFER_MW_DMA_1:
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