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drm/radeon/cik: Add tiling mode index for 1D tiled depth/stencil surfaces 

CIK uses a different index for 1D DST surfaces compared to SI.  Expose
the new index so libdrm_radeon can use it properly for userspace
drivers.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Michel Dänzer 2013-09-18 18:23:51 +02:00 committed by Alex Deucher
parent a537314e0b
commit 42baf21d91
1 changed files with 2 additions and 0 deletions
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2
include/uapi/drm/radeon_drm.h
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@ -1007,4 +1007,6 @@ struct drm_radeon_info {
#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
#define CIK_TILE_MODE_DEPTH_STENCIL_1D 5
#endif