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A few fixes for code that came in during the merge window or 

that started getting exercised differently this time around:
 
  - Select regmap MMIO kconfig in spreadtrum driver to avoid compile
    errors
  - Complete kerneldoc on devm_clk_bulk_get_optional()
  - Register an essential clk earlier on mediatek mt8183 SoCs so
    the clocksource driver can use it
  - Fix divisor math in the at91 driver
  - Plug a race in Renesas reset control logic
 -----BEGIN PGP SIGNATURE-----
 
 iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl1DH5oRHHNib3lkQGtl
 cm5lbC5vcmcACgkQrQKIl8bklSXEiRAAlKgH3gBvg9gtwRuK11qeW/yJYA9/rdF6
 nRxMQDq3AA/BktyHpnfDBOHbHs7zmwaeg/bk0x/Ex4+mgdCRe8+X9PJxlgSovenY
 8Ky0CAijGxY2Mud/R0YPR2+QVCLYON8cp9SryrWpfokZP4bMqZOKUE6vs2NbeYCa
 0iDneX9UUQhvGejEnhgKiuGtiRWPux3htxNlGaHkk/I/z1CvvsfGnxfbAPWN6ppl
 txiZDLvtYjGx4tHVWg+olXhyQAMg3JADS1MOx3AcDv7OO5UnfLzdLMp/NLVwqdor
 ZmbE2yTdzplGtuoh7waE7Mel6bm/gd94XHsX5S0gJU+ock2wWYoCMMkRGskSJFg3
 /Dn7ajNS0Z4xMmdyz+O3kBMB4zu8kiedT07nkwXm+bsFzGK4UEzY6Gn09JP9+m2P
 qSzxVLoO5Kg1M4yDIauOX6IyOC0VNgpftdZ4SGoCVqUrH3BYI804I6unbLOF5nad
 u4mL0v8Bfz/OuJxuvaFpWCYoowHMi7NOz9ipQRB2bS/QYCB9H6rjv8tT4xAw81w6
 P6DI0eG+QCjfHCEbe8W/KikLWSL52fnycwAAospkV+1AFFZ2735oJgb9KY4xY6Qd
 tMRLsVjOTnq3mu/PlHuilnyaNtH7OHxp47HoBdgg8kc8VEIsfY+Z7SsPMms228/u
 KBzPg709SIk=
 =tNyv
 -----END PGP SIGNATURE-----

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "A few fixes for code that came in during the merge window or that
  started getting exercised differently this time around:

   - Select regmap MMIO kconfig in spreadtrum driver to avoid compile
     errors

   - Complete kerneldoc on devm_clk_bulk_get_optional()

   - Register an essential clk earlier on mediatek mt8183 SoCs so the
     clocksource driver can use it

   - Fix divisor math in the at91 driver

   - Plug a race in Renesas reset control logic"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: renesas: cpg-mssr: Fix reset control race condition
  clk: sprd: Select REGMAP_MMIO to avoid compile errors
  clk: mediatek: mt8183: Register 13MHz clock earlier for clocksource
  clk: Add missing documentation of devm_clk_bulk_get_optional() argument
  clk: at91: generated: Truncate divisor to GENERATED_MAX_DIV + 1
This commit is contained in:
Linus Torvalds 2019-08-02 08:47:28 -07:00
parent 234172f6bb e1f1ae8002
commit 42d21900b3
5 changed files with 40 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/clk/at91/clk-generated.c
View File

@ -141,6 +141,8 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
continue;
div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
if (div > GENERATED_MAX_DIV + 1)
div = GENERATED_MAX_DIV + 1;
clk_generated_best_diff(req, parent, parent_rate, div,
&best_diff, &best_rate);

46
drivers/clk/mediatek/clk-mt8183.c
View File

@ -25,9 +25,11 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000),
};
static const struct mtk_fixed_factor top_early_divs[] = {
FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
};
static const struct mtk_fixed_factor top_divs[] = {
FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1,
2),
FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1,
2),
FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1,
@ -1148,37 +1150,57 @@ static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
}
static struct clk_onecell_data *top_clk_data;
static void clk_mt8183_top_init_early(struct device_node *node)
{
int i;
top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
for (i = 0; i < CLK_TOP_NR_CLK; i++)
top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
top_clk_data);
of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
}
CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen",
clk_mt8183_top_init_early);
static int clk_mt8183_top_probe(struct platform_device *pdev)
{
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
void __iomem *base;
struct clk_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
clk_data);
top_clk_data);
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
top_clk_data);
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
node, &mt8183_clk_lock, clk_data);
node, &mt8183_clk_lock, top_clk_data);
mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
base, &mt8183_clk_lock, clk_data);
base, &mt8183_clk_lock, top_clk_data);
mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
base, &mt8183_clk_lock, clk_data);
base, &mt8183_clk_lock, top_clk_data);
mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
clk_data);
top_clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
}
static int clk_mt8183_infra_probe(struct platform_device *pdev)

16
drivers/clk/renesas/renesas-cpg-mssr.c
View File

@ -572,17 +572,11 @@ static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
unsigned int reg = id / 32;
unsigned int bit = id % 32;
u32 bitmask = BIT(bit);
unsigned long flags;
u32 value;
dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
/* Reset module */
spin_lock_irqsave(&priv->rmw_lock, flags);
value = readl(priv->base + SRCR(reg));
value |= bitmask;
writel(value, priv->base + SRCR(reg));
spin_unlock_irqrestore(&priv->rmw_lock, flags);
writel(bitmask, priv->base + SRCR(reg));
/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
udelay(35);
@ -599,16 +593,10 @@ static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
unsigned int reg = id / 32;
unsigned int bit = id % 32;
u32 bitmask = BIT(bit);
unsigned long flags;
u32 value;
dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
spin_lock_irqsave(&priv->rmw_lock, flags);
value = readl(priv->base + SRCR(reg));
value |= bitmask;
writel(value, priv->base + SRCR(reg));
spin_unlock_irqrestore(&priv->rmw_lock, flags);
writel(bitmask, priv->base + SRCR(reg));
return 0;
}

1
drivers/clk/sprd/Kconfig
View File

@ -3,6 +3,7 @@ config SPRD_COMMON_CLK
tristate "Clock support for Spreadtrum SoCs"
depends on ARCH_SPRD || COMPILE_TEST
default ARCH_SPRD
select REGMAP_MMIO
if SPRD_COMMON_CLK

1
include/linux/clk.h
View File

@ -359,6 +359,7 @@ int __must_check devm_clk_bulk_get(struct device *dev, int num_clks,
/**
* devm_clk_bulk_get_optional - managed get multiple optional consumer clocks
* @dev: device for clock "consumer"
* @num_clks: the number of clk_bulk_data
* @clks: pointer to the clk_bulk_data table of consumer
*
* Behaves the same as devm_clk_bulk_get() except where there is no clock