A few fixes for code that came in during the merge window or
that started getting exercised differently this time around: - Select regmap MMIO kconfig in spreadtrum driver to avoid compile errors - Complete kerneldoc on devm_clk_bulk_get_optional() - Register an essential clk earlier on mediatek mt8183 SoCs so the clocksource driver can use it - Fix divisor math in the at91 driver - Plug a race in Renesas reset control logic -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl1DH5oRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSXEiRAAlKgH3gBvg9gtwRuK11qeW/yJYA9/rdF6 nRxMQDq3AA/BktyHpnfDBOHbHs7zmwaeg/bk0x/Ex4+mgdCRe8+X9PJxlgSovenY 8Ky0CAijGxY2Mud/R0YPR2+QVCLYON8cp9SryrWpfokZP4bMqZOKUE6vs2NbeYCa 0iDneX9UUQhvGejEnhgKiuGtiRWPux3htxNlGaHkk/I/z1CvvsfGnxfbAPWN6ppl txiZDLvtYjGx4tHVWg+olXhyQAMg3JADS1MOx3AcDv7OO5UnfLzdLMp/NLVwqdor ZmbE2yTdzplGtuoh7waE7Mel6bm/gd94XHsX5S0gJU+ock2wWYoCMMkRGskSJFg3 /Dn7ajNS0Z4xMmdyz+O3kBMB4zu8kiedT07nkwXm+bsFzGK4UEzY6Gn09JP9+m2P qSzxVLoO5Kg1M4yDIauOX6IyOC0VNgpftdZ4SGoCVqUrH3BYI804I6unbLOF5nad u4mL0v8Bfz/OuJxuvaFpWCYoowHMi7NOz9ipQRB2bS/QYCB9H6rjv8tT4xAw81w6 P6DI0eG+QCjfHCEbe8W/KikLWSL52fnycwAAospkV+1AFFZ2735oJgb9KY4xY6Qd tMRLsVjOTnq3mu/PlHuilnyaNtH7OHxp47HoBdgg8kc8VEIsfY+Z7SsPMms228/u KBzPg709SIk= =tNyv -----END PGP SIGNATURE----- Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "A few fixes for code that came in during the merge window or that started getting exercised differently this time around: - Select regmap MMIO kconfig in spreadtrum driver to avoid compile errors - Complete kerneldoc on devm_clk_bulk_get_optional() - Register an essential clk earlier on mediatek mt8183 SoCs so the clocksource driver can use it - Fix divisor math in the at91 driver - Plug a race in Renesas reset control logic" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: renesas: cpg-mssr: Fix reset control race condition clk: sprd: Select REGMAP_MMIO to avoid compile errors clk: mediatek: mt8183: Register 13MHz clock earlier for clocksource clk: Add missing documentation of devm_clk_bulk_get_optional() argument clk: at91: generated: Truncate divisor to GENERATED_MAX_DIV + 1
This commit is contained in:
commit
42d21900b3
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@ -141,6 +141,8 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
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continue;
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continue;
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div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
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div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
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if (div > GENERATED_MAX_DIV + 1)
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div = GENERATED_MAX_DIV + 1;
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clk_generated_best_diff(req, parent, parent_rate, div,
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clk_generated_best_diff(req, parent, parent_rate, div,
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&best_diff, &best_rate);
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&best_diff, &best_rate);
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@ -25,9 +25,11 @@ static const struct mtk_fixed_clk top_fixed_clks[] = {
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FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000),
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FIXED_CLK(CLK_TOP_UNIVP_192M, "univpll_192m", "univpll", 192000000),
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};
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};
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static const struct mtk_fixed_factor top_early_divs[] = {
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FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
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};
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static const struct mtk_fixed_factor top_divs[] = {
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static const struct mtk_fixed_factor top_divs[] = {
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FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1,
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2),
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FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1,
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FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1,
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2),
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2),
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FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1,
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FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1,
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@ -1148,37 +1150,57 @@ static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
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return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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}
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static struct clk_onecell_data *top_clk_data;
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static void clk_mt8183_top_init_early(struct device_node *node)
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{
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int i;
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top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
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for (i = 0; i < CLK_TOP_NR_CLK; i++)
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top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
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mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
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top_clk_data);
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of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
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}
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CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen",
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clk_mt8183_top_init_early);
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static int clk_mt8183_top_probe(struct platform_device *pdev)
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static int clk_mt8183_top_probe(struct platform_device *pdev)
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{
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{
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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void __iomem *base;
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void __iomem *base;
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struct clk_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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struct device_node *node = pdev->dev.of_node;
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base = devm_ioremap_resource(&pdev->dev, res);
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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if (IS_ERR(base))
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return PTR_ERR(base);
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return PTR_ERR(base);
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clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
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mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
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mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
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clk_data);
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top_clk_data);
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mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
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mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
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top_clk_data);
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mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
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mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
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mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
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node, &mt8183_clk_lock, clk_data);
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node, &mt8183_clk_lock, top_clk_data);
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mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
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mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
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base, &mt8183_clk_lock, clk_data);
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base, &mt8183_clk_lock, top_clk_data);
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mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
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mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
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base, &mt8183_clk_lock, clk_data);
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base, &mt8183_clk_lock, top_clk_data);
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mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
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mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
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clk_data);
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top_clk_data);
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return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
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}
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}
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static int clk_mt8183_infra_probe(struct platform_device *pdev)
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static int clk_mt8183_infra_probe(struct platform_device *pdev)
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@ -572,17 +572,11 @@ static int cpg_mssr_reset(struct reset_controller_dev *rcdev,
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unsigned int reg = id / 32;
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unsigned int reg = id / 32;
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unsigned int bit = id % 32;
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unsigned int bit = id % 32;
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u32 bitmask = BIT(bit);
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u32 bitmask = BIT(bit);
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unsigned long flags;
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u32 value;
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dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
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dev_dbg(priv->dev, "reset %u%02u\n", reg, bit);
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/* Reset module */
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/* Reset module */
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spin_lock_irqsave(&priv->rmw_lock, flags);
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writel(bitmask, priv->base + SRCR(reg));
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value = readl(priv->base + SRCR(reg));
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value |= bitmask;
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writel(value, priv->base + SRCR(reg));
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spin_unlock_irqrestore(&priv->rmw_lock, flags);
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/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
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/* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
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udelay(35);
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udelay(35);
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@ -599,16 +593,10 @@ static int cpg_mssr_assert(struct reset_controller_dev *rcdev, unsigned long id)
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unsigned int reg = id / 32;
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unsigned int reg = id / 32;
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unsigned int bit = id % 32;
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unsigned int bit = id % 32;
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u32 bitmask = BIT(bit);
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u32 bitmask = BIT(bit);
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unsigned long flags;
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u32 value;
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dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
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dev_dbg(priv->dev, "assert %u%02u\n", reg, bit);
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spin_lock_irqsave(&priv->rmw_lock, flags);
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writel(bitmask, priv->base + SRCR(reg));
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value = readl(priv->base + SRCR(reg));
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value |= bitmask;
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writel(value, priv->base + SRCR(reg));
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spin_unlock_irqrestore(&priv->rmw_lock, flags);
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return 0;
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return 0;
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}
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}
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@ -3,6 +3,7 @@ config SPRD_COMMON_CLK
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tristate "Clock support for Spreadtrum SoCs"
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tristate "Clock support for Spreadtrum SoCs"
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depends on ARCH_SPRD || COMPILE_TEST
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depends on ARCH_SPRD || COMPILE_TEST
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default ARCH_SPRD
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default ARCH_SPRD
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select REGMAP_MMIO
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if SPRD_COMMON_CLK
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if SPRD_COMMON_CLK
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@ -359,6 +359,7 @@ int __must_check devm_clk_bulk_get(struct device *dev, int num_clks,
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/**
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/**
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* devm_clk_bulk_get_optional - managed get multiple optional consumer clocks
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* devm_clk_bulk_get_optional - managed get multiple optional consumer clocks
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* @dev: device for clock "consumer"
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* @dev: device for clock "consumer"
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* @num_clks: the number of clk_bulk_data
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* @clks: pointer to the clk_bulk_data table of consumer
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* @clks: pointer to the clk_bulk_data table of consumer
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*
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*
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* Behaves the same as devm_clk_bulk_get() except where there is no clock
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* Behaves the same as devm_clk_bulk_get() except where there is no clock
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