sh: SH7786 clock framework rewrite.
This rewrites the SH7786 clock framework support completely. It's reworked to provide all of the DIV4 and MSTP function clocks. This brings it in line with the current clock framework code and lets us drop SH7786 from the list of CPUs that require legacy CPG handling. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
a4ae2b2b18
commit
43a1839cb1
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@ -551,8 +551,7 @@ config SH_PCLK_FREQ
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CPU_SUBTYPE_SH7203 || \
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CPU_SUBTYPE_SH7206 || \
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CPU_SUBTYPE_SH7263 || \
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CPU_SUBTYPE_MXG || \
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CPU_SUBTYPE_SH7786
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CPU_SUBTYPE_MXG
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default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
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default "66000000" if CPU_SUBTYPE_SH4_202
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default "50000000"
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@ -566,7 +565,8 @@ config SH_CLK_CPG
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config SH_CLK_CPG_LEGACY
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depends on SH_CLK_CPG
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def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE
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def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
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!CPU_SUBTYPE_SH7786
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config SH_CLK_MD
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int "CPU Mode Pin Setting"
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@ -3,11 +3,7 @@
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*
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* SH7786 support for the clock framework
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*
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* Copyright (C) 2008, 2009 Renesas Solutions Corp.
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* Kuninori Morimoto <morimoto.kuninori@renesas.com>
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*
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* Based on SH7785
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* Copyright (C) 2007 Paul Mundt
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* Copyright (C) 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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@ -15,127 +11,123 @@
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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static int ifc_divisors[] = { 1, 2, 4, 1 };
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static int sfc_divisors[] = { 1, 1, 4, 1 };
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static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1,
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24, 32, 1, 1, 1, 1, 1, 1 };
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static int mfc_divisors[] = { 1, 1, 4, 1 };
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static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1,
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24, 32, 1, 48, 1, 1, 1, 1 };
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static void master_clk_init(struct clk *clk)
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{
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clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
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}
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static struct clk_ops sh7786_master_clk_ops = {
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.init = master_clk_init,
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};
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static unsigned long module_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inl(FRQMR1) & 0x000f);
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return clk->parent->rate / pfc_divisors[idx];
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}
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static struct clk_ops sh7786_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static unsigned long bus_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
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return clk->parent->rate / bfc_divisors[idx];
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}
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static struct clk_ops sh7786_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static unsigned long cpu_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
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return clk->parent->rate / ifc_divisors[idx];
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}
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static struct clk_ops sh7786_cpu_clk_ops = {
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.recalc = cpu_clk_recalc,
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};
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static struct clk_ops *sh7786_clk_ops[] = {
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&sh7786_master_clk_ops,
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&sh7786_module_clk_ops,
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&sh7786_bus_clk_ops,
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&sh7786_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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if (idx < ARRAY_SIZE(sh7786_clk_ops))
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*ops = sh7786_clk_ops[idx];
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}
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static unsigned long shyway_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
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return clk->parent->rate / sfc_divisors[idx];
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}
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static struct clk_ops sh7786_shyway_clk_ops = {
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.recalc = shyway_clk_recalc,
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};
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static struct clk sh7786_shyway_clk = {
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.name = "shyway_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh7786_shyway_clk_ops,
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};
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static unsigned long ddr_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
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return clk->parent->rate / mfc_divisors[idx];
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}
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static struct clk_ops sh7786_ddr_clk_ops = {
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.recalc = ddr_clk_recalc,
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};
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static struct clk sh7786_ddr_clk = {
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.name = "ddr_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh7786_ddr_clk_ops,
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};
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/*
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* Additional SH7786-specific on-chip clocks that aren't already part of the
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* clock framework
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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static struct clk *sh7786_onchip_clocks[] = {
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&sh7786_shyway_clk,
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&sh7786_ddr_clk,
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static struct clk extal_clk = {
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.name = "extal",
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.id = -1,
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.rate = 33333333,
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};
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static unsigned long pll_recalc(struct clk *clk)
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{
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int multiplier;
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/*
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* Clock modes 0, 1, and 2 use an x64 multiplier against PLL1,
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* while modes 3, 4, and 5 use an x32.
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*/
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multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32;
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return clk->parent->rate * multiplier;
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}
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static struct clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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};
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static struct clk pll_clk = {
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.name = "pll_clk",
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.id = -1,
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.ops = &pll_clk_ops,
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.parent = &extal_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static struct clk *clks[] = {
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&extal_clk,
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&pll_clk,
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};
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static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
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24, 32, 36, 48 };
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static struct clk_div_mult_table div4_table = {
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.divisors = div2,
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.nr_divisors = ARRAY_SIZE(div2),
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};
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enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
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#define DIV4(_str, _bit, _mask, _flags) \
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SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0),
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[DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0),
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[DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT),
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[DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT),
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};
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#define MSTPCR0 0xffc40030
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#define MSTPCR1 0xffc40034
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static struct clk mstp_clks[] = {
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/* MSTPCR0 */
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SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
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SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
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SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
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SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
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SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
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SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
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SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0),
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SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0),
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SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
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SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
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SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
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SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
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SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0),
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SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0),
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SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0),
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SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0),
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SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
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SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
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SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
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SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
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SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
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/* MSTPCR1 */
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SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0),
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SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0),
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SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0),
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SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0),
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SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
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SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
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SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0),
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SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0),
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};
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int __init arch_clk_init(void)
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{
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struct clk *clk;
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int i, ret = 0;
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cpg_clk_init();
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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ret |= clk_register(clks[i]);
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clk = clk_get(NULL, "master_clk");
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for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
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struct clk *clkp = sh7786_onchip_clocks[i];
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clkp->parent = clk;
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ret |= clk_register(clkp);
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}
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clk_put(clk);
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
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&div4_table);
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if (!ret)
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ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
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return ret;
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}
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