RDMA/hns: Fix cmdq parameter of querying pf timer resource
The firmware has reduced the number of descriptions of command
HNS_ROCE_OPC_QUERY_PF_TIMER_RES to 1. The driver needs to adapt, otherwise
the hardware will report error 4(CMD_NEXT_ERR).
Fixes: 0e40dc2f70
("RDMA/hns: Add timer allocation support for hip08")
Link: https://lore.kernel.org/r/1588931159-56875-3-git-send-email-liweihang@huawei.com
Signed-off-by: Lang Cheng <chenglang@huawei.com>
Signed-off-by: Weihang Li <liweihang@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
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@ -1450,34 +1450,26 @@ static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)
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static int hns_roce_query_pf_timer_resource(struct hns_roce_dev *hr_dev)
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{
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struct hns_roce_pf_timer_res_a *req_a;
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struct hns_roce_cmq_desc desc[2];
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int ret, i;
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struct hns_roce_cmq_desc desc;
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int ret;
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for (i = 0; i < 2; i++) {
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hns_roce_cmq_setup_basic_desc(&desc[i],
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HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
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true);
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hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_QUERY_PF_TIMER_RES,
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true);
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if (i == 0)
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desc[i].flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
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else
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desc[i].flag &= ~cpu_to_le16(HNS_ROCE_CMD_FLAG_NEXT);
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}
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ret = hns_roce_cmq_send(hr_dev, desc, 2);
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ret = hns_roce_cmq_send(hr_dev, &desc, 1);
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if (ret)
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return ret;
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req_a = (struct hns_roce_pf_timer_res_a *)desc[0].data;
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req_a = (struct hns_roce_pf_timer_res_a *)desc.data;
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hr_dev->caps.qpc_timer_bt_num =
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roce_get_field(req_a->qpc_timer_bt_idx_num,
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PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M,
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PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S);
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roce_get_field(req_a->qpc_timer_bt_idx_num,
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PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_M,
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PF_RES_DATA_1_PF_QPC_TIMER_BT_NUM_S);
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hr_dev->caps.cqc_timer_bt_num =
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roce_get_field(req_a->cqc_timer_bt_idx_num,
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PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M,
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PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S);
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roce_get_field(req_a->cqc_timer_bt_idx_num,
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PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_M,
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PF_RES_DATA_2_PF_CQC_TIMER_BT_NUM_S);
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return 0;
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}
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