Merge branch 'edac-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp
* 'edac-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: amd64_edac: Disable DRAM ECC injection on K8 EDAC: Fixup scrubrate manipulation amd64_edac: Remove two-stage initialization amd64_edac: Check ECC capabilities initially amd64_edac: Carve out ECC-related hw settings amd64_edac: Remove PCI ECS enabling functions amd64_edac: Remove explicit Kconfig PCI dependency amd64_edac: Allocate driver instances dynamically amd64_edac: Rework printk macros amd64_edac: Rename CPU PCI devices amd64_edac: Concentrate per-family init even more amd64_edac: Cleanup the CPU PCI device reservation amd64_edac: Simplify CPU family detection amd64_edac: Add per-family init function amd64_edac: Use cached extended CPU model amd64_edac: Remove F11h support
This commit is contained in:
Linus Torvalds
commit
442d1ba237
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@ -75,11 +75,11 @@ config EDAC_MCE
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bool
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config EDAC_AMD64
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tristate "AMD64 (Opteron, Athlon64) K8, F10h, F11h"
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depends on EDAC_MM_EDAC && AMD_NB && X86_64 && PCI && EDAC_DECODE_MCE
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tristate "AMD64 (Opteron, Athlon64) K8, F10h"
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depends on EDAC_MM_EDAC && AMD_NB && X86_64 && EDAC_DECODE_MCE
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help
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Support for error detection and correction on the AMD 64
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Families of Memory Controllers (K8, F10h and F11h)
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Support for error detection and correction of DRAM ECC errors on
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the AMD64 families of memory controllers (K8 and F10h)
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config EDAC_AMD64_ERROR_INJECTION
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bool "Sysfs HW Error injection facilities"
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File diff suppressed because it is too large
Load Diff
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@ -74,11 +74,26 @@
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#include "edac_core.h"
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#include "mce_amd.h"
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#define amd64_printk(level, fmt, arg...) \
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edac_printk(level, "amd64", fmt, ##arg)
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#define amd64_debug(fmt, arg...) \
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edac_printk(KERN_DEBUG, "amd64", fmt, ##arg)
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#define amd64_mc_printk(mci, level, fmt, arg...) \
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edac_mc_chipset_printk(mci, level, "amd64", fmt, ##arg)
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#define amd64_info(fmt, arg...) \
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edac_printk(KERN_INFO, "amd64", fmt, ##arg)
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#define amd64_notice(fmt, arg...) \
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edac_printk(KERN_NOTICE, "amd64", fmt, ##arg)
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#define amd64_warn(fmt, arg...) \
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edac_printk(KERN_WARNING, "amd64", fmt, ##arg)
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#define amd64_err(fmt, arg...) \
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edac_printk(KERN_ERR, "amd64", fmt, ##arg)
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#define amd64_mc_warn(mci, fmt, arg...) \
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edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg)
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#define amd64_mc_err(mci, fmt, arg...) \
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edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg)
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/*
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* Throughout the comments in this code, the following terms are used:
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@ -129,11 +144,9 @@
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* sections 3.5.4 and 3.5.5 for more information.
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*/
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#define EDAC_AMD64_VERSION " Ver: 3.3.0 " __DATE__
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#define EDAC_AMD64_VERSION "v3.3.0"
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#define EDAC_MOD_STR "amd64_edac"
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#define EDAC_MAX_NUMNODES 8
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/* Extended Model from CPUID, for CPU Revision numbers */
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#define K8_REV_D 1
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#define K8_REV_E 2
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@ -322,9 +335,6 @@
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#define K8_SCRCTRL 0x58
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#define F10_NB_CFG_LOW 0x88
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#define F10_NB_CFG_LOW_ENABLE_EXT_CFG BIT(14)
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#define F10_NB_CFG_HIGH 0x8C
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#define F10_ONLINE_SPARE 0xB0
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#define F10_ONLINE_SPARE_SWAPDONE0(x) ((x) & BIT(1))
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@ -373,7 +383,6 @@ static inline int get_node_id(struct pci_dev *pdev)
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enum amd64_chipset_families {
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K8_CPUS = 0,
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F10_CPUS,
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F11_CPUS,
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};
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/* Error injection control structure */
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@ -384,16 +393,13 @@ struct error_injection {
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};
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struct amd64_pvt {
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struct low_ops *ops;
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/* pci_device handles which we utilize */
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struct pci_dev *addr_f1_ctl;
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struct pci_dev *dram_f2_ctl;
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struct pci_dev *misc_f3_ctl;
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struct pci_dev *F1, *F2, *F3;
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int mc_node_id; /* MC index of this MC node */
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int ext_model; /* extended model value of this node */
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struct low_ops *ops; /* pointer to per PCI Device ID func table */
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int channel_count;
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/* Raw registers */
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@ -455,27 +461,27 @@ struct amd64_pvt {
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/* place to store error injection parameters prior to issue */
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struct error_injection injection;
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/* Save old hw registers' values before we modified them */
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u32 nbctl_mcgctl_saved; /* When true, following 2 are valid */
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/* DCT per-family scrubrate setting */
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u32 min_scrubrate;
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/* family name this instance is running on */
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const char *ctl_name;
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};
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/*
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* per-node ECC settings descriptor
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*/
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struct ecc_settings {
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u32 old_nbctl;
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bool nbctl_valid;
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/* MC Type Index value: socket F vs Family 10h */
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u32 mc_type_index;
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/* misc settings */
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struct flags {
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unsigned long cf8_extcfg:1;
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unsigned long nb_mce_enable:1;
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unsigned long nb_ecc_prev:1;
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} flags;
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};
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struct scrubrate {
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u32 scrubval; /* bit pattern for scrub rate */
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u32 bandwidth; /* bandwidth consumed (bytes/sec) */
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};
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extern struct scrubrate scrubrates[23];
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extern const char *tt_msgs[4];
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extern const char *ll_msgs[4];
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extern const char *rrrr_msgs[16];
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@ -517,23 +523,10 @@ struct low_ops {
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struct amd64_family_type {
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const char *ctl_name;
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u16 addr_f1_ctl;
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u16 misc_f3_ctl;
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u16 f1_id, f3_id;
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struct low_ops ops;
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};
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static struct amd64_family_type amd64_family_types[];
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static inline const char *get_amd_family_name(int index)
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{
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return amd64_family_types[index].ctl_name;
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}
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static inline struct low_ops *family_ops(int index)
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{
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return &amd64_family_types[index].ops;
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}
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static inline int amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
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u32 *val, const char *func)
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{
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@ -541,8 +534,8 @@ static inline int amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
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err = pci_read_config_dword(pdev, offset, val);
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if (err)
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amd64_printk(KERN_WARNING, "%s: error reading F%dx%x.\n",
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func, PCI_FUNC(pdev->devfn), offset);
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amd64_warn("%s: error reading F%dx%x.\n",
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func, PCI_FUNC(pdev->devfn), offset);
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return err;
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}
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@ -556,7 +549,6 @@ static inline int amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
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*/
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#define K8_MIN_SCRUB_RATE_BITS 0x0
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#define F10_MIN_SCRUB_RATE_BITS 0x5
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#define F11_MIN_SCRUB_RATE_BITS 0x6
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int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
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u64 *hole_offset, u64 *hole_size);
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@ -23,9 +23,7 @@ static ssize_t amd64_inject_section_store(struct mem_ctl_info *mci,
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if (ret != -EINVAL) {
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if (value > 3) {
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amd64_printk(KERN_WARNING,
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"%s: invalid section 0x%lx\n",
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__func__, value);
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amd64_warn("%s: invalid section 0x%lx\n", __func__, value);
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return -EINVAL;
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}
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@ -58,9 +56,7 @@ static ssize_t amd64_inject_word_store(struct mem_ctl_info *mci,
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if (ret != -EINVAL) {
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if (value > 8) {
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amd64_printk(KERN_WARNING,
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"%s: invalid word 0x%lx\n",
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__func__, value);
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amd64_warn("%s: invalid word 0x%lx\n", __func__, value);
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return -EINVAL;
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}
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@ -92,9 +88,8 @@ static ssize_t amd64_inject_ecc_vector_store(struct mem_ctl_info *mci,
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if (ret != -EINVAL) {
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if (value & 0xFFFF0000) {
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amd64_printk(KERN_WARNING,
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"%s: invalid EccVector: 0x%lx\n",
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__func__, value);
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amd64_warn("%s: invalid EccVector: 0x%lx\n",
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__func__, value);
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return -EINVAL;
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}
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@ -122,15 +117,13 @@ static ssize_t amd64_inject_read_store(struct mem_ctl_info *mci,
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/* Form value to choose 16-byte section of cacheline */
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section = F10_NB_ARRAY_DRAM_ECC |
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SET_NB_ARRAY_ADDRESS(pvt->injection.section);
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pci_write_config_dword(pvt->misc_f3_ctl,
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F10_NB_ARRAY_ADDR, section);
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pci_write_config_dword(pvt->F3, F10_NB_ARRAY_ADDR, section);
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word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection.word,
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pvt->injection.bit_map);
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/* Issue 'word' and 'bit' along with the READ request */
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pci_write_config_dword(pvt->misc_f3_ctl,
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F10_NB_ARRAY_DATA, word_bits);
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pci_write_config_dword(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
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debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
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@ -157,15 +150,13 @@ static ssize_t amd64_inject_write_store(struct mem_ctl_info *mci,
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/* Form value to choose 16-byte section of cacheline */
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section = F10_NB_ARRAY_DRAM_ECC |
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SET_NB_ARRAY_ADDRESS(pvt->injection.section);
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pci_write_config_dword(pvt->misc_f3_ctl,
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F10_NB_ARRAY_ADDR, section);
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pci_write_config_dword(pvt->F3, F10_NB_ARRAY_ADDR, section);
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word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection.word,
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pvt->injection.bit_map);
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/* Issue 'word' and 'bit' along with the READ request */
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pci_write_config_dword(pvt->misc_f3_ctl,
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F10_NB_ARRAY_DATA, word_bits);
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pci_write_config_dword(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
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debugf0("section=0x%x word_bits=0x%x\n", section, word_bits);
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@ -818,9 +818,10 @@ static void cpc925_del_edac_devices(void)
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}
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/* Convert current back-ground scrub rate into byte/sec bandwith */
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static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
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static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci)
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{
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struct cpc925_mc_pdata *pdata = mci->pvt_info;
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int bw;
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u32 mscr;
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u8 si;
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@ -832,11 +833,11 @@ static int cpc925_get_sdram_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
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if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) ||
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(si == 0)) {
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cpc925_mc_printk(mci, KERN_INFO, "Scrub mode not enabled\n");
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*bw = 0;
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bw = 0;
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} else
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*bw = CPC925_SCRUB_BLOCK_SIZE * 0xFA67 / si;
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bw = CPC925_SCRUB_BLOCK_SIZE * 0xFA67 / si;
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return 0;
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return bw;
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}
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/* Return 0 for single channel; 1 for dual channel */
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|
|
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@ -983,11 +983,11 @@ static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw)
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pci_write_config_word(pdev, E752X_MCHSCRB, scrubrates[i].scrubval);
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|
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return 0;
|
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return scrubrates[i].bandwidth;
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}
|
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|
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/* Convert current scrub rate value into byte/sec bandwidth */
|
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static int get_sdram_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
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static int get_sdram_scrub_rate(struct mem_ctl_info *mci)
|
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{
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const struct scrubrate *scrubrates;
|
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struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
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|
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@ -1013,10 +1013,8 @@ static int get_sdram_scrub_rate(struct mem_ctl_info *mci, u32 *bw)
|
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"Invalid sdram scrub control value: 0x%x\n", scrubval);
|
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return -1;
|
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}
|
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return scrubrates[i].bandwidth;
|
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|
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*bw = scrubrates[i].bandwidth;
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|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Return 1 if dual channel mode is active. Else return 0. */
|
||||
|
|
|
|||
|
|
@ -68,9 +68,10 @@
|
|||
#define EDAC_PCI "PCI"
|
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#define EDAC_DEBUG "DEBUG"
|
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|
||||
extern const char *edac_mem_types[];
|
||||
|
||||
#ifdef CONFIG_EDAC_DEBUG
|
||||
extern int edac_debug_level;
|
||||
extern const char *edac_mem_types[];
|
||||
|
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#define edac_debug_printk(level, fmt, arg...) \
|
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do { \
|
||||
|
|
@ -386,7 +387,7 @@ struct mem_ctl_info {
|
|||
representation and converts it to the closest matching
|
||||
bandwith in bytes/sec.
|
||||
*/
|
||||
int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
|
||||
int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
|
||||
|
||||
|
||||
/* pointer to edac checking routine */
|
||||
|
|
|
|||
|
|
@ -76,6 +76,8 @@ static void edac_mc_dump_mci(struct mem_ctl_info *mci)
|
|||
debugf3("\tpvt_info = %p\n\n", mci->pvt_info);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_EDAC_DEBUG */
|
||||
|
||||
/*
|
||||
* keep those in sync with the enum mem_type
|
||||
*/
|
||||
|
|
@ -100,8 +102,6 @@ const char *edac_mem_types[] = {
|
|||
};
|
||||
EXPORT_SYMBOL_GPL(edac_mem_types);
|
||||
|
||||
#endif /* CONFIG_EDAC_DEBUG */
|
||||
|
||||
/* 'ptr' points to a possibly unaligned item X such that sizeof(X) is 'size'.
|
||||
* Adjust 'ptr' so that its alignment is at least as stringent as what the
|
||||
* compiler would provide for X and return the aligned result.
|
||||
|
|
|
|||
|
|
@ -436,56 +436,55 @@ static ssize_t mci_reset_counters_store(struct mem_ctl_info *mci,
|
|||
return count;
|
||||
}
|
||||
|
||||
/* memory scrubbing */
|
||||
/* Memory scrubbing interface:
|
||||
*
|
||||
* A MC driver can limit the scrubbing bandwidth based on the CPU type.
|
||||
* Therefore, ->set_sdram_scrub_rate should be made to return the actual
|
||||
* bandwidth that is accepted or 0 when scrubbing is to be disabled.
|
||||
*
|
||||
* Negative value still means that an error has occurred while setting
|
||||
* the scrub rate.
|
||||
*/
|
||||
static ssize_t mci_sdram_scrub_rate_store(struct mem_ctl_info *mci,
|
||||
const char *data, size_t count)
|
||||
{
|
||||
unsigned long bandwidth = 0;
|
||||
int err;
|
||||
int new_bw = 0;
|
||||
|
||||
if (!mci->set_sdram_scrub_rate) {
|
||||
edac_printk(KERN_WARNING, EDAC_MC,
|
||||
"Memory scrub rate setting not implemented!\n");
|
||||
if (!mci->set_sdram_scrub_rate)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (strict_strtoul(data, 10, &bandwidth) < 0)
|
||||
return -EINVAL;
|
||||
|
||||
err = mci->set_sdram_scrub_rate(mci, (u32)bandwidth);
|
||||
if (err) {
|
||||
edac_printk(KERN_DEBUG, EDAC_MC,
|
||||
"Failed setting scrub rate to %lu\n", bandwidth);
|
||||
return -EINVAL;
|
||||
}
|
||||
else {
|
||||
edac_printk(KERN_DEBUG, EDAC_MC,
|
||||
"Scrub rate set to: %lu\n", bandwidth);
|
||||
new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
|
||||
if (new_bw >= 0) {
|
||||
edac_printk(KERN_DEBUG, EDAC_MC, "Scrub rate set to %d\n", new_bw);
|
||||
return count;
|
||||
}
|
||||
|
||||
edac_printk(KERN_DEBUG, EDAC_MC, "Error setting scrub rate to: %lu\n", bandwidth);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* ->get_sdram_scrub_rate() return value semantics same as above.
|
||||
*/
|
||||
static ssize_t mci_sdram_scrub_rate_show(struct mem_ctl_info *mci, char *data)
|
||||
{
|
||||
u32 bandwidth = 0;
|
||||
int err;
|
||||
int bandwidth = 0;
|
||||
|
||||
if (!mci->get_sdram_scrub_rate) {
|
||||
edac_printk(KERN_WARNING, EDAC_MC,
|
||||
"Memory scrub rate reading not implemented\n");
|
||||
if (!mci->get_sdram_scrub_rate)
|
||||
return -EINVAL;
|
||||
|
||||
bandwidth = mci->get_sdram_scrub_rate(mci);
|
||||
if (bandwidth < 0) {
|
||||
edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
|
||||
return bandwidth;
|
||||
}
|
||||
|
||||
err = mci->get_sdram_scrub_rate(mci, &bandwidth);
|
||||
if (err) {
|
||||
edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
|
||||
return err;
|
||||
}
|
||||
else {
|
||||
edac_printk(KERN_DEBUG, EDAC_MC,
|
||||
"Read scrub rate: %d\n", bandwidth);
|
||||
return sprintf(data, "%d\n", bandwidth);
|
||||
}
|
||||
edac_printk(KERN_DEBUG, EDAC_MC, "Read scrub rate: %d\n", bandwidth);
|
||||
return sprintf(data, "%d\n", bandwidth);
|
||||
}
|
||||
|
||||
/* default attribute files for the MCI object */
|
||||
|
|
|
|||
|
|
@ -611,20 +611,17 @@ static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth)
|
|||
|
||||
bandwidth = 5900000 * i5100_mc_scrben(dw);
|
||||
|
||||
return 0;
|
||||
return bandwidth;
|
||||
}
|
||||
|
||||
static int i5100_get_scrub_rate(struct mem_ctl_info *mci,
|
||||
u32 *bandwidth)
|
||||
static int i5100_get_scrub_rate(struct mem_ctl_info *mci)
|
||||
{
|
||||
struct i5100_priv *priv = mci->pvt_info;
|
||||
u32 dw;
|
||||
|
||||
pci_read_config_dword(priv->mc, I5100_MC, &dw);
|
||||
|
||||
*bandwidth = 5900000 * i5100_mc_scrben(dw);
|
||||
|
||||
return 0;
|
||||
return 5900000 * i5100_mc_scrben(dw);
|
||||
}
|
||||
|
||||
static struct pci_dev *pci_get_device_func(unsigned vendor,
|
||||
|
|
|
|||
Loading…
Reference in New Issue