[ARM] 4186/1: iop: remove cp6_enable/disable routines
This functionality is replaced by cp6_trap Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
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@ -161,65 +161,49 @@ static void write_intsize(u32 val)
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static void
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iop13xx_irq_mask0 (unsigned int irq)
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{
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u32 cp_flags = iop13xx_cp6_save();
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write_intctl_0(read_intctl_0() & ~(1 << (irq - 0)));
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iop13xx_cp6_restore(cp_flags);
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}
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static void
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iop13xx_irq_mask1 (unsigned int irq)
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{
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u32 cp_flags = iop13xx_cp6_save();
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write_intctl_1(read_intctl_1() & ~(1 << (irq - 32)));
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iop13xx_cp6_restore(cp_flags);
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}
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static void
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iop13xx_irq_mask2 (unsigned int irq)
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{
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u32 cp_flags = iop13xx_cp6_save();
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write_intctl_2(read_intctl_2() & ~(1 << (irq - 64)));
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iop13xx_cp6_restore(cp_flags);
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}
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static void
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iop13xx_irq_mask3 (unsigned int irq)
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{
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u32 cp_flags = iop13xx_cp6_save();
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write_intctl_3(read_intctl_3() & ~(1 << (irq - 96)));
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iop13xx_cp6_restore(cp_flags);
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}
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static void
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iop13xx_irq_unmask0(unsigned int irq)
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{
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u32 cp_flags = iop13xx_cp6_save();
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write_intctl_0(read_intctl_0() | (1 << (irq - 0)));
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iop13xx_cp6_restore(cp_flags);
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}
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static void
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iop13xx_irq_unmask1(unsigned int irq)
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{
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u32 cp_flags = iop13xx_cp6_save();
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write_intctl_1(read_intctl_1() | (1 << (irq - 32)));
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iop13xx_cp6_restore(cp_flags);
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}
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static void
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iop13xx_irq_unmask2(unsigned int irq)
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{
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u32 cp_flags = iop13xx_cp6_save();
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write_intctl_2(read_intctl_2() | (1 << (irq - 64)));
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iop13xx_cp6_restore(cp_flags);
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}
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static void
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iop13xx_irq_unmask3(unsigned int irq)
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{
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u32 cp_flags = iop13xx_cp6_save();
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write_intctl_3(read_intctl_3() | (1 << (irq - 96)));
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iop13xx_cp6_restore(cp_flags);
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}
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static struct irq_chip iop13xx_irqchip1 = {
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@ -256,7 +240,6 @@ void __init iop13xx_init_irq(void)
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{
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unsigned int i;
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u32 cp_flags = iop13xx_cp6_save();
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iop_init_cp6_handler();
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/* disable all interrupts */
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@ -288,6 +271,4 @@ void __init iop13xx_init_irq(void)
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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iop13xx_cp6_restore(cp_flags);
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}
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@ -38,11 +38,8 @@ static inline u32 read_tcr1(void)
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unsigned long iop13xx_gettimeoffset(void)
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{
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unsigned long offset;
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u32 cp_flags;
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cp_flags = iop13xx_cp6_save();
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offset = next_jiffy_time - read_tcr1();
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iop13xx_cp6_restore(cp_flags);
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return offset / ticks_per_usec;
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}
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@ -50,8 +47,6 @@ unsigned long iop13xx_gettimeoffset(void)
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static irqreturn_t
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iop13xx_timer_interrupt(int irq, void *dev_id)
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{
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u32 cp_flags = iop13xx_cp6_save();
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write_seqlock(&xtime_lock);
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asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (1));
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@ -64,8 +59,6 @@ iop13xx_timer_interrupt(int irq, void *dev_id)
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write_sequnlock(&xtime_lock);
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iop13xx_cp6_restore(cp_flags);
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return IRQ_HANDLED;
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}
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@ -78,7 +71,6 @@ static struct irqaction iop13xx_timer_irq = {
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void __init iop13xx_init_time(unsigned long tick_rate)
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{
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u32 timer_ctl;
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u32 cp_flags;
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ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
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ticks_per_usec = tick_rate / 1000000;
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@ -91,12 +83,10 @@ void __init iop13xx_init_time(unsigned long tick_rate)
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* We use timer 0 for our timer interrupt, and timer 1 as
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* monotonic counter for tracking missed jiffies.
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*/
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cp_flags = iop13xx_cp6_save();
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asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (ticks_per_jiffy - 1));
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asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (timer_ctl));
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asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (0xffffffff));
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asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (timer_ctl));
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iop13xx_cp6_restore(cp_flags);
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setup_irq(IRQ_IOP13XX_TIMER0, &iop13xx_timer_irq);
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}
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@ -23,16 +23,12 @@ static u32 iop32x_mask;
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static inline void intctl_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intstr_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static void
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@ -24,44 +24,32 @@ static u32 iop33x_mask1;
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static inline void intctl0_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intctl1_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intstr0_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intstr1_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intbase_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static inline void intsize_write(u32 val)
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{
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
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iop3xx_cp6_disable();
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}
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static void
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@ -51,9 +51,7 @@ iop3xx_timer_interrupt(int irq, void *dev_id)
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{
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write_seqlock(&xtime_lock);
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (1));
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iop3xx_cp6_disable();
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while ((signed long)(next_jiffy_time - *IOP3XX_TU_TCR1)
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>= ticks_per_jiffy) {
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@ -87,12 +85,10 @@ void __init iop3xx_init_time(unsigned long tick_rate)
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* We use timer 0 for our timer interrupt, and timer 1 as
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* monotonic counter for tracking missed jiffies.
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*/
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iop3xx_cp6_enable();
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asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (ticks_per_jiffy - 1));
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asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (timer_ctl));
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asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (0xffffffff));
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asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (timer_ctl));
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iop3xx_cp6_disable();
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setup_irq(IRQ_IOP3XX_TIMER0, &iop3xx_timer_irq);
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}
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@ -12,32 +12,6 @@ void iop13xx_init_irq(void);
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void iop13xx_init_time(unsigned long tickrate);
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unsigned long iop13xx_gettimeoffset(void);
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/* handle cp6 access
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* to do: handle access in entry-armv5.S and unify with
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* the iop3xx implementation
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* note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h)
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* when interrupts are enabled
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*/
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static inline unsigned long iop13xx_cp6_save(void)
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{
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u32 temp, cp_flags;
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asm volatile (
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"mrc p15, 0, %1, c15, c1, 0\n\t"
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"orr %0, %1, #(1 << 6)\n\t"
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"mcr p15, 0, %0, c15, c1, 0\n\t"
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: "=r" (temp), "=r"(cp_flags));
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return cp_flags;
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}
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static inline void iop13xx_cp6_restore(unsigned long cp_flags)
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{
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asm volatile (
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"mcr p15, 0, %0, c15, c1, 0\n\t"
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: : "r" (cp_flags) );
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}
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/* CPUID CP6 R0 Page 0 */
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static inline int iop13xx_cpu_id(void)
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{
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@ -3,8 +3,6 @@
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#ifndef __ASSEMBLER__
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#include <linux/types.h>
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#include <asm/system.h> /* local_irq_save */
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#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */
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/* INTPND0 CP6 R0 Page 3
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*/
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@ -41,21 +39,6 @@ static inline u32 read_intpnd_3(void)
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asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
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return val;
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}
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static inline void
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iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags)
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{
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local_irq_save(*irq_flags);
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*cp_flags = iop13xx_cp6_save();
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}
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static inline void
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iop13xx_cp6_irq_restore(unsigned long *cp_flags,
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unsigned long *irq_flags)
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{
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iop13xx_cp6_restore(*cp_flags);
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local_irq_restore(*irq_flags);
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}
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#endif
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#define INTBASE 0
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@ -48,12 +48,10 @@ static inline void arch_reset(char mode)
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/*
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* Reset the internal bus (warning both cores are reset)
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*/
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u32 cp_flags = iop13xx_cp6_save();
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write_wdtcr(IOP13XX_WDTCR_EN_ARM);
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write_wdtcr(IOP13XX_WDTCR_EN);
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write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
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write_wdtcr(0x1000);
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iop13xx_cp6_restore(cp_flags);
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for(;;);
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}
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@ -283,33 +283,6 @@ void iop_init_cp6_handler(void);
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extern struct platform_device iop3xx_i2c0_device;
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extern struct platform_device iop3xx_i2c1_device;
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extern inline void iop3xx_cp6_enable(void)
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{
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u32 temp;
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asm volatile (
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"orr %0, %0, #(1 << 6)\n\t"
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"mcr p15, 0, %0, c15, c1, 0\n\t"
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"mov %0, %0\n\t"
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"sub pc, pc, #4\n\t"
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: "=r" (temp) );
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}
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extern inline void iop3xx_cp6_disable(void)
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{
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u32 temp;
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asm volatile (
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"bic %0, %0, #(1 << 6)\n\t"
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"mcr p15, 0, %0, c15, c1, 0\n\t"
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"mov %0, %0\n\t"
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"sub pc, pc, #4\n\t"
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: "=r" (temp) );
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}
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#endif
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