ARM: tegra: Add EMC driver for v4.2-rc1
This introduces the EMC driver that's required to scale the external memory frequency. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAABCAAGBQJVU1FHAAoJEN0jrNd/PrOhClAQAKDOt5OYvadTfmPogJiwxlQl 7NvVVsnIzHfScANP6B/pynoC8Gfx1owRdLzPPWKM860gtdtaA9pXOWRuxQV8NLcR 5WQO4Z4sNXyvA704MNFK+EqydCN2Iu/Z+2Ups8VHZ9VmukSNaCu/se6JvW+GJMm1 DHytjzHeckNUruNrZnXLA6ckwymDbMtCBV3W9hIeKe9aPjJrgjR7Rlhhu7cX9XGF XSCF9eigh4MsyLgf3cWMoVl2NIePCW3sbAQEKkiM5xzPo21VlpPyja7OWoytcQkC HEMmuICfwT8XEd7fTabW+WHxTnVhkL+OZ833p+LSBUCeXJ82N8vSV8HZlRHly9LZ diXoJ9+2l/C02FtnnB7BtLxnyQ2NF6LAP1CvYZ7eF/Z+lxthErs0bIXyjC0RTuBN 9y6t0/VhEGMv6ApOly1VrHLtU6LnQEbYryvlOjvP4NQVb6jQc165UdPZtXufgx9o VprQoOIHdBzMnThI7ndRWgZcayn+VmJy0TvjTGmhLcurwigbCjkqYdwhq2c7Z0F2 FpEOCqWMJ0mywQXoZadIk5ON51IVRin0otyKed14PY9QU6c6hJ6NCZQi1pQnB95W Ut7ZrdZnZMIjMui8EOzeJc82mjKL3agpbYTQqqiIV+kHY9dXpxSOOHd4DbMN5Kc2 3xvgkGtj61VOlGiGnp/W =QeY4 -----END PGP SIGNATURE----- Merge tag 'tegra-for-4.2-emc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers Merge "ARM: tegra: Add EMC driver for v4.2-rc1" from Thierry Reding: This introduces the EMC driver that's required to scale the external memory frequency. * tag 'tegra-for-4.2-emc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra: Add EMC frequency debugfs entry memory: tegra: Add EMC (external memory controller) driver memory: tegra: Add API needed by the EMC driver of: Add Tegra124 EMC bindings of: Document timings subnode of nvidia,tegra-mc
This commit is contained in:
Arnd Bergmann
commit
44fb3026ad
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@ -1,6 +1,9 @@
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NVIDIA Tegra Memory Controller device tree bindings
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===================================================
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memory-controller node
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----------------------
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Required properties:
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- compatible: Should be "nvidia,tegra<chip>-mc"
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- reg: Physical base address and length of the controller's registers.
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@ -15,9 +18,49 @@ Required properties:
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This device implements an IOMMU that complies with the generic IOMMU binding.
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See ../iommu/iommu.txt for details.
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Example:
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--------
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emc-timings subnode
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-------------------
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The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in
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register PMC_STRAPPING_OPT_A).
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Required properties for "emc-timings" nodes :
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- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for.
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timing subnode
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--------------
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Each "emc-timings" node should contain a subnode for every supported EMC clock rate.
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Required properties for timing nodes :
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- clock-frequency : Should contain the memory clock rate in Hz.
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- nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC
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(see section "15.6.1 MC Registers" in the TRM), these are the registers whose values need to be
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specified, according to the board documentation:
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MC_EMEM_ARB_CFG
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MC_EMEM_ARB_OUTSTANDING_REQ
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MC_EMEM_ARB_TIMING_RCD
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MC_EMEM_ARB_TIMING_RP
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MC_EMEM_ARB_TIMING_RC
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MC_EMEM_ARB_TIMING_RAS
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MC_EMEM_ARB_TIMING_FAW
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MC_EMEM_ARB_TIMING_RRD
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MC_EMEM_ARB_TIMING_RAP2PRE
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MC_EMEM_ARB_TIMING_WAP2PRE
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MC_EMEM_ARB_TIMING_R2R
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MC_EMEM_ARB_TIMING_W2W
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MC_EMEM_ARB_TIMING_R2W
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MC_EMEM_ARB_TIMING_W2R
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MC_EMEM_ARB_DA_TURNS
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MC_EMEM_ARB_DA_COVERS
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MC_EMEM_ARB_MISC0
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MC_EMEM_ARB_MISC1
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MC_EMEM_ARB_RING1_THROTTLE
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Example SoC include file:
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/ {
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mc: memory-controller@0,70019000 {
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compatible = "nvidia,tegra124-mc";
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reg = <0x0 0x70019000 0x0 0x1000>;
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@ -34,3 +77,40 @@ Example:
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...
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iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
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};
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};
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Example board file:
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/ {
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memory-controller@0,70019000 {
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emc-timings-3 {
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nvidia,ram-code = <3>;
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timing-12750000 {
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clock-frequency = <12750000>;
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nvidia,emem-configuration = <
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0x40040001 /* MC_EMEM_ARB_CFG */
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0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
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0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
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0x00000001 /* MC_EMEM_ARB_TIMING_RP */
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0x00000002 /* MC_EMEM_ARB_TIMING_RC */
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0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
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0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
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0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
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0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
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0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
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0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
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0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
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0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
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0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
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0x06030203 /* MC_EMEM_ARB_DA_TURNS */
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0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
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0x77e30303 /* MC_EMEM_ARB_MISC0 */
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0x70000f03 /* MC_EMEM_ARB_MISC1 */
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0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
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>;
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};
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};
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};
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};
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@ -0,0 +1,374 @@
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NVIDIA Tegra124 SoC EMC (external memory controller)
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====================================================
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Required properties :
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- compatible : Should be "nvidia,tegra124-emc".
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- reg : physical base address and length of the controller's registers.
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- nvidia,memory-controller : phandle of the MC driver.
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The node should contain a "emc-timings" subnode for each supported RAM type
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(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address
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being its RAM_CODE.
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Required properties for "emc-timings" nodes :
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- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
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used for.
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Each "emc-timings" node should contain a "timing" subnode for every supported
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EMC clock rate. The "timing" subnodes should have the clock rate in Hz as
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their unit address.
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Required properties for "timing" nodes :
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- clock-frequency : Should contain the memory clock rate in Hz.
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- The following properties contain EMC timing characterization values
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(specified in the board documentation) :
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- nvidia,emc-auto-cal-config : EMC_AUTO_CAL_CONFIG
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- nvidia,emc-auto-cal-config2 : EMC_AUTO_CAL_CONFIG2
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- nvidia,emc-auto-cal-config3 : EMC_AUTO_CAL_CONFIG3
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- nvidia,emc-auto-cal-interval : EMC_AUTO_CAL_INTERVAL
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- nvidia,emc-bgbias-ctl0 : EMC_BGBIAS_CTL0
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- nvidia,emc-cfg : EMC_CFG
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- nvidia,emc-cfg-2 : EMC_CFG_2
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- nvidia,emc-ctt-term-ctrl : EMC_CTT_TERM_CTRL
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- nvidia,emc-mode-1 : Mode Register 1
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- nvidia,emc-mode-2 : Mode Register 2
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- nvidia,emc-mode-4 : Mode Register 4
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- nvidia,emc-mode-reset : Mode Register 0
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- nvidia,emc-mrs-wait-cnt : EMC_MRS_WAIT_CNT
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- nvidia,emc-sel-dpd-ctrl : EMC_SEL_DPD_CTRL
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- nvidia,emc-xm2dqspadctrl2 : EMC_XM2DQSPADCTRL2
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- nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change
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- nvidia,emc-zcal-interval : EMC_ZCAL_INTERVAL
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- nvidia,emc-configuration : EMC timing characterization data. These are the
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registers (see section "15.6.2 EMC Registers" in the TRM) whose values need to
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be specified, according to the board documentation:
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EMC_RC
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EMC_RFC
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EMC_RFC_SLR
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EMC_RAS
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EMC_RP
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EMC_R2W
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EMC_W2R
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EMC_R2P
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EMC_W2P
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EMC_RD_RCD
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EMC_WR_RCD
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EMC_RRD
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EMC_REXT
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EMC_WEXT
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EMC_WDV
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EMC_WDV_MASK
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EMC_QUSE
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EMC_QUSE_WIDTH
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EMC_IBDLY
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EMC_EINPUT
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EMC_EINPUT_DURATION
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EMC_PUTERM_EXTRA
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EMC_PUTERM_WIDTH
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EMC_PUTERM_ADJ
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EMC_CDB_CNTL_1
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EMC_CDB_CNTL_2
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EMC_CDB_CNTL_3
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EMC_QRST
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EMC_QSAFE
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EMC_RDV
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EMC_RDV_MASK
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EMC_REFRESH
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EMC_BURST_REFRESH_NUM
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EMC_PRE_REFRESH_REQ_CNT
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EMC_PDEX2WR
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EMC_PDEX2RD
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EMC_PCHG2PDEN
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EMC_ACT2PDEN
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EMC_AR2PDEN
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EMC_RW2PDEN
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EMC_TXSR
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EMC_TXSRDLL
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EMC_TCKE
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EMC_TCKESR
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EMC_TPD
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EMC_TFAW
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EMC_TRPAB
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EMC_TCLKSTABLE
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EMC_TCLKSTOP
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EMC_TREFBW
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EMC_FBIO_CFG6
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EMC_ODT_WRITE
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EMC_ODT_READ
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EMC_FBIO_CFG5
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EMC_CFG_DIG_DLL
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EMC_CFG_DIG_DLL_PERIOD
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EMC_DLL_XFORM_DQS0
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EMC_DLL_XFORM_DQS1
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EMC_DLL_XFORM_DQS2
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EMC_DLL_XFORM_DQS3
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EMC_DLL_XFORM_DQS4
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EMC_DLL_XFORM_DQS5
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EMC_DLL_XFORM_DQS6
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EMC_DLL_XFORM_DQS7
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EMC_DLL_XFORM_DQS8
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EMC_DLL_XFORM_DQS9
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EMC_DLL_XFORM_DQS10
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EMC_DLL_XFORM_DQS11
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EMC_DLL_XFORM_DQS12
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EMC_DLL_XFORM_DQS13
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EMC_DLL_XFORM_DQS14
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EMC_DLL_XFORM_DQS15
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EMC_DLL_XFORM_QUSE0
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EMC_DLL_XFORM_QUSE1
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EMC_DLL_XFORM_QUSE2
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EMC_DLL_XFORM_QUSE3
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EMC_DLL_XFORM_QUSE4
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EMC_DLL_XFORM_QUSE5
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EMC_DLL_XFORM_QUSE6
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EMC_DLL_XFORM_QUSE7
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EMC_DLL_XFORM_ADDR0
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EMC_DLL_XFORM_ADDR1
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EMC_DLL_XFORM_ADDR2
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EMC_DLL_XFORM_ADDR3
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EMC_DLL_XFORM_ADDR4
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EMC_DLL_XFORM_ADDR5
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EMC_DLL_XFORM_QUSE8
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EMC_DLL_XFORM_QUSE9
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EMC_DLL_XFORM_QUSE10
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EMC_DLL_XFORM_QUSE11
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EMC_DLL_XFORM_QUSE12
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EMC_DLL_XFORM_QUSE13
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EMC_DLL_XFORM_QUSE14
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EMC_DLL_XFORM_QUSE15
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EMC_DLI_TRIM_TXDQS0
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EMC_DLI_TRIM_TXDQS1
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EMC_DLI_TRIM_TXDQS2
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EMC_DLI_TRIM_TXDQS3
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EMC_DLI_TRIM_TXDQS4
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EMC_DLI_TRIM_TXDQS5
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EMC_DLI_TRIM_TXDQS6
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EMC_DLI_TRIM_TXDQS7
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EMC_DLI_TRIM_TXDQS8
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EMC_DLI_TRIM_TXDQS9
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EMC_DLI_TRIM_TXDQS10
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EMC_DLI_TRIM_TXDQS11
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EMC_DLI_TRIM_TXDQS12
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EMC_DLI_TRIM_TXDQS13
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EMC_DLI_TRIM_TXDQS14
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EMC_DLI_TRIM_TXDQS15
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EMC_DLL_XFORM_DQ0
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EMC_DLL_XFORM_DQ1
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EMC_DLL_XFORM_DQ2
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EMC_DLL_XFORM_DQ3
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EMC_DLL_XFORM_DQ4
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EMC_DLL_XFORM_DQ5
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EMC_DLL_XFORM_DQ6
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EMC_DLL_XFORM_DQ7
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EMC_XM2CMDPADCTRL
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EMC_XM2CMDPADCTRL4
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EMC_XM2CMDPADCTRL5
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EMC_XM2DQPADCTRL2
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EMC_XM2DQPADCTRL3
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EMC_XM2CLKPADCTRL
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EMC_XM2CLKPADCTRL2
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EMC_XM2COMPPADCTRL
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EMC_XM2VTTGENPADCTRL
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EMC_XM2VTTGENPADCTRL2
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EMC_XM2VTTGENPADCTRL3
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EMC_XM2DQSPADCTRL3
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EMC_XM2DQSPADCTRL4
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EMC_XM2DQSPADCTRL5
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EMC_XM2DQSPADCTRL6
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EMC_DSR_VTTGEN_DRV
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EMC_TXDSRVTTGEN
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EMC_FBIO_SPARE
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EMC_ZCAL_WAIT_CNT
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EMC_MRS_WAIT_CNT2
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EMC_CTT
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EMC_CTT_DURATION
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EMC_CFG_PIPE
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EMC_DYN_SELF_REF_CONTROL
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EMC_QPOP
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Example SoC include file:
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/ {
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emc@0,7001b000 {
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compatible = "nvidia,tegra124-emc";
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reg = <0x0 0x7001b000 0x0 0x1000>;
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nvidia,memory-controller = <&mc>;
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};
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};
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Example board file:
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/ {
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emc@0,7001b000 {
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emc-timings-3 {
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nvidia,ram-code = <3>;
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timing-12750000 {
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clock-frequency = <12750000>;
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nvidia,emc-zcal-cnt-long = <0x00000042>;
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nvidia,emc-auto-cal-interval = <0x001fffff>;
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nvidia,emc-ctt-term-ctrl = <0x00000802>;
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nvidia,emc-cfg = <0x73240000>;
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nvidia,emc-cfg-2 = <0x000008c5>;
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nvidia,emc-sel-dpd-ctrl = <0x00040128>;
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nvidia,emc-bgbias-ctl0 = <0x00000008>;
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nvidia,emc-auto-cal-config = <0xa1430000>;
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nvidia,emc-auto-cal-config2 = <0x00000000>;
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nvidia,emc-auto-cal-config3 = <0x00000000>;
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nvidia,emc-mode-reset = <0x80001221>;
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nvidia,emc-mode-1 = <0x80100003>;
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nvidia,emc-mode-2 = <0x80200008>;
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nvidia,emc-mode-4 = <0x00000000>;
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nvidia,emc-configuration = <
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0x00000000 /* EMC_RC */
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0x00000003 /* EMC_RFC */
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0x00000000 /* EMC_RFC_SLR */
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0x00000000 /* EMC_RAS */
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0x00000000 /* EMC_RP */
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0x00000004 /* EMC_R2W */
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0x0000000a /* EMC_W2R */
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0x00000003 /* EMC_R2P */
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0x0000000b /* EMC_W2P */
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0x00000000 /* EMC_RD_RCD */
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0x00000000 /* EMC_WR_RCD */
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0x00000003 /* EMC_RRD */
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0x00000003 /* EMC_REXT */
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0x00000000 /* EMC_WEXT */
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0x00000006 /* EMC_WDV */
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0x00000006 /* EMC_WDV_MASK */
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0x00000006 /* EMC_QUSE */
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0x00000002 /* EMC_QUSE_WIDTH */
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0x00000000 /* EMC_IBDLY */
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0x00000005 /* EMC_EINPUT */
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0x00000005 /* EMC_EINPUT_DURATION */
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0x00010000 /* EMC_PUTERM_EXTRA */
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0x00000003 /* EMC_PUTERM_WIDTH */
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0x00000000 /* EMC_PUTERM_ADJ */
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0x00000000 /* EMC_CDB_CNTL_1 */
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0x00000000 /* EMC_CDB_CNTL_2 */
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0x00000000 /* EMC_CDB_CNTL_3 */
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0x00000004 /* EMC_QRST */
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0x0000000c /* EMC_QSAFE */
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0x0000000d /* EMC_RDV */
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0x0000000f /* EMC_RDV_MASK */
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0x00000060 /* EMC_REFRESH */
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0x00000000 /* EMC_BURST_REFRESH_NUM */
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0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
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0x00000002 /* EMC_PDEX2WR */
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0x00000002 /* EMC_PDEX2RD */
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0x00000001 /* EMC_PCHG2PDEN */
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0x00000000 /* EMC_ACT2PDEN */
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0x00000007 /* EMC_AR2PDEN */
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0x0000000f /* EMC_RW2PDEN */
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0x00000005 /* EMC_TXSR */
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0x00000005 /* EMC_TXSRDLL */
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0x00000004 /* EMC_TCKE */
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0x00000005 /* EMC_TCKESR */
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0x00000004 /* EMC_TPD */
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0x00000000 /* EMC_TFAW */
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0x00000000 /* EMC_TRPAB */
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0x00000005 /* EMC_TCLKSTABLE */
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0x00000005 /* EMC_TCLKSTOP */
|
||||
0x00000064 /* EMC_TREFBW */
|
||||
0x00000000 /* EMC_FBIO_CFG6 */
|
||||
0x00000000 /* EMC_ODT_WRITE */
|
||||
0x00000000 /* EMC_ODT_READ */
|
||||
0x106aa298 /* EMC_FBIO_CFG5 */
|
||||
0x002c00a0 /* EMC_CFG_DIG_DLL */
|
||||
0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS0 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS1 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS2 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS3 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS4 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS5 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS6 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS7 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS8 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS9 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS10 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS11 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS12 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS13 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS14 */
|
||||
0x00064000 /* EMC_DLL_XFORM_DQS15 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE0 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE1 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE2 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE3 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE4 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE5 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE6 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE7 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR0 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR1 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR2 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR3 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR4 */
|
||||
0x00000000 /* EMC_DLL_XFORM_ADDR5 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE8 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE9 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE10 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE11 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE12 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE13 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE14 */
|
||||
0x00000000 /* EMC_DLL_XFORM_QUSE15 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
|
||||
0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
|
||||
0x000fc000 /* EMC_DLL_XFORM_DQ0 */
|
||||
0x000fc000 /* EMC_DLL_XFORM_DQ1 */
|
||||
0x000fc000 /* EMC_DLL_XFORM_DQ2 */
|
||||
0x000fc000 /* EMC_DLL_XFORM_DQ3 */
|
||||
0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
|
||||
0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
|
||||
0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
|
||||
0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
|
||||
0x10000280 /* EMC_XM2CMDPADCTRL */
|
||||
0x00000000 /* EMC_XM2CMDPADCTRL4 */
|
||||
0x00111111 /* EMC_XM2CMDPADCTRL5 */
|
||||
0x00000000 /* EMC_XM2DQPADCTRL2 */
|
||||
0x00000000 /* EMC_XM2DQPADCTRL3 */
|
||||
0x77ffc081 /* EMC_XM2CLKPADCTRL */
|
||||
0x00000e0e /* EMC_XM2CLKPADCTRL2 */
|
||||
0x81f1f108 /* EMC_XM2COMPPADCTRL */
|
||||
0x07070004 /* EMC_XM2VTTGENPADCTRL */
|
||||
0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
|
||||
0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
|
||||
0x51451400 /* EMC_XM2DQSPADCTRL3 */
|
||||
0x00514514 /* EMC_XM2DQSPADCTRL4 */
|
||||
0x00514514 /* EMC_XM2DQSPADCTRL5 */
|
||||
0x51451400 /* EMC_XM2DQSPADCTRL6 */
|
||||
0x0000003f /* EMC_DSR_VTTGEN_DRV */
|
||||
0x00000007 /* EMC_TXDSRVTTGEN */
|
||||
0x00000000 /* EMC_FBIO_SPARE */
|
||||
0x00000042 /* EMC_ZCAL_WAIT_CNT */
|
||||
0x000e000e /* EMC_MRS_WAIT_CNT2 */
|
||||
0x00000000 /* EMC_CTT */
|
||||
0x00000003 /* EMC_CTT_DURATION */
|
||||
0x0000f2f3 /* EMC_CFG_PIPE */
|
||||
0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
|
||||
0x0000000a /* EMC_QPOP */
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -5,3 +5,13 @@ config TEGRA_MC
|
|||
help
|
||||
This driver supports the Memory Controller (MC) hardware found on
|
||||
NVIDIA Tegra SoCs.
|
||||
|
||||
config TEGRA124_EMC
|
||||
bool "NVIDIA Tegra124 External Memory Controller driver"
|
||||
default y
|
||||
depends on TEGRA_MC && ARCH_TEGRA_124_SOC
|
||||
help
|
||||
This driver is for the External Memory Controller (EMC) found on
|
||||
Tegra124 chips. The EMC controls the external DRAM on the board.
|
||||
This driver is required to change memory timings / clock rate for
|
||||
external memory.
|
||||
|
|
|
|||
|
|
@ -6,3 +6,5 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
|
|||
tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
|
||||
|
||||
obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
|
||||
|
||||
obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
|
||||
|
|
|
|||
|
|
@ -13,6 +13,9 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/sort.h>
|
||||
|
||||
#include <soc/tegra/fuse.h>
|
||||
|
||||
#include "mc.h"
|
||||
|
||||
|
|
@ -48,6 +51,9 @@
|
|||
#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
|
||||
#define MC_EMEM_ARB_MISC0 0xd8
|
||||
|
||||
#define MC_EMEM_ADR_CFG 0x54
|
||||
#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
|
||||
|
||||
static const struct of_device_id tegra_mc_of_match[] = {
|
||||
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
|
||||
{ .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
|
||||
|
|
@ -94,6 +100,130 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
|
||||
{
|
||||
unsigned int i;
|
||||
struct tegra_mc_timing *timing = NULL;
|
||||
|
||||
for (i = 0; i < mc->num_timings; i++) {
|
||||
if (mc->timings[i].rate == rate) {
|
||||
timing = &mc->timings[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!timing) {
|
||||
dev_err(mc->dev, "no memory timing registered for rate %lu\n",
|
||||
rate);
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < mc->soc->num_emem_regs; ++i)
|
||||
mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
|
||||
}
|
||||
|
||||
unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
|
||||
{
|
||||
u8 dram_count;
|
||||
|
||||
dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);
|
||||
dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;
|
||||
dram_count++;
|
||||
|
||||
return dram_count;
|
||||
}
|
||||
|
||||
static int load_one_timing(struct tegra_mc *mc,
|
||||
struct tegra_mc_timing *timing,
|
||||
struct device_node *node)
|
||||
{
|
||||
int err;
|
||||
u32 tmp;
|
||||
|
||||
err = of_property_read_u32(node, "clock-frequency", &tmp);
|
||||
if (err) {
|
||||
dev_err(mc->dev,
|
||||
"timing %s: failed to read rate\n", node->name);
|
||||
return err;
|
||||
}
|
||||
|
||||
timing->rate = tmp;
|
||||
timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
|
||||
sizeof(u32), GFP_KERNEL);
|
||||
if (!timing->emem_data)
|
||||
return -ENOMEM;
|
||||
|
||||
err = of_property_read_u32_array(node, "nvidia,emem-configuration",
|
||||
timing->emem_data,
|
||||
mc->soc->num_emem_regs);
|
||||
if (err) {
|
||||
dev_err(mc->dev,
|
||||
"timing %s: failed to read EMEM configuration\n",
|
||||
node->name);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int load_timings(struct tegra_mc *mc, struct device_node *node)
|
||||
{
|
||||
struct device_node *child;
|
||||
struct tegra_mc_timing *timing;
|
||||
int child_count = of_get_child_count(node);
|
||||
int i = 0, err;
|
||||
|
||||
mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
|
||||
GFP_KERNEL);
|
||||
if (!mc->timings)
|
||||
return -ENOMEM;
|
||||
|
||||
mc->num_timings = child_count;
|
||||
|
||||
for_each_child_of_node(node, child) {
|
||||
timing = &mc->timings[i++];
|
||||
|
||||
err = load_one_timing(mc, timing, child);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_mc_setup_timings(struct tegra_mc *mc)
|
||||
{
|
||||
struct device_node *node;
|
||||
u32 ram_code, node_ram_code;
|
||||
int err;
|
||||
|
||||
ram_code = tegra_read_ram_code();
|
||||
|
||||
mc->num_timings = 0;
|
||||
|
||||
for_each_child_of_node(mc->dev->of_node, node) {
|
||||
err = of_property_read_u32(node, "nvidia,ram-code",
|
||||
&node_ram_code);
|
||||
if (err || (node_ram_code != ram_code)) {
|
||||
of_node_put(node);
|
||||
continue;
|
||||
}
|
||||
|
||||
err = load_timings(mc, node);
|
||||
if (err)
|
||||
return err;
|
||||
of_node_put(node);
|
||||
break;
|
||||
}
|
||||
|
||||
if (mc->num_timings == 0)
|
||||
dev_warn(mc->dev,
|
||||
"no memory timings for RAM code %u registered\n",
|
||||
ram_code);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char *const status_names[32] = {
|
||||
[ 1] = "External interrupt",
|
||||
[ 6] = "EMEM address decode error",
|
||||
|
|
@ -251,6 +381,12 @@ static int tegra_mc_probe(struct platform_device *pdev)
|
|||
return err;
|
||||
}
|
||||
|
||||
err = tegra_mc_setup_timings(mc);
|
||||
if (err < 0) {
|
||||
dev_err(&pdev->dev, "failed to setup timings: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) {
|
||||
mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
|
||||
if (IS_ERR(mc->smmu)) {
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -15,6 +15,48 @@
|
|||
|
||||
#include "mc.h"
|
||||
|
||||
#define MC_EMEM_ARB_CFG 0x90
|
||||
#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
|
||||
#define MC_EMEM_ARB_TIMING_RCD 0x98
|
||||
#define MC_EMEM_ARB_TIMING_RP 0x9c
|
||||
#define MC_EMEM_ARB_TIMING_RC 0xa0
|
||||
#define MC_EMEM_ARB_TIMING_RAS 0xa4
|
||||
#define MC_EMEM_ARB_TIMING_FAW 0xa8
|
||||
#define MC_EMEM_ARB_TIMING_RRD 0xac
|
||||
#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
|
||||
#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
|
||||
#define MC_EMEM_ARB_TIMING_R2R 0xb8
|
||||
#define MC_EMEM_ARB_TIMING_W2W 0xbc
|
||||
#define MC_EMEM_ARB_TIMING_R2W 0xc0
|
||||
#define MC_EMEM_ARB_TIMING_W2R 0xc4
|
||||
#define MC_EMEM_ARB_DA_TURNS 0xd0
|
||||
#define MC_EMEM_ARB_DA_COVERS 0xd4
|
||||
#define MC_EMEM_ARB_MISC0 0xd8
|
||||
#define MC_EMEM_ARB_MISC1 0xdc
|
||||
#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
|
||||
|
||||
static const unsigned long tegra124_mc_emem_regs[] = {
|
||||
MC_EMEM_ARB_CFG,
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ,
|
||||
MC_EMEM_ARB_TIMING_RCD,
|
||||
MC_EMEM_ARB_TIMING_RP,
|
||||
MC_EMEM_ARB_TIMING_RC,
|
||||
MC_EMEM_ARB_TIMING_RAS,
|
||||
MC_EMEM_ARB_TIMING_FAW,
|
||||
MC_EMEM_ARB_TIMING_RRD,
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE,
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE,
|
||||
MC_EMEM_ARB_TIMING_R2R,
|
||||
MC_EMEM_ARB_TIMING_W2W,
|
||||
MC_EMEM_ARB_TIMING_R2W,
|
||||
MC_EMEM_ARB_TIMING_W2R,
|
||||
MC_EMEM_ARB_DA_TURNS,
|
||||
MC_EMEM_ARB_DA_COVERS,
|
||||
MC_EMEM_ARB_MISC0,
|
||||
MC_EMEM_ARB_MISC1,
|
||||
MC_EMEM_ARB_RING1_THROTTLE
|
||||
};
|
||||
|
||||
static const struct tegra_mc_client tegra124_mc_clients[] = {
|
||||
{
|
||||
.id = 0x00,
|
||||
|
|
@ -991,6 +1033,8 @@ const struct tegra_mc_soc tegra124_mc_soc = {
|
|||
.num_address_bits = 34,
|
||||
.atom_size = 32,
|
||||
.smmu = &tegra124_smmu_soc,
|
||||
.emem_regs = tegra124_mc_emem_regs,
|
||||
.num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
|
||||
};
|
||||
#endif /* CONFIG_ARCH_TEGRA_124_SOC */
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (c) 2014 NVIDIA Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_TEGRA_EMC_H__
|
||||
#define __SOC_TEGRA_EMC_H__
|
||||
|
||||
struct tegra_emc;
|
||||
|
||||
int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
|
||||
unsigned long rate);
|
||||
void tegra_emc_complete_timing_change(struct tegra_emc *emc,
|
||||
unsigned long rate);
|
||||
|
||||
#endif /* __SOC_TEGRA_EMC_H__ */
|
||||
|
|
@ -20,6 +20,12 @@ struct tegra_smmu_enable {
|
|||
unsigned int bit;
|
||||
};
|
||||
|
||||
struct tegra_mc_timing {
|
||||
unsigned long rate;
|
||||
|
||||
u32 *emem_data;
|
||||
};
|
||||
|
||||
/* latency allowance */
|
||||
struct tegra_mc_la {
|
||||
unsigned int reg;
|
||||
|
|
@ -90,7 +96,7 @@ struct tegra_mc_soc {
|
|||
const struct tegra_mc_client *clients;
|
||||
unsigned int num_clients;
|
||||
|
||||
const unsigned int *emem_regs;
|
||||
const unsigned long *emem_regs;
|
||||
unsigned int num_emem_regs;
|
||||
|
||||
unsigned int num_address_bits;
|
||||
|
|
@ -108,6 +114,12 @@ struct tegra_mc {
|
|||
|
||||
const struct tegra_mc_soc *soc;
|
||||
unsigned long tick;
|
||||
|
||||
struct tegra_mc_timing *timings;
|
||||
unsigned int num_timings;
|
||||
};
|
||||
|
||||
void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
|
||||
unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
|
||||
|
||||
#endif /* __SOC_TEGRA_MC_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue