clk: imx: clk-gate2: allow custom gate configuration
The 2-bit gates found i.MX and Vybrid SoC support different clock configuration: 0b00: clk disabled 0b01: clk enabled in RUN mode but disabled in WAIT and STOP mode 0b10: clk enabled in RUN, WAIT and STOP mode (only Vybrid) 0b11: clk enabled in RUN and WAIT mode For some clocks, we might want to configure different behaviour, e.g. a memory clock should be on even in STOP mode. Add a new function imx_clk_gate2_cgr which allow to configure specific gate values through the cgr_val parameter. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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0b55257ebc
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@ -31,6 +31,7 @@ struct clk_gate2 {
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struct clk_hw hw;
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void __iomem *reg;
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u8 bit_idx;
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u8 cgr_val;
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u8 flags;
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spinlock_t *lock;
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unsigned int *share_count;
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@ -50,7 +51,8 @@ static int clk_gate2_enable(struct clk_hw *hw)
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goto out;
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reg = readl(gate->reg);
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reg |= 3 << gate->bit_idx;
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reg &= ~(3 << gate->bit_idx);
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reg |= gate->cgr_val << gate->bit_idx;
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writel(reg, gate->reg);
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out:
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@ -125,7 +127,7 @@ static struct clk_ops clk_gate2_ops = {
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struct clk *clk_register_gate2(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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void __iomem *reg, u8 bit_idx, u8 cgr_val,
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u8 clk_gate2_flags, spinlock_t *lock,
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unsigned int *share_count)
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{
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@ -140,6 +142,7 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
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/* struct clk_gate2 assignments */
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gate->reg = reg;
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gate->bit_idx = bit_idx;
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gate->cgr_val = cgr_val;
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gate->flags = clk_gate2_flags;
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gate->lock = lock;
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gate->share_count = share_count;
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@ -41,7 +41,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
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struct clk *clk_register_gate2(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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void __iomem *reg, u8 bit_idx, u8 cgr_val,
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u8 clk_gate_flags, spinlock_t *lock,
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unsigned int *share_count);
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@ -55,7 +55,7 @@ static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
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void __iomem *reg, u8 shift)
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{
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return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0, &imx_ccm_lock, NULL);
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shift, 0x3, 0, &imx_ccm_lock, NULL);
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}
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static inline struct clk *imx_clk_gate2_shared(const char *name,
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@ -63,7 +63,14 @@ static inline struct clk *imx_clk_gate2_shared(const char *name,
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unsigned int *share_count)
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{
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return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, 0, &imx_ccm_lock, share_count);
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shift, 0x3, 0, &imx_ccm_lock, share_count);
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}
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static inline struct clk *imx_clk_gate2_cgr(const char *name, const char *parent,
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void __iomem *reg, u8 shift, u8 cgr_val)
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{
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return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
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shift, cgr_val, 0, &imx_ccm_lock, NULL);
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}
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struct clk *imx_clk_pfd(const char *name, const char *parent_name,
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