clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output
The configurable hdmi_ref output of the PLL block is derived from the tvdpll_594m clock signal via a configurable PLL post-divider. It is used as the PLL reference input to the HDMI PHY module. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -1095,6 +1095,11 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
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clk_data->clks[cku->id] = clk;
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clk_data->clks[cku->id] = clk;
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}
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}
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clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
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base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
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NULL);
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clk_data->clks[CLK_APMIXED_HDMI_REF] = clk;
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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if (r)
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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pr_err("%s(): could not register clock provider: %d\n",
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@ -176,7 +176,8 @@
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#define CLK_APMIXED_LVDSPLL 13
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#define CLK_APMIXED_LVDSPLL 13
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#define CLK_APMIXED_MSDCPLL2 14
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#define CLK_APMIXED_MSDCPLL2 14
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#define CLK_APMIXED_REF2USB_TX 15
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#define CLK_APMIXED_REF2USB_TX 15
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#define CLK_APMIXED_NR_CLK 16
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#define CLK_APMIXED_HDMI_REF 16
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#define CLK_APMIXED_NR_CLK 17
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/* INFRA_SYS */
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/* INFRA_SYS */
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