clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output

The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Philipp Zabel 2015-11-30 22:07:53 +01:00
parent 06445994fe
commit 4585945bf1
2 changed files with 7 additions and 1 deletions

View File

@ -1095,6 +1095,11 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
clk_data->clks[cku->id] = clk; clk_data->clks[cku->id] = clk;
} }
clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
NULL);
clk_data->clks[CLK_APMIXED_HDMI_REF] = clk;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r) if (r)
pr_err("%s(): could not register clock provider: %d\n", pr_err("%s(): could not register clock provider: %d\n",

View File

@ -176,7 +176,8 @@
#define CLK_APMIXED_LVDSPLL 13 #define CLK_APMIXED_LVDSPLL 13
#define CLK_APMIXED_MSDCPLL2 14 #define CLK_APMIXED_MSDCPLL2 14
#define CLK_APMIXED_REF2USB_TX 15 #define CLK_APMIXED_REF2USB_TX 15
#define CLK_APMIXED_NR_CLK 16 #define CLK_APMIXED_HDMI_REF 16
#define CLK_APMIXED_NR_CLK 17
/* INFRA_SYS */ /* INFRA_SYS */